2 * arch/arm/mach-omap/time.c
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Author: Greg Lonnon <glonnon@ridgerun.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 #include <linux/config.h>
31 #include <linux/kernel.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
37 #include <asm/system.h>
38 #include <asm/hardware.h>
42 #include <asm/mach/irq.h>
43 #include <asm/mach/time.h>
44 #include <asm/arch/clocks.h>
48 #define __noinstrument __attribute__ ((no_instrument_function))
52 u32 cntl; /* CNTL_TIMER, R/W */
53 u32 load_tim; /* LOAD_TIM, W */
54 u32 read_tim; /* READ_TIM, R */
57 #define mputimer_base(n) \
58 ((volatile mputimer_regs_t*)IO_ADDRESS(OMAP_MPUTIMER_BASE + \
59 (n)*OMAP_MPUTIMER_OFFSET))
61 static inline unsigned long timer32k_read(int reg) {
63 val = omap_readw(reg + OMAP_32kHz_TIMER_BASE);
66 static inline void timer32k_write(int reg,int val) {
67 omap_writew(val, reg + OMAP_32kHz_TIMER_BASE);
71 * How long is the timer interval? 100 HZ, right...
72 * IRQ rate = (TVR + 1) / 32768 seconds
73 * TVR = 32768 * IRQ_RATE -1
77 #define TIMER32k_PERIOD 326
78 //#define TIMER32k_PERIOD 0x7ff
80 static inline void start_timer32k(void) {
81 timer32k_write(TIMER32k_CR,
82 TIMER32k_TSS | TIMER32k_TRB |
83 TIMER32k_INT | TIMER32k_ARL);
86 #ifdef CONFIG_MACH_OMAP_PERSEUS2
88 * After programming PTV with 0 and setting the MPUTIM_CLOCK_ENABLE
89 * (external clock enable) bit, the timer count rate is 6.5 MHz (13
90 * MHZ input/2). !! The divider by 2 is undocumented !!
92 #define MPUTICKS_PER_SEC (13000000/2)
95 * After programming PTV with 0, the timer count rate is 6 MHz.
96 * WARNING! this must be an even number, or machinecycles_to_usecs
99 #define MPUTICKS_PER_SEC (12000000/2)
102 static int mputimer_started[3] = {0,0,0};
104 static inline void __noinstrument start_mputimer(int n,
105 unsigned long load_val)
107 volatile mputimer_regs_t* timer = mputimer_base(n);
109 mputimer_started[n] = 0;
110 timer->cntl = MPUTIM_CLOCK_ENABLE;
113 timer->load_tim = load_val;
115 timer->cntl = (MPUTIM_CLOCK_ENABLE | MPUTIM_AR | MPUTIM_ST);
116 mputimer_started[n] = 1;
119 static inline unsigned long __noinstrument
122 volatile mputimer_regs_t* timer = mputimer_base(n);
123 return (mputimer_started[n] ? timer->read_tim : 0);
126 void __noinstrument start_mputimer1(unsigned long load_val)
128 start_mputimer(0, load_val);
130 void __noinstrument start_mputimer2(unsigned long load_val)
132 start_mputimer(1, load_val);
134 void __noinstrument start_mputimer3(unsigned long load_val)
136 start_mputimer(2, load_val);
139 unsigned long __noinstrument read_mputimer1(void)
141 return read_mputimer(0);
143 unsigned long __noinstrument read_mputimer2(void)
145 return read_mputimer(1);
147 unsigned long __noinstrument read_mputimer3(void)
149 return read_mputimer(2);
152 unsigned long __noinstrument do_getmachinecycles(void)
154 return 0 - read_mputimer(0);
157 unsigned long __noinstrument machinecycles_to_usecs(unsigned long mputicks)
159 /* Round up to nearest usec */
160 return ((mputicks * 1000) / (MPUTICKS_PER_SEC / 2 / 1000) + 1) >> 1;
164 * This marks the time of the last system timer interrupt
165 * that was *processed by the ISR* (timer 2).
167 static unsigned long systimer_mark;
169 static unsigned long omap_gettimeoffset(void)
171 /* Return elapsed usecs since last system timer ISR */
172 return machinecycles_to_usecs(do_getmachinecycles() - systimer_mark);
176 omap_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
178 unsigned long now, ilatency;
181 * Mark the time at which the timer interrupt ocurred using
182 * timer1. We need to remove interrupt latency, which we can
183 * retrieve from the current system timer2 counter. Both the
184 * offset timer1 and the system timer2 are counting at 6MHz,
187 now = 0 - read_mputimer1();
188 ilatency = MPUTICKS_PER_SEC / 100 - read_mputimer2();
189 systimer_mark = now - ilatency;
196 static struct irqaction omap_timer_irq = {
197 .name = "OMAP Timer Tick",
198 .flags = SA_INTERRUPT,
199 .handler = omap_timer_interrupt
202 void __init omap_init_time(void)
204 /* Since we don't call request_irq, we must init the structure */
205 gettimeoffset = omap_gettimeoffset;
207 #ifdef OMAP1510_USE_32KHZ_TIMER
208 timer32k_write(TIMER32k_CR, 0x0);
209 timer32k_write(TIMER32k_TVR,TIMER32k_PERIOD);
210 setup_irq(INT_OS_32kHz_TIMER, &omap_timer_irq);
213 setup_irq(INT_TIMER2, &omap_timer_irq);
214 start_mputimer2(MPUTICKS_PER_SEC / 100 - 1);