1 /* linux/arch/arm/mach-s3c2410/clock.c
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 Clock control support
8 * Based on, and code from linux/arch/arm/mach-versatile/clock.c
10 ** Copyright (C) 2004 ARM Limited.
11 ** Written by Deep Blue Solutions Limited.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/errno.h>
34 #include <linux/err.h>
35 #include <linux/device.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
40 #include <asm/hardware.h>
41 #include <asm/atomic.h>
45 #include <asm/hardware/clock.h>
46 #include <asm/arch/regs-clock.h>
50 /* clock information */
52 unsigned long s3c24xx_xtal = 12*1000*1000; /* default 12MHz */
53 unsigned long s3c24xx_fclk;
54 unsigned long s3c24xx_hclk;
55 unsigned long s3c24xx_pclk;
57 static LIST_HEAD(clocks);
58 static DECLARE_MUTEX(clocks_sem);
63 void inline s3c24xx_clk_enable(unsigned int clocks, unsigned int enable)
68 local_irq_save(flags);
70 clkcon = __raw_readl(S3C2410_CLKCON);
76 /* ensure none of the special function bits set */
77 clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
79 __raw_writel(clkcon, S3C2410_CLKCON);
81 local_irq_restore(flags);
84 /* enable and disable calls for use with the clk struct */
86 static int clk_null_enable(struct clk *clk, int enable)
91 int s3c24xx_clkcon_enable(struct clk *clk, int enable)
93 s3c24xx_clk_enable(clk->ctrlbit, enable);
99 struct clk *clk_get(struct device *dev, const char *id)
102 struct clk *clk = ERR_PTR(-ENOENT);
105 idno = (dev == NULL) ? -1 : to_platform_device(dev)->id;
109 list_for_each_entry(p, &clocks, list) {
111 strcmp(id, p->name) == 0 &&
112 try_module_get(p->owner)) {
118 /* check for the case where a device was supplied, but the
119 * clock that was being searched for is not device specific */
122 list_for_each_entry(p, &clocks, list) {
123 if (p->id == -1 && strcmp(id, p->name) == 0 &&
124 try_module_get(p->owner)) {
135 void clk_put(struct clk *clk)
137 module_put(clk->owner);
140 int clk_enable(struct clk *clk)
145 return (clk->enable)(clk, 1);
148 void clk_disable(struct clk *clk)
151 (clk->enable)(clk, 0);
155 int clk_use(struct clk *clk)
157 atomic_inc(&clk->used);
162 void clk_unuse(struct clk *clk)
164 atomic_dec(&clk->used);
167 unsigned long clk_get_rate(struct clk *clk)
175 while (clk->parent != NULL && clk->rate == 0)
181 long clk_round_rate(struct clk *clk, unsigned long rate)
186 int clk_set_rate(struct clk *clk, unsigned long rate)
191 struct clk *clk_get_parent(struct clk *clk)
196 EXPORT_SYMBOL(clk_get);
197 EXPORT_SYMBOL(clk_put);
198 EXPORT_SYMBOL(clk_enable);
199 EXPORT_SYMBOL(clk_disable);
200 EXPORT_SYMBOL(clk_use);
201 EXPORT_SYMBOL(clk_unuse);
202 EXPORT_SYMBOL(clk_get_rate);
203 EXPORT_SYMBOL(clk_round_rate);
204 EXPORT_SYMBOL(clk_set_rate);
205 EXPORT_SYMBOL(clk_get_parent);
209 static struct clk clk_f = {
217 static struct clk clk_h = {
225 static struct clk clk_p = {
233 /* clocks that could be registered by external code */
235 struct clk s3c24xx_dclk0 = {
240 struct clk s3c24xx_dclk1 = {
245 struct clk s3c24xx_clkout0 = {
250 struct clk s3c24xx_clkout1 = {
255 struct clk s3c24xx_uclk = {
261 /* clock definitions */
263 static struct clk init_clocks[] = {
267 .enable = s3c24xx_clkcon_enable,
268 .ctrlbit = S3C2410_CLKCON_NAND
273 .enable = s3c24xx_clkcon_enable,
274 .ctrlbit = S3C2410_CLKCON_LCDC
276 { .name = "usb-host",
279 .enable = s3c24xx_clkcon_enable,
280 .ctrlbit = S3C2410_CLKCON_USBH
282 { .name = "usb-device",
285 .enable = s3c24xx_clkcon_enable,
286 .ctrlbit = S3C2410_CLKCON_USBD
290 .enable = s3c24xx_clkcon_enable,
291 .ctrlbit = S3C2410_CLKCON_PWMT
296 .enable = s3c24xx_clkcon_enable,
297 .ctrlbit = S3C2410_CLKCON_SDI
302 .enable = s3c24xx_clkcon_enable,
303 .ctrlbit = S3C2410_CLKCON_UART0
308 .enable = s3c24xx_clkcon_enable,
309 .ctrlbit = S3C2410_CLKCON_UART1
314 .enable = s3c24xx_clkcon_enable,
315 .ctrlbit = S3C2410_CLKCON_UART2
320 .enable = s3c24xx_clkcon_enable,
321 .ctrlbit = S3C2410_CLKCON_GPIO
326 .enable = s3c24xx_clkcon_enable,
327 .ctrlbit = S3C2410_CLKCON_RTC
332 .enable = s3c24xx_clkcon_enable,
333 .ctrlbit = S3C2410_CLKCON_ADC
338 .enable = s3c24xx_clkcon_enable,
339 .ctrlbit = S3C2410_CLKCON_IIC
344 .enable = s3c24xx_clkcon_enable,
345 .ctrlbit = S3C2410_CLKCON_IIS
350 .enable = s3c24xx_clkcon_enable,
351 .ctrlbit = S3C2410_CLKCON_SPI
353 { .name = "watchdog",
360 /* initialise the clock system */
362 int s3c24xx_register_clock(struct clk *clk)
364 clk->owner = THIS_MODULE;
365 atomic_set(&clk->used, 0);
367 if (clk->enable == NULL)
368 clk->enable = clk_null_enable;
370 /* add to the list of available clocks */
373 list_add(&clk->list, &clocks);
379 /* initalise all the clocks */
381 int __init s3c24xx_setup_clocks(void)
383 struct clk *clkp = init_clocks;
387 printk(KERN_INFO "S3C2410 Clock control, (c) 2004 Simtec Electronics\n");
389 /* initialise the main system clocks */
391 clk_h.rate = s3c24xx_hclk;
392 clk_p.rate = s3c24xx_pclk;
393 clk_f.rate = s3c24xx_fclk;
395 /* it looks like just setting the register here is not good
396 * enough, and causes the odd hang at initial boot time, so
397 * do all of them indivdually.
399 * I think disabling the LCD clock if the LCD is active is
400 * very dangerous, and therefore the bootloader should be
401 * careful to not enable the LCD clock if it is not needed.
403 * and of course, this looks neater
406 s3c24xx_clk_enable(S3C2410_CLKCON_NAND, 0);
407 s3c24xx_clk_enable(S3C2410_CLKCON_USBH, 0);
408 s3c24xx_clk_enable(S3C2410_CLKCON_USBD, 0);
409 s3c24xx_clk_enable(S3C2410_CLKCON_ADC, 0);
410 s3c24xx_clk_enable(S3C2410_CLKCON_IIC, 0);
411 s3c24xx_clk_enable(S3C2410_CLKCON_SPI, 0);
413 /* assume uart clocks are correctly setup */
415 /* register our clocks */
417 if (s3c24xx_register_clock(&clk_f) < 0)
418 printk(KERN_ERR "failed to register cpu fclk\n");
420 if (s3c24xx_register_clock(&clk_h) < 0)
421 printk(KERN_ERR "failed to register cpu hclk\n");
423 if (s3c24xx_register_clock(&clk_p) < 0)
424 printk(KERN_ERR "failed to register cpu pclk\n");
426 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
427 ret = s3c24xx_register_clock(clkp);
429 printk(KERN_ERR "Failed to register clock %s (%d)\n",