1 /* linux/arch/arm/mach-s3c2410/gpio.c
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * 13-Sep-2004 BJD Implemented change of MISCCR
24 * 14-Sep-2004 BJD Added getpin call
25 * 14-Sep-2004 BJD Fixed bug in setpin() call
26 * 30-Sep-2004 BJD Fixed cfgpin() mask bug
27 * 01-Oct-2004 BJD Added getcfg() to get pin configuration
28 * 01-Oct-2004 BJD Fixed mask bug in pullup() call
29 * 01-Oct-2004 BJD Added getirq() to turn pin into irqno
30 * 04-Oct-2004 BJD Added irq filter controls for GPIO
31 * 05-Nov-2004 BJD EXPORT_SYMBOL() added for all code
35 #include <linux/init.h>
36 #include <linux/module.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
40 #include <asm/hardware.h>
44 #include <asm/arch/regs-gpio.h>
46 void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
48 unsigned long base = S3C2410_GPIO_BASE(pin);
53 if (pin < S3C2410_GPIO_BANKB) {
54 mask = 1 << S3C2410_GPIO_OFFSET(pin);
56 mask = 3 << S3C2410_GPIO_OFFSET(pin)*2;
59 local_irq_save(flags);
61 con = __raw_readl(base + 0x00);
65 __raw_writel(con, base + 0x00);
67 local_irq_restore(flags);
70 EXPORT_SYMBOL(s3c2410_gpio_cfgpin);
72 unsigned int s3c2410_gpio_getcfg(unsigned int pin)
74 unsigned long base = S3C2410_GPIO_BASE(pin);
77 if (pin < S3C2410_GPIO_BANKB) {
78 mask = 1 << S3C2410_GPIO_OFFSET(pin);
80 mask = 3 << S3C2410_GPIO_OFFSET(pin)*2;
83 return __raw_readl(base) & mask;
86 EXPORT_SYMBOL(s3c2410_gpio_getcfg);
88 void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
90 unsigned long base = S3C2410_GPIO_BASE(pin);
91 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
95 if (pin < S3C2410_GPIO_BANKB)
98 local_irq_save(flags);
100 up = __raw_readl(base + 0x08);
103 __raw_writel(up, base + 0x08);
105 local_irq_restore(flags);
108 EXPORT_SYMBOL(s3c2410_gpio_pullup);
110 void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
112 unsigned long base = S3C2410_GPIO_BASE(pin);
113 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
117 local_irq_save(flags);
119 dat = __raw_readl(base + 0x04);
122 __raw_writel(dat, base + 0x04);
124 local_irq_restore(flags);
127 EXPORT_SYMBOL(s3c2410_gpio_setpin);
129 unsigned int s3c2410_gpio_getpin(unsigned int pin)
131 unsigned long base = S3C2410_GPIO_BASE(pin);
132 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
134 return __raw_readl(base + 0x04) & (1<< offs);
137 EXPORT_SYMBOL(s3c2410_gpio_getpin);
139 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
142 unsigned long misccr;
144 local_irq_save(flags);
145 misccr = __raw_readl(S3C2410_MISCCR);
148 __raw_writel(misccr, S3C2410_MISCCR);
149 local_irq_restore(flags);
154 EXPORT_SYMBOL(s3c2410_modify_misccr);
156 int s3c2410_gpio_getirq(unsigned int pin)
158 if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15_EINT23)
159 return -1; /* not valid interrupts */
161 if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7)
162 return -1; /* not valid pin */
164 if (pin < S3C2410_GPF4)
165 return (pin - S3C2410_GPF0) + IRQ_EINT0;
167 if (pin < S3C2410_GPG0)
168 return (pin - S3C2410_GPF4) + IRQ_EINT4;
170 return (pin - S3C2410_GPG0) + IRQ_EINT8;
173 EXPORT_SYMBOL(s3c2410_gpio_getirq);
175 int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
178 unsigned long reg = S3C2410_EINFLT0;
182 if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15)
187 pin -= S3C2410_GPG8_EINT16;
190 local_irq_save(flags);
192 /* update filter width and clock source */
194 val = __raw_readl(reg);
195 val &= ~(0xff << ((pin & 3) * 8));
196 val |= config << ((pin & 3) * 8);
197 __raw_writel(val, reg);
199 /* update filter enable */
201 val = __raw_readl(S3C2410_EXTINT2);
202 val &= ~(1 << ((pin * 4) + 3));
203 val |= on << ((pin * 4) + 3);
204 __raw_writel(val, S3C2410_EXTINT2);
206 local_irq_restore(flags);
211 EXPORT_SYMBOL(s3c2410_gpio_irqfilter);