1 /* linux/arch/arm/mach-s3c2410/irq.c
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * 22-Jul-2004 Ben Dooks <ben@simtec.co.uk>
23 * Fixed compile warnings
25 * 22-Jul-2004 Roc Wu <cooloney@yahoo.com.cn>
26 * Fixed s3c_extirq_type
28 * 21-Jul-2004 Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
29 * Addition of ADC/TC demux
31 * 04-Oct-2004 Klaus Fetscher <k.fetscher@fetron.de>
32 * Fix for set_irq_type() on low EINT numbers
34 * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
35 * Tidy up KF's patch and sort out new release
37 * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
38 * Add support for power management controls
40 * 04-Nov-2004 Ben Dooks
41 * Fix standard IRQ wake for EINT0..4 and RTC
44 #include <linux/init.h>
45 #include <linux/module.h>
46 #include <linux/interrupt.h>
47 #include <linux/ioport.h>
48 #include <linux/ptrace.h>
49 #include <linux/sysdev.h>
51 #include <asm/hardware.h>
55 #include <asm/mach/irq.h>
57 #include <asm/arch/regs-irq.h>
58 #include <asm/arch/regs-gpio.h>
65 #define EXTINT_OFF (IRQ_EINT4 - 4)
67 /* wakeup irq control */
71 /* state for IRQs over sleep */
73 /* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
75 * set bit to 1 in allow bitfield to enable the wakeup settings on it
78 unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
79 unsigned long s3c_irqwake_intmask = 0xffffffffL;
80 unsigned long s3c_irqwake_eintallow = 0x0000fff0L;
81 unsigned long s3c_irqwake_eintmask = 0xffffffffL;
84 s3c_irq_wake(unsigned int irqno, unsigned int state)
86 unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
88 if (!(s3c_irqwake_intallow & irqbit))
91 printk(KERN_INFO "wake %s for irq %d\n",
92 state ? "enabled" : "disabled", irqno);
95 s3c_irqwake_intmask |= irqbit;
97 s3c_irqwake_intmask &= ~irqbit;
103 s3c_irqext_wake(unsigned int irqno, unsigned int state)
105 unsigned long bit = 1L << (irqno - EXTINT_OFF);
107 if (!(s3c_irqwake_eintallow & bit))
110 printk(KERN_INFO "wake %s for irq %d\n",
111 state ? "enabled" : "disabled", irqno);
114 s3c_irqwake_eintmask |= bit;
116 s3c_irqwake_eintmask &= ~bit;
122 #define s3c_irqext_wake NULL
123 #define s3c_irq_wake NULL
128 s3c_irq_mask(unsigned int irqno)
134 mask = __raw_readl(S3C2410_INTMSK);
135 mask |= 1UL << irqno;
136 __raw_writel(mask, S3C2410_INTMSK);
140 s3c_irq_ack(unsigned int irqno)
142 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
144 __raw_writel(bitval, S3C2410_SRCPND);
145 __raw_writel(bitval, S3C2410_INTPND);
149 s3c_irq_maskack(unsigned int irqno)
151 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
154 mask = __raw_readl(S3C2410_INTMSK);
155 __raw_writel(mask|bitval, S3C2410_INTMSK);
157 __raw_writel(bitval, S3C2410_SRCPND);
158 __raw_writel(bitval, S3C2410_INTPND);
163 s3c_irq_unmask(unsigned int irqno)
167 if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
168 irqdbf2("s3c_irq_unmask %d\n", irqno);
172 mask = __raw_readl(S3C2410_INTMSK);
173 mask &= ~(1UL << irqno);
174 __raw_writel(mask, S3C2410_INTMSK);
177 static struct irqchip s3c_irq_level_chip = {
178 .ack = s3c_irq_maskack,
179 .mask = s3c_irq_mask,
180 .unmask = s3c_irq_unmask,
184 static struct irqchip s3c_irq_chip = {
186 .mask = s3c_irq_mask,
187 .unmask = s3c_irq_unmask,
196 s3c_irqext_mask(unsigned int irqno)
202 mask = __raw_readl(S3C2410_EINTMASK);
203 mask |= ( 1UL << irqno);
204 __raw_writel(mask, S3C2410_EINTMASK);
206 if (irqno <= (IRQ_EINT7 - EXTINT_OFF)) {
207 /* check to see if all need masking */
209 if ((mask & (0xf << 4)) == (0xf << 4)) {
210 /* all masked, mask the parent */
211 s3c_irq_mask(IRQ_EINT4t7);
214 /* todo: the same check as above for the rest of the irq regs...*/
220 s3c_irqext_ack(unsigned int irqno)
226 bit = 1UL << (irqno - EXTINT_OFF);
229 mask = __raw_readl(S3C2410_EINTMASK);
231 __raw_writel(bit, S3C2410_EINTPEND);
233 req = __raw_readl(S3C2410_EINTPEND);
236 /* not sure if we should be acking the parent irq... */
238 if (irqno <= IRQ_EINT7 ) {
239 if ((req & 0xf0) == 0)
240 s3c_irq_ack(IRQ_EINT4t7);
243 s3c_irq_ack(IRQ_EINT8t23);
248 s3c_irqext_unmask(unsigned int irqno)
254 mask = __raw_readl(S3C2410_EINTMASK);
255 mask &= ~( 1UL << irqno);
256 __raw_writel(mask, S3C2410_EINTMASK);
258 s3c_irq_unmask((irqno <= (IRQ_EINT7 - EXTINT_OFF)) ? IRQ_EINT4t7 : IRQ_EINT8t23);
262 s3c_irqext_type(unsigned int irq, unsigned int type)
264 unsigned long extint_reg;
265 unsigned long gpcon_reg;
266 unsigned long gpcon_offset, extint_offset;
267 unsigned long newvalue = 0, value;
269 if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3))
271 gpcon_reg = S3C2410_GPFCON;
272 extint_reg = S3C2410_EXTINT0;
273 gpcon_offset = (irq - IRQ_EINT0) * 2;
274 extint_offset = (irq - IRQ_EINT0) * 4;
276 else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7))
278 gpcon_reg = S3C2410_GPFCON;
279 extint_reg = S3C2410_EXTINT0;
280 gpcon_offset = (irq - (EXTINT_OFF)) * 2;
281 extint_offset = (irq - (EXTINT_OFF)) * 4;
283 else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15))
285 gpcon_reg = S3C2410_GPGCON;
286 extint_reg = S3C2410_EXTINT1;
287 gpcon_offset = (irq - IRQ_EINT8) * 2;
288 extint_offset = (irq - IRQ_EINT8) * 4;
290 else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23))
292 gpcon_reg = S3C2410_GPGCON;
293 extint_reg = S3C2410_EXTINT2;
294 gpcon_offset = (irq - IRQ_EINT8) * 2;
295 extint_offset = (irq - IRQ_EINT16) * 4;
299 /* Set the GPIO to external interrupt mode */
300 value = __raw_readl(gpcon_reg);
301 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
302 __raw_writel(value, gpcon_reg);
304 /* Set the external interrupt to pointed trigger type */
308 printk(KERN_WARNING "No edge setting!\n");
312 newvalue = S3C2410_EXTINT_RISEEDGE;
316 newvalue = S3C2410_EXTINT_FALLEDGE;
320 newvalue = S3C2410_EXTINT_BOTHEDGE;
324 newvalue = S3C2410_EXTINT_LOWLEV;
328 newvalue = S3C2410_EXTINT_HILEV;
332 printk(KERN_ERR "No such irq type %d", type);
336 value = __raw_readl(extint_reg);
337 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
338 __raw_writel(value, extint_reg);
343 static struct irqchip s3c_irqext_chip = {
344 .mask = s3c_irqext_mask,
345 .unmask = s3c_irqext_unmask,
346 .ack = s3c_irqext_ack,
347 .type = s3c_irqext_type,
348 .wake = s3c_irqext_wake
351 static struct irqchip s3c_irq_eint0t4 = {
353 .mask = s3c_irq_mask,
354 .unmask = s3c_irq_unmask,
355 .wake = s3c_irq_wake,
356 .type = s3c_irqext_type,
359 /* mask values for the parent registers for each of the interrupt types */
361 #define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0))
362 #define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0))
363 #define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0))
364 #define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
365 #define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
368 s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
372 unsigned long submask;
374 submask = __raw_readl(S3C2410_INTSUBMSK);
375 mask = __raw_readl(S3C2410_INTMSK);
377 submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
379 /* check to see if we need to mask the parent IRQ */
381 if ((submask & subcheck) == subcheck) {
382 __raw_writel(mask | parentbit, S3C2410_INTMSK);
385 /* write back masks */
386 __raw_writel(submask, S3C2410_INTSUBMSK);
391 s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
394 unsigned long submask;
396 submask = __raw_readl(S3C2410_INTSUBMSK);
397 mask = __raw_readl(S3C2410_INTMSK);
399 submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
402 /* write back masks */
403 __raw_writel(submask, S3C2410_INTSUBMSK);
404 __raw_writel(mask, S3C2410_INTMSK);
409 s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group)
411 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
413 s3c_irqsub_mask(irqno, parentmask, group);
415 __raw_writel(bit, S3C2410_SUBSRCPND);
417 /* only ack parent if we've got all the irqs (seems we must
418 * ack, all and hope that the irq system retriggers ok when
419 * the interrupt goes off again)
423 __raw_writel(parentmask, S3C2410_SRCPND);
424 __raw_writel(parentmask, S3C2410_INTPND);
432 s3c_irq_uart0_mask(unsigned int irqno)
434 s3c_irqsub_mask(irqno, INTMSK_UART0, 7);
438 s3c_irq_uart0_unmask(unsigned int irqno)
440 s3c_irqsub_unmask(irqno, INTMSK_UART0);
444 s3c_irq_uart0_ack(unsigned int irqno)
446 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
449 static struct irqchip s3c_irq_uart0 = {
450 .mask = s3c_irq_uart0_mask,
451 .unmask = s3c_irq_uart0_unmask,
452 .ack = s3c_irq_uart0_ack,
458 s3c_irq_uart1_mask(unsigned int irqno)
460 s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3);
464 s3c_irq_uart1_unmask(unsigned int irqno)
466 s3c_irqsub_unmask(irqno, INTMSK_UART1);
470 s3c_irq_uart1_ack(unsigned int irqno)
472 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
475 static struct irqchip s3c_irq_uart1 = {
476 .mask = s3c_irq_uart1_mask,
477 .unmask = s3c_irq_uart1_unmask,
478 .ack = s3c_irq_uart1_ack,
484 s3c_irq_uart2_mask(unsigned int irqno)
486 s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6);
490 s3c_irq_uart2_unmask(unsigned int irqno)
492 s3c_irqsub_unmask(irqno, INTMSK_UART2);
496 s3c_irq_uart2_ack(unsigned int irqno)
498 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
501 static struct irqchip s3c_irq_uart2 = {
502 .mask = s3c_irq_uart2_mask,
503 .unmask = s3c_irq_uart2_unmask,
504 .ack = s3c_irq_uart2_ack,
507 /* ADC and Touchscreen */
510 s3c_irq_adc_mask(unsigned int irqno)
512 s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9);
516 s3c_irq_adc_unmask(unsigned int irqno)
518 s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT);
522 s3c_irq_adc_ack(unsigned int irqno)
524 s3c_irqsub_maskack(irqno, INTMSK_ADCPARENT, 3 << 9);
527 static struct irqchip s3c_irq_adc = {
528 .mask = s3c_irq_adc_mask,
529 .unmask = s3c_irq_adc_unmask,
530 .ack = s3c_irq_adc_ack,
533 /* irq demux for adc */
534 static void s3c_irq_demux_adc(unsigned int irq,
535 struct irqdesc *desc,
536 struct pt_regs *regs)
538 unsigned int subsrc, submsk;
539 unsigned int offset = 9;
540 struct irqdesc *mydesc;
542 /* read the current pending interrupts, and the mask
543 * for what it is available */
545 subsrc = __raw_readl(S3C2410_SUBSRCPND);
546 submsk = __raw_readl(S3C2410_INTSUBMSK);
554 mydesc = irq_desc + IRQ_TC;
555 mydesc->handle( IRQ_TC, mydesc, regs);
558 mydesc = irq_desc + IRQ_ADC;
559 mydesc->handle(IRQ_ADC, mydesc, regs);
564 static void s3c_irq_demux_uart(unsigned int start,
565 struct pt_regs *regs)
567 unsigned int subsrc, submsk;
568 unsigned int offset = start - IRQ_S3CUART_RX0;
569 struct irqdesc *desc;
571 /* read the current pending interrupts, and the mask
572 * for what it is available */
574 subsrc = __raw_readl(S3C2410_SUBSRCPND);
575 submsk = __raw_readl(S3C2410_INTSUBMSK);
577 irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
578 start, offset, subsrc, submsk);
585 desc = irq_desc + start;
588 desc->handle(start, desc, regs);
593 desc->handle(start+1, desc, regs);
598 desc->handle(start+2, desc, regs);
602 /* uart demux entry points */
605 s3c_irq_demux_uart0(unsigned int irq,
606 struct irqdesc *desc,
607 struct pt_regs *regs)
610 s3c_irq_demux_uart(IRQ_S3CUART_RX0, regs);
614 s3c_irq_demux_uart1(unsigned int irq,
615 struct irqdesc *desc,
616 struct pt_regs *regs)
619 s3c_irq_demux_uart(IRQ_S3CUART_RX1, regs);
623 s3c_irq_demux_uart2(unsigned int irq,
624 struct irqdesc *desc,
625 struct pt_regs *regs)
628 s3c_irq_demux_uart(IRQ_S3CUART_RX2, regs);
633 * Initialise S3C2410 IRQ system
636 void __init s3c2410_init_irq(void)
643 irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
645 /* first, clear all interrupts pending... */
648 for (i = 0; i < 4; i++) {
649 pend = __raw_readl(S3C2410_EINTPEND);
651 if (pend == 0 || pend == last)
654 __raw_writel(pend, S3C2410_EINTPEND);
655 printk("irq: clearing pending ext status %08x\n", (int)pend);
660 for (i = 0; i < 4; i++) {
661 pend = __raw_readl(S3C2410_INTPND);
663 if (pend == 0 || pend == last)
666 __raw_writel(pend, S3C2410_SRCPND);
667 __raw_writel(pend, S3C2410_INTPND);
668 printk("irq: clearing pending status %08x\n", (int)pend);
673 for (i = 0; i < 4; i++) {
674 pend = __raw_readl(S3C2410_SUBSRCPND);
676 if (pend == 0 || pend == last)
679 printk("irq: clearing subpending status %08x\n", (int)pend);
680 __raw_writel(pend, S3C2410_SUBSRCPND);
684 /* register the main interrupts */
686 irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
688 for (irqno = IRQ_BATT_FLT; irqno <= IRQ_ADCPARENT; irqno++) {
689 /* set all the s3c2410 internal irqs */
692 /* deal with the special IRQs (cascaded) */
699 set_irq_chip(irqno, &s3c_irq_level_chip);
700 set_irq_handler(irqno, do_level_IRQ);
709 //irqdbf("registering irq %d (s3c irq)\n", irqno);
710 set_irq_chip(irqno, &s3c_irq_chip);
711 set_irq_handler(irqno, do_edge_IRQ);
712 set_irq_flags(irqno, IRQF_VALID);
716 /* setup the cascade irq handlers */
718 set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
719 set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
720 set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
721 set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
724 /* external interrupts */
726 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
727 irqdbf("registering irq %d (ext int)\n", irqno);
728 set_irq_chip(irqno, &s3c_irq_eint0t4);
729 set_irq_handler(irqno, do_edge_IRQ);
730 set_irq_flags(irqno, IRQF_VALID);
733 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
734 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
735 set_irq_chip(irqno, &s3c_irqext_chip);
736 set_irq_handler(irqno, do_edge_IRQ);
737 set_irq_flags(irqno, IRQF_VALID);
740 /* register the uart interrupts */
742 irqdbf("s3c2410: registering external interrupts\n");
744 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
745 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
746 set_irq_chip(irqno, &s3c_irq_uart0);
747 set_irq_handler(irqno, do_level_IRQ);
748 set_irq_flags(irqno, IRQF_VALID);
751 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
752 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
753 set_irq_chip(irqno, &s3c_irq_uart1);
754 set_irq_handler(irqno, do_level_IRQ);
755 set_irq_flags(irqno, IRQF_VALID);
758 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
759 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
760 set_irq_chip(irqno, &s3c_irq_uart2);
761 set_irq_handler(irqno, do_level_IRQ);
762 set_irq_flags(irqno, IRQF_VALID);
765 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
766 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
767 set_irq_chip(irqno, &s3c_irq_adc);
768 set_irq_handler(irqno, do_edge_IRQ);
769 set_irq_flags(irqno, IRQF_VALID);
772 irqdbf("s3c2410: registered interrupt handlers\n");