1 /* linux/arch/arm/mach-s3c2410/irq.c
3 * Copyright (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/interrupt.h>
26 #include <linux/ioport.h>
27 #include <linux/ptrace.h>
28 #include <linux/sysdev.h>
30 #include <asm/hardware.h>
34 #include <asm/mach/irq.h>
36 #include <asm/arch/regs-irq.h>
37 #include <asm/arch/regs-lcd.h>
40 #include <asm/debug-ll.h>
47 s3c_irq_mask(unsigned int irqno)
53 mask = __raw_readl(S3C2410_INTMSK);
55 __raw_writel(mask, S3C2410_INTMSK);
59 s3c_irq_ack(unsigned int irqno)
61 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
63 __raw_writel(bitval, S3C2410_SRCPND);
64 __raw_writel(bitval, S3C2410_INTPND);
68 s3c_irq_maskack(unsigned int irqno)
70 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
73 mask = __raw_readl(S3C2410_INTMSK);
74 __raw_writel(mask|bitval, S3C2410_INTMSK);
76 __raw_writel(bitval, S3C2410_SRCPND);
77 __raw_writel(bitval, S3C2410_INTPND);
82 s3c_irq_unmask(unsigned int irqno)
86 if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
87 irqdbf2("s3c_irq_unmask %d\n", irqno);
91 mask = __raw_readl(S3C2410_INTMSK);
92 mask &= ~(1UL << irqno);
93 __raw_writel(mask, S3C2410_INTMSK);
96 static struct irqchip s3c_irq_level_chip = {
97 .ack = s3c_irq_maskack,
99 .unmask = s3c_irq_unmask
102 static struct irqchip s3c_irq_chip = {
104 .mask = s3c_irq_mask,
105 .unmask = s3c_irq_unmask
112 #define EXTINT_OFF (IRQ_EINT4 - 4)
115 s3c_irqext_mask(unsigned int irqno)
121 mask = __raw_readl(S3C2410_EINTMASK);
122 mask |= ( 1UL << irqno);
123 __raw_writel(mask, S3C2410_EINTMASK);
125 if (irqno <= (IRQ_EINT7 - EXTINT_OFF)) {
126 /* check to see if all need masking */
128 if ((mask & (0xf << 4)) == (0xf << 4)) {
129 /* all masked, mask the parent */
130 s3c_irq_mask(IRQ_EINT4t7);
133 /* todo: the same check as above for the rest of the irq regs...*/
139 s3c_irqext_ack(unsigned int irqno)
145 bit = 1UL << (irqno - EXTINT_OFF);
148 mask = __raw_readl(S3C2410_EINTMASK);
150 __raw_writel(bit, S3C2410_EINTPEND);
152 req = __raw_readl(S3C2410_EINTPEND);
155 /* not sure if we should be acking the parent irq... */
157 if (irqno <= IRQ_EINT7 ) {
158 if ((req & 0xf0) == 0)
159 s3c_irq_ack(IRQ_EINT4t7);
162 s3c_irq_ack(IRQ_EINT8t23);
167 s3c_irqext_unmask(unsigned int irqno)
173 mask = __raw_readl(S3C2410_EINTMASK);
174 mask &= ~( 1UL << irqno);
175 __raw_writel(mask, S3C2410_EINTMASK);
177 s3c_irq_unmask((irqno <= (IRQ_EINT7 - EXTINT_OFF)) ? IRQ_EINT4t7 : IRQ_EINT8t23);
180 /* todo - put type handler in here */
183 s3c_irqext_type(unsigned int irq, unsigned int type)
185 irqdbf("s3c_irqext_type: called for irq %d, type %d\n", irq, type);
190 static struct irqchip s3c_irqext_chip = {
191 .mask = s3c_irqext_mask,
192 .unmask = s3c_irqext_unmask,
193 .ack = s3c_irqext_ack,
194 .type = s3c_irqext_type
197 /* mask values for the parent registers for each of the interrupt types */
199 #define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0))
200 #define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0))
201 #define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0))
202 #define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
203 #define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
206 s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
210 unsigned long submask;
212 submask = __raw_readl(S3C2410_INTSUBMSK);
213 mask = __raw_readl(S3C2410_INTMSK);
215 submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
217 /* check to see if we need to mask the parent IRQ */
219 if ((submask & subcheck) == subcheck) {
220 __raw_writel(mask | parentbit, S3C2410_INTMSK);
223 /* write back masks */
224 __raw_writel(submask, S3C2410_INTSUBMSK);
229 s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
232 unsigned long submask;
234 submask = __raw_readl(S3C2410_INTSUBMSK);
235 mask = __raw_readl(S3C2410_INTMSK);
237 submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
240 /* write back masks */
241 __raw_writel(submask, S3C2410_INTSUBMSK);
242 __raw_writel(mask, S3C2410_INTMSK);
247 s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group)
249 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
251 s3c_irqsub_mask(irqno, parentmask, group);
253 __raw_writel(bit, S3C2410_SUBSRCPND);
255 /* only ack parent if we've got all the irqs (seems we must
256 * ack, all and hope that the irq system retriggers ok when
257 * the interrupt goes off again)
261 __raw_writel(parentmask, S3C2410_SRCPND);
262 __raw_writel(parentmask, S3C2410_INTPND);
270 s3c_irq_uart0_mask(unsigned int irqno)
272 s3c_irqsub_mask(irqno, INTMSK_UART0, 7);
276 s3c_irq_uart0_unmask(unsigned int irqno)
278 s3c_irqsub_unmask(irqno, INTMSK_UART0);
282 s3c_irq_uart0_ack(unsigned int irqno)
284 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
287 static struct irqchip s3c_irq_uart0 = {
288 .mask = s3c_irq_uart0_mask,
289 .unmask = s3c_irq_uart0_unmask,
290 .ack = s3c_irq_uart0_ack,
296 s3c_irq_uart1_mask(unsigned int irqno)
298 s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3);
302 s3c_irq_uart1_unmask(unsigned int irqno)
304 s3c_irqsub_unmask(irqno, INTMSK_UART1);
308 s3c_irq_uart1_ack(unsigned int irqno)
310 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
313 static struct irqchip s3c_irq_uart1 = {
314 .mask = s3c_irq_uart1_mask,
315 .unmask = s3c_irq_uart1_unmask,
316 .ack = s3c_irq_uart1_ack,
322 s3c_irq_uart2_mask(unsigned int irqno)
324 s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6);
328 s3c_irq_uart2_unmask(unsigned int irqno)
330 s3c_irqsub_unmask(irqno, INTMSK_UART2);
334 s3c_irq_uart2_ack(unsigned int irqno)
336 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
339 static struct irqchip s3c_irq_uart2 = {
340 .mask = s3c_irq_uart2_mask,
341 .unmask = s3c_irq_uart2_unmask,
342 .ack = s3c_irq_uart2_ack,
345 /* ADC and Touchscreen */
348 s3c_irq_adc_mask(unsigned int irqno)
350 s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9);
354 s3c_irq_adc_unmask(unsigned int irqno)
356 s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT);
360 s3c_irq_adc_ack(unsigned int irqno)
362 s3c_irqsub_maskack(irqno, INTMSK_ADCPARENT, 3 << 9);
365 static struct irqchip s3c_irq_adc = {
366 .mask = s3c_irq_adc_mask,
367 .unmask = s3c_irq_adc_unmask,
368 .ack = s3c_irq_adc_ack,
375 s3c_irq_lcd_mask(unsigned int irqno)
381 s3c_irq_lcd_unmask(unsigned int irqno)
387 s3c_irq_lcd_ack(unsigned int irqno)
392 static struct irqchip s3c_irq_lcd = {
393 .mask = s3c_irq_lcd_mask,
394 .unmask = s3c_irq_lcd_unmask,
395 .ack = s3c_irq_lcd_ack,
402 static void s3c_irq_demux_uart(unsigned int start,
403 struct pt_regs *regs)
405 unsigned int subsrc, submsk;
406 unsigned int offset = start - IRQ_S3CUART_RX0;
407 struct irqdesc *desc;
409 /* read the current pending interrupts, and the mask
410 * for what it is available */
412 subsrc = __raw_readl(S3C2410_SUBSRCPND);
413 submsk = __raw_readl(S3C2410_INTSUBMSK);
415 irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
416 start, offset, subsrc, submsk);
423 desc = irq_desc + start;
426 desc->handle(start, desc, regs);
431 desc->handle(start+1, desc, regs);
436 desc->handle(start+2, desc, regs);
440 /* uart demux entry points */
443 s3c_irq_demux_uart0(unsigned int irq,
444 struct irqdesc *desc,
445 struct pt_regs *regs)
448 s3c_irq_demux_uart(IRQ_S3CUART_RX0, regs);
452 s3c_irq_demux_uart1(unsigned int irq,
453 struct irqdesc *desc,
454 struct pt_regs *regs)
457 s3c_irq_demux_uart(IRQ_S3CUART_RX1, regs);
461 s3c_irq_demux_uart2(unsigned int irq,
462 struct irqdesc *desc,
463 struct pt_regs *regs)
466 s3c_irq_demux_uart(IRQ_S3CUART_RX2, regs);
471 void __init s3c2410_init_irq(void)
477 irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
479 /* first, clear all interrupts pending... */
481 for (i = 0; i < 4; i++) {
482 pend = __raw_readl(S3C2410_EINTPEND);
485 __raw_writel(pend, S3C2410_EINTPEND);
486 printk("irq: clearing pending ext status %08x\n", (int)pend);
489 for (i = 0; i < 4; i++) {
490 pend = __raw_readl(S3C2410_INTPND);
493 __raw_writel(pend, S3C2410_SRCPND);
494 __raw_writel(pend, S3C2410_INTPND);
495 printk("irq: clearing pending status %08x\n", (int)pend);
498 for (i = 0; i < 4; i++) {
499 pend = __raw_readl(S3C2410_SUBSRCPND);
504 printk("irq: clearing subpending status %08x\n", (int)pend);
505 __raw_writel(pend, S3C2410_SUBSRCPND);
508 /* register the main interrupts */
510 irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
512 for (irqno = IRQ_EINT0; irqno < IRQ_ADCPARENT; irqno++) {
513 /* set all the s3c2410 internal irqs */
519 /* these are already dealt with, so should never
523 /* deal with the special IRQs (cascaded) */
530 set_irq_chip(irqno, &s3c_irq_level_chip);
531 set_irq_handler(irqno, do_level_IRQ);
540 //irqdbf("registering irq %d (s3c irq)\n", irqno);
541 set_irq_chip(irqno, &s3c_irq_chip);
542 set_irq_handler(irqno, do_edge_IRQ);
543 set_irq_flags(irqno, IRQF_VALID);
547 /* setup the cascade irq handlers */
549 set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
550 set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
551 set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
552 //set_irq_chained_handler(IRQ_LCD, s3c_irq_demux_);
553 //set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_);
556 /* external interrupts */
558 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
559 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
560 set_irq_chip(irqno, &s3c_irqext_chip);
561 set_irq_handler(irqno, do_edge_IRQ);
562 set_irq_flags(irqno, IRQF_VALID);
565 /* register the uart interrupts */
567 irqdbf("s3c2410: registering external interrupts\n");
569 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
570 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
571 set_irq_chip(irqno, &s3c_irq_uart0);
572 set_irq_handler(irqno, do_level_IRQ);
573 set_irq_flags(irqno, IRQF_VALID);
576 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
577 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
578 set_irq_chip(irqno, &s3c_irq_uart1);
579 set_irq_handler(irqno, do_level_IRQ);
580 set_irq_flags(irqno, IRQF_VALID);
583 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
584 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
585 set_irq_chip(irqno, &s3c_irq_uart2);
586 set_irq_handler(irqno, do_level_IRQ);
587 set_irq_flags(irqno, IRQF_VALID);
590 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
591 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
592 set_irq_chip(irqno, &s3c_irq_adc);
593 set_irq_handler(irqno, do_edge_IRQ);
594 set_irq_flags(irqno, IRQF_VALID);
597 irqdbf("s3c2410: registered interrupt handlers\n");