1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * http://www.simtec.co.uk/products/EB2410ITX/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * 14-Sep-2004 BJD USB power control
14 * 20-Aug-2004 BJD Added s3c2410_board struct
15 * 18-Aug-2004 BJD Added platform devices from default set
16 * 16-May-2003 BJD Created initial version
17 * 16-Aug-2003 BJD Fixed header files and copyright, added URL
18 * 05-Sep-2003 BJD Moved to v2.6 kernel
19 * 06-Jan-2003 BJD Updates for <arch/map.h>
20 * 18-Jan-2003 BJD Added serial port configuration
21 * 05-Oct-2004 BJD Power management code
22 * 04-Nov-2004 BJD Updated serial port clocks
23 * 04-Jan-2005 BJD New uart init call
24 * 10-Jan-2005 BJD Removed include of s3c2410.h
25 * 14-Jan-2005 BJD Add support for muitlple NAND devices
28 #include <linux/kernel.h>
29 #include <linux/types.h>
30 #include <linux/interrupt.h>
31 #include <linux/list.h>
32 #include <linux/timer.h>
33 #include <linux/init.h>
34 #include <linux/device.h>
36 #include <asm/mach/arch.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach/irq.h>
40 #include <asm/arch/bast-map.h>
41 #include <asm/arch/bast-irq.h>
43 #include <asm/hardware.h>
46 #include <asm/mach-types.h>
48 //#include <asm/debug-ll.h>
49 #include <asm/arch/regs-serial.h>
50 #include <asm/arch/regs-gpio.h>
51 #include <asm/arch/regs-mem.h>
52 #include <asm/arch/nand.h>
54 #include <linux/mtd/mtd.h>
55 #include <linux/mtd/nand.h>
56 #include <linux/mtd/nand_ecc.h>
57 #include <linux/mtd/partitions.h>
62 #include "usb-simtec.h"
65 #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
67 /* macros for virtual address mods for the io space entries */
68 #define VA_C5(item) ((item) + BAST_VAM_CS5)
69 #define VA_C4(item) ((item) + BAST_VAM_CS4)
70 #define VA_C3(item) ((item) + BAST_VAM_CS3)
71 #define VA_C2(item) ((item) + BAST_VAM_CS2)
73 /* macros to modify the physical addresses for io space */
75 #define PA_CS2(item) ((item) + S3C2410_CS2)
76 #define PA_CS3(item) ((item) + S3C2410_CS3)
77 #define PA_CS4(item) ((item) + S3C2410_CS4)
78 #define PA_CS5(item) ((item) + S3C2410_CS5)
80 static struct map_desc bast_iodesc[] __initdata = {
83 { S3C2410_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
84 { S3C2410_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
86 /* we could possibly compress the next set down into a set of smaller tables
87 * pagetables, but that would mean using an L2 section, and it still means
88 * we cannot actually feed the same register to an LDR due to 16K spacing
91 /* bast CPLD control registers, and external interrupt controls */
92 { BAST_VA_CTRL1, BAST_PA_CTRL1, SZ_1M, MT_DEVICE },
93 { BAST_VA_CTRL2, BAST_PA_CTRL2, SZ_1M, MT_DEVICE },
94 { BAST_VA_CTRL3, BAST_PA_CTRL3, SZ_1M, MT_DEVICE },
95 { BAST_VA_CTRL4, BAST_PA_CTRL4, SZ_1M, MT_DEVICE },
98 { BAST_VA_PC104_IRQREQ, BAST_PA_PC104_IRQREQ, SZ_1M, MT_DEVICE },
99 { BAST_VA_PC104_IRQRAW, BAST_PA_PC104_IRQRAW, SZ_1M, MT_DEVICE },
100 { BAST_VA_PC104_IRQMASK, BAST_PA_PC104_IRQMASK, SZ_1M, MT_DEVICE },
102 /* onboard 8bit lcd port */
104 { BAST_VA_LCD_RCMD1, BAST_PA_LCD_RCMD1, SZ_1M, MT_DEVICE },
105 { BAST_VA_LCD_WCMD1, BAST_PA_LCD_WCMD1, SZ_1M, MT_DEVICE },
106 { BAST_VA_LCD_RDATA1, BAST_PA_LCD_RDATA1, SZ_1M, MT_DEVICE },
107 { BAST_VA_LCD_WDATA1, BAST_PA_LCD_WDATA1, SZ_1M, MT_DEVICE },
108 { BAST_VA_LCD_RCMD2, BAST_PA_LCD_RCMD2, SZ_1M, MT_DEVICE },
109 { BAST_VA_LCD_WCMD2, BAST_PA_LCD_WCMD2, SZ_1M, MT_DEVICE },
110 { BAST_VA_LCD_RDATA2, BAST_PA_LCD_RDATA2, SZ_1M, MT_DEVICE },
111 { BAST_VA_LCD_WDATA2, BAST_PA_LCD_WDATA2, SZ_1M, MT_DEVICE },
113 /* peripheral space... one for each of fast/slow/byte/16bit */
114 /* note, ide is only decoded in word space, even though some registers
118 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
119 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
120 { VA_C2(BAST_VA_ASIXNET), PA_CS3(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE },
121 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
122 { VA_C2(BAST_VA_DM9000), PA_CS2(BAST_PA_DM9000), SZ_1M, MT_DEVICE },
123 { VA_C2(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
124 { VA_C2(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
125 { VA_C2(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
126 { VA_C2(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
129 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
130 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
131 { VA_C3(BAST_VA_ASIXNET), PA_CS3(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE },
132 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
133 { VA_C3(BAST_VA_DM9000), PA_CS3(BAST_PA_DM9000), SZ_1M, MT_DEVICE },
134 { VA_C3(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
135 { VA_C3(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
136 { VA_C3(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
137 { VA_C3(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
140 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
141 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
142 { VA_C4(BAST_VA_ASIXNET), PA_CS5(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE },
143 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
144 { VA_C4(BAST_VA_DM9000), PA_CS4(BAST_PA_DM9000), SZ_1M, MT_DEVICE },
145 { VA_C4(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
146 { VA_C4(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
147 { VA_C4(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
148 { VA_C4(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
151 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
152 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
153 { VA_C5(BAST_VA_ASIXNET), PA_CS5(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE },
154 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
155 { VA_C5(BAST_VA_DM9000), PA_CS5(BAST_PA_DM9000), SZ_1M, MT_DEVICE },
156 { VA_C5(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
157 { VA_C5(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
158 { VA_C5(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
159 { VA_C5(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
162 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
163 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
164 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
166 static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
182 static struct s3c2410_uartcfg bast_uartcfgs[] = {
189 .clocks = bast_serial_clocks,
190 .clocks_size = ARRAY_SIZE(bast_serial_clocks)
198 .clocks = bast_serial_clocks,
199 .clocks_size = ARRAY_SIZE(bast_serial_clocks)
201 /* port 2 is not actually used */
208 .clocks = bast_serial_clocks,
209 .clocks_size = ARRAY_SIZE(bast_serial_clocks)
213 /* NOR Flash on BAST board */
215 static struct resource bast_nor_resource[] = {
217 .start = S3C2410_CS1 + 0x4000000,
218 .end = S3C2410_CS1 + 0x4000000 + (32*1024*1024) - 1,
219 .flags = IORESOURCE_MEM,
223 static struct platform_device bast_device_nor = {
226 .num_resources = ARRAY_SIZE(bast_nor_resource),
227 .resource = bast_nor_resource,
230 /* NAND Flash on BAST board */
233 static int smartmedia_map[] = { 0 };
234 static int chip0_map[] = { 1 };
235 static int chip1_map[] = { 2 };
236 static int chip2_map[] = { 3 };
238 struct mtd_partition bast_default_nand_part[] = {
240 .name = "Boot Agent",
246 .size = SZ_4M - SZ_16K,
252 .size = MTDPART_SIZ_FULL,
256 /* the bast has 4 selectable slots for nand-flash, the three
257 * on-board chip areas, as well as the external SmartMedia
260 * Note, there is no current hot-plug support for the SmartMedia
264 static struct s3c2410_nand_set bast_nand_sets[] = {
266 .name = "SmartMedia",
268 .nr_map = smartmedia_map,
269 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
270 .partitions = bast_default_nand_part
276 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
277 .partitions = bast_default_nand_part
283 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
284 .partitions = bast_default_nand_part
290 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
291 .partitions = bast_default_nand_part
295 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
299 slot = set->nr_map[slot] & 3;
301 pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
302 slot, set, set->nr_map);
304 tmp = __raw_readb(BAST_VA_CTRL2);
305 tmp &= BAST_CPLD_CTLR2_IDERST;
307 tmp |= BAST_CPLD_CTRL2_WNAND;
309 pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
311 __raw_writeb(tmp, BAST_VA_CTRL2);
314 static struct s3c2410_platform_nand bast_nand_info = {
318 .nr_sets = ARRAY_SIZE(bast_nand_sets),
319 .sets = bast_nand_sets,
320 .select_chip = bast_nand_select,
324 /* Standard BAST devices */
326 static struct platform_device *bast_devices[] __initdata = {
337 static struct clk *bast_clocks[] = {
345 static struct s3c24xx_board bast_board __initdata = {
346 .devices = bast_devices,
347 .devices_count = ARRAY_SIZE(bast_devices),
348 .clocks = bast_clocks,
349 .clocks_count = ARRAY_SIZE(bast_clocks)
352 void __init bast_map_io(void)
354 /* initialise the clocks */
356 s3c24xx_dclk0.parent = NULL;
357 s3c24xx_dclk0.rate = 12*1000*1000;
359 s3c24xx_dclk1.parent = NULL;
360 s3c24xx_dclk1.rate = 24*1000*1000;
362 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
363 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
365 s3c24xx_uclk.parent = &s3c24xx_clkout1;
367 s3c_device_nand.dev.platform_data = &bast_nand_info;
369 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
370 s3c24xx_init_clocks(0);
371 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
372 s3c24xx_set_board(&bast_board);
376 void __init bast_init_irq(void)
385 * enable the power management functions for the EB2410ITX
388 static __init void bast_init_machine(void)
390 unsigned long gstatus4;
392 printk(KERN_INFO "BAST Power Manangement" COPYRIGHT "\n");
394 gstatus4 = (__raw_readl(S3C2410_BANKCON7) & 0x3) << 30;
395 gstatus4 |= (__raw_readl(S3C2410_BANKCON6) & 0x3) << 28;
396 gstatus4 |= (__raw_readl(S3C2410_BANKSIZE) & S3C2410_BANKSIZE_MASK);
398 __raw_writel(gstatus4, S3C2410_GSTATUS4);
404 #define bast_init_machine NULL
408 MACHINE_START(BAST, "Simtec-BAST")
409 MAINTAINER("Ben Dooks <ben@simtec.co.uk>")
410 BOOT_MEM(S3C2410_SDRAM_PA, S3C2410_PA_UART, S3C2410_VA_UART)
411 BOOT_PARAMS(S3C2410_SDRAM_PA + 0x100)
413 INITIRQ(bast_init_irq)
414 .init_machine = bast_init_machine,
415 .timer = &s3c24xx_timer,