1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * http://www.simtec.co.uk/products/EB2410ITX/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * 14-Sep-2004 BJD USB power control
14 * 20-Aug-2004 BJD Added s3c2410_board struct
15 * 18-Aug-2004 BJD Added platform devices from default set
16 * 16-May-2003 BJD Created initial version
17 * 16-Aug-2003 BJD Fixed header files and copyright, added URL
18 * 05-Sep-2003 BJD Moved to v2.6 kernel
19 * 06-Jan-2003 BJD Updates for <arch/map.h>
20 * 18-Jan-2003 BJD Added serial port configuration
21 * 05-Oct-2004 BJD Power management code
22 * 04-Nov-2004 BJD Updated serial port clocks
25 #include <linux/kernel.h>
26 #include <linux/types.h>
27 #include <linux/interrupt.h>
28 #include <linux/list.h>
29 #include <linux/timer.h>
30 #include <linux/init.h>
31 #include <linux/device.h>
33 #include <asm/mach/arch.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach/irq.h>
37 #include <asm/arch/bast-map.h>
38 #include <asm/arch/bast-irq.h>
40 #include <asm/hardware.h>
43 #include <asm/mach-types.h>
45 //#include <asm/debug-ll.h>
46 #include <asm/arch/regs-serial.h>
47 #include <asm/arch/regs-gpio.h>
48 #include <asm/arch/regs-mem.h>
54 #include "usb-simtec.h"
57 #define COPYRIGHT ", (c) 2004 Simtec Electronics"
59 /* macros for virtual address mods for the io space entries */
60 #define VA_C5(item) ((item) + BAST_VAM_CS5)
61 #define VA_C4(item) ((item) + BAST_VAM_CS4)
62 #define VA_C3(item) ((item) + BAST_VAM_CS3)
63 #define VA_C2(item) ((item) + BAST_VAM_CS2)
65 /* macros to modify the physical addresses for io space */
67 #define PA_CS2(item) ((item) + S3C2410_CS2)
68 #define PA_CS3(item) ((item) + S3C2410_CS3)
69 #define PA_CS4(item) ((item) + S3C2410_CS4)
70 #define PA_CS5(item) ((item) + S3C2410_CS5)
72 static struct map_desc bast_iodesc[] __initdata = {
75 { S3C2410_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
76 { S3C2410_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
78 /* we could possibly compress the next set down into a set of smaller tables
79 * pagetables, but that would mean using an L2 section, and it still means
80 * we cannot actually feed the same register to an LDR due to 16K spacing
83 /* bast CPLD control registers, and external interrupt controls */
84 { BAST_VA_CTRL1, BAST_PA_CTRL1, SZ_1M, MT_DEVICE },
85 { BAST_VA_CTRL2, BAST_PA_CTRL2, SZ_1M, MT_DEVICE },
86 { BAST_VA_CTRL3, BAST_PA_CTRL3, SZ_1M, MT_DEVICE },
87 { BAST_VA_CTRL4, BAST_PA_CTRL4, SZ_1M, MT_DEVICE },
90 { BAST_VA_PC104_IRQREQ, BAST_PA_PC104_IRQREQ, SZ_1M, MT_DEVICE },
91 { BAST_VA_PC104_IRQRAW, BAST_PA_PC104_IRQRAW, SZ_1M, MT_DEVICE },
92 { BAST_VA_PC104_IRQMASK, BAST_PA_PC104_IRQMASK, SZ_1M, MT_DEVICE },
94 /* onboard 8bit lcd port */
96 { BAST_VA_LCD_RCMD1, BAST_PA_LCD_RCMD1, SZ_1M, MT_DEVICE },
97 { BAST_VA_LCD_WCMD1, BAST_PA_LCD_WCMD1, SZ_1M, MT_DEVICE },
98 { BAST_VA_LCD_RDATA1, BAST_PA_LCD_RDATA1, SZ_1M, MT_DEVICE },
99 { BAST_VA_LCD_WDATA1, BAST_PA_LCD_WDATA1, SZ_1M, MT_DEVICE },
100 { BAST_VA_LCD_RCMD2, BAST_PA_LCD_RCMD2, SZ_1M, MT_DEVICE },
101 { BAST_VA_LCD_WCMD2, BAST_PA_LCD_WCMD2, SZ_1M, MT_DEVICE },
102 { BAST_VA_LCD_RDATA2, BAST_PA_LCD_RDATA2, SZ_1M, MT_DEVICE },
103 { BAST_VA_LCD_WDATA2, BAST_PA_LCD_WDATA2, SZ_1M, MT_DEVICE },
105 /* peripheral space... one for each of fast/slow/byte/16bit */
106 /* note, ide is only decoded in word space, even though some registers
110 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
111 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
112 { VA_C2(BAST_VA_ASIXNET), PA_CS3(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE },
113 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
114 { VA_C2(BAST_VA_DM9000), PA_CS2(BAST_PA_DM9000), SZ_1M, MT_DEVICE },
115 { VA_C2(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
116 { VA_C2(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
117 { VA_C2(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
118 { VA_C2(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
121 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
122 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
123 { VA_C3(BAST_VA_ASIXNET), PA_CS3(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE },
124 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
125 { VA_C3(BAST_VA_DM9000), PA_CS3(BAST_PA_DM9000), SZ_1M, MT_DEVICE },
126 { VA_C3(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
127 { VA_C3(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
128 { VA_C3(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
129 { VA_C3(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
132 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
133 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
134 { VA_C4(BAST_VA_ASIXNET), PA_CS5(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE },
135 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
136 { VA_C4(BAST_VA_DM9000), PA_CS4(BAST_PA_DM9000), SZ_1M, MT_DEVICE },
137 { VA_C4(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
138 { VA_C4(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
139 { VA_C4(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
140 { VA_C4(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
143 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
144 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
145 { VA_C5(BAST_VA_ASIXNET), PA_CS5(BAST_PA_ASIXNET), SZ_1M, MT_DEVICE },
146 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
147 { VA_C5(BAST_VA_DM9000), PA_CS5(BAST_PA_DM9000), SZ_1M, MT_DEVICE },
148 { VA_C5(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
149 { VA_C5(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
150 { VA_C5(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
151 { VA_C5(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
154 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
155 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
156 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
158 static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
174 static struct s3c2410_uartcfg bast_uartcfgs[] = {
181 .clocks = bast_serial_clocks,
182 .clocks_size = ARRAY_SIZE(bast_serial_clocks)
190 .clocks = bast_serial_clocks,
191 .clocks_size = ARRAY_SIZE(bast_serial_clocks)
193 /* port 2 is not actually used */
200 .clocks = bast_serial_clocks,
201 .clocks_size = ARRAY_SIZE(bast_serial_clocks)
205 /* NOR Flash on BAST board */
207 static struct resource bast_nor_resource[] = {
209 .start = S3C2410_CS1 + 0x4000000,
210 .end = S3C2410_CS1 + 0x4000000 + (32*1024*1024) - 1,
211 .flags = IORESOURCE_MEM,
215 static struct platform_device bast_device_nor = {
218 .num_resources = ARRAY_SIZE(bast_nor_resource),
219 .resource = bast_nor_resource,
222 /* Standard BAST devices */
224 static struct platform_device *bast_devices[] __initdata = {
234 static struct clk *bast_clocks[] = {
242 static struct s3c24xx_board bast_board __initdata = {
243 .devices = bast_devices,
244 .devices_count = ARRAY_SIZE(bast_devices),
245 .clocks = bast_clocks,
246 .clocks_count = ARRAY_SIZE(bast_clocks)
249 void __init bast_map_io(void)
251 /* initialise the clocks */
253 s3c24xx_dclk0.parent = NULL;
254 s3c24xx_dclk0.rate = 12*1000*1000;
256 s3c24xx_dclk1.parent = NULL;
257 s3c24xx_dclk1.rate = 24*1000*1000;
259 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
260 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
262 s3c24xx_uclk.parent = &s3c24xx_clkout1;
264 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
265 s3c2410_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
266 s3c24xx_set_board(&bast_board);
270 void __init bast_init_irq(void)
279 * enable the power management functions for the EB2410ITX
282 static __init void bast_init_machine(void)
284 unsigned long gstatus4;
286 printk(KERN_INFO "BAST Power Manangement" COPYRIGHT "\n");
288 gstatus4 = (__raw_readl(S3C2410_BANKCON7) & 0x3) << 30;
289 gstatus4 |= (__raw_readl(S3C2410_BANKCON6) & 0x3) << 28;
290 gstatus4 |= (__raw_readl(S3C2410_BANKSIZE) & S3C2410_BANKSIZE_MASK);
292 __raw_writel(gstatus4, S3C2410_GSTATUS4);
298 #define bast_init_machine NULL
302 MACHINE_START(BAST, "Simtec-BAST")
303 MAINTAINER("Ben Dooks <ben@simtec.co.uk>")
304 BOOT_MEM(S3C2410_SDRAM_PA, S3C2410_PA_UART, S3C2410_VA_UART)
305 BOOT_PARAMS(S3C2410_SDRAM_PA + 0x100)
307 INITIRQ(bast_init_irq)
308 .init_machine = bast_init_machine,
309 .timer = &s3c2410_timer,