1 /* linux/arch/arm/mach-s3c2410/mach-vr1000.c
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * Machine support for Thorcom VR1000 board. Designed for Thorcom by
7 * Simtec Electronics, http://www.simtec.co.uk/
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * 14-Sep-2004 BJD USB Power control
15 * 04-Sep-2004 BJD Added new uart init, and io init
16 * 21-Aug-2004 BJD Added struct s3c2410_board
17 * 06-Aug-2004 BJD Fixed call to time initialisation
18 * 05-Apr-2004 BJD Copied to make mach-vr1000.c
19 * 18-Oct-2004 BJD Updated board struct
20 * 04-Nov-2004 BJD Clock and serial configuration update
22 * 04-Jan-2005 BJD Updated uart init call
23 * 10-Jan-2005 BJD Removed include of s3c2410.h
24 * 14-Jan-2005 BJD Added clock init
25 * 15-Jan-2005 BJD Add serial port device definition
26 * 20-Jan-2005 BJD Use UPF_IOREMAP for ports
29 #include <linux/kernel.h>
30 #include <linux/types.h>
31 #include <linux/interrupt.h>
32 #include <linux/list.h>
33 #include <linux/timer.h>
34 #include <linux/init.h>
36 #include <linux/serial.h>
37 #include <linux/tty.h>
38 #include <linux/serial_8250.h>
39 #include <linux/serial_reg.h>
41 #include <asm/mach/arch.h>
42 #include <asm/mach/map.h>
43 #include <asm/mach/irq.h>
45 #include <asm/arch/bast-map.h>
46 #include <asm/arch/vr1000-map.h>
47 #include <asm/arch/vr1000-irq.h>
48 #include <asm/arch/vr1000-cpld.h>
50 #include <asm/hardware.h>
53 #include <asm/mach-types.h>
55 //#include <asm/debug-ll.h>
56 #include <asm/arch/regs-serial.h>
61 #include "usb-simtec.h"
63 /* macros for virtual address mods for the io space entries */
64 #define VA_C5(item) ((item) + BAST_VAM_CS5)
65 #define VA_C4(item) ((item) + BAST_VAM_CS4)
66 #define VA_C3(item) ((item) + BAST_VAM_CS3)
67 #define VA_C2(item) ((item) + BAST_VAM_CS2)
69 /* macros to modify the physical addresses for io space */
71 #define PA_CS2(item) ((item) + S3C2410_CS2)
72 #define PA_CS3(item) ((item) + S3C2410_CS3)
73 #define PA_CS4(item) ((item) + S3C2410_CS4)
74 #define PA_CS5(item) ((item) + S3C2410_CS5)
76 static struct map_desc vr1000_iodesc[] __initdata = {
79 { S3C2410_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
80 { S3C2410_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
82 /* we could possibly compress the next set down into a set of smaller tables
83 * pagetables, but that would mean using an L2 section, and it still means
84 * we cannot actually feed the same register to an LDR due to 16K spacing
87 /* bast CPLD control registers, and external interrupt controls */
88 { VR1000_VA_CTRL1, VR1000_PA_CTRL1, SZ_1M, MT_DEVICE },
89 { VR1000_VA_CTRL2, VR1000_PA_CTRL2, SZ_1M, MT_DEVICE },
90 { VR1000_VA_CTRL3, VR1000_PA_CTRL3, SZ_1M, MT_DEVICE },
91 { VR1000_VA_CTRL4, VR1000_PA_CTRL4, SZ_1M, MT_DEVICE },
93 /* peripheral space... one for each of fast/slow/byte/16bit */
94 /* note, ide is only decoded in word space, even though some registers
98 { VA_C2(VR1000_VA_DM9000), PA_CS2(VR1000_PA_DM9000), SZ_1M, MT_DEVICE },
99 { VA_C2(VR1000_VA_IDEPRI), PA_CS3(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
100 { VA_C2(VR1000_VA_IDESEC), PA_CS3(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
101 { VA_C2(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
102 { VA_C2(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
105 { VA_C3(VR1000_VA_DM9000), PA_CS3(VR1000_PA_DM9000), SZ_1M, MT_DEVICE },
106 { VA_C3(VR1000_VA_IDEPRI), PA_CS3(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
107 { VA_C3(VR1000_VA_IDESEC), PA_CS3(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
108 { VA_C3(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
109 { VA_C3(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
112 { VA_C4(VR1000_VA_DM9000), PA_CS4(VR1000_PA_DM9000), SZ_1M, MT_DEVICE },
113 { VA_C4(VR1000_VA_IDEPRI), PA_CS5(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
114 { VA_C4(VR1000_VA_IDESEC), PA_CS5(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
115 { VA_C4(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
116 { VA_C4(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
119 { VA_C5(VR1000_VA_DM9000), PA_CS5(VR1000_PA_DM9000), SZ_1M, MT_DEVICE },
120 { VA_C5(VR1000_VA_IDEPRI), PA_CS5(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
121 { VA_C5(VR1000_VA_IDESEC), PA_CS5(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
122 { VA_C5(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
123 { VA_C5(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
126 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
127 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
128 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
130 /* uart clock source(s) */
132 static struct s3c24xx_uart_clksrc vr1000_serial_clocks[] = {
147 static struct s3c2410_uartcfg vr1000_uartcfgs[] = {
154 .clocks = vr1000_serial_clocks,
155 .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
163 .clocks = vr1000_serial_clocks,
164 .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
166 /* port 2 is not actually used */
173 .clocks = vr1000_serial_clocks,
174 .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
179 /* definitions for the vr1000 extra 16550 serial ports */
181 #define VR1000_BAUDBASE (3692307)
183 #define VR1000_SERIAL_MAPBASE(x) (VR1000_PA_SERIAL + 0x80 + ((x) << 5))
185 static struct plat_serial8250_port serial_platform_data[] = {
187 .mapbase = VR1000_SERIAL_MAPBASE(0),
188 .irq = IRQ_VR1000_SERIAL + 0,
189 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
192 .uartclk = VR1000_BAUDBASE,
195 .mapbase = VR1000_SERIAL_MAPBASE(1),
196 .irq = IRQ_VR1000_SERIAL + 1,
197 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
200 .uartclk = VR1000_BAUDBASE,
203 .mapbase = VR1000_SERIAL_MAPBASE(2),
204 .irq = IRQ_VR1000_SERIAL + 2,
205 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
208 .uartclk = VR1000_BAUDBASE,
211 .mapbase = VR1000_SERIAL_MAPBASE(3),
212 .irq = IRQ_VR1000_SERIAL + 3,
213 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
216 .uartclk = VR1000_BAUDBASE,
221 static struct platform_device serial_device = {
222 .name = "serial8250",
225 .platform_data = serial_platform_data,
231 static struct resource vr1000_nor_resource[] = {
233 .start = S3C2410_CS1 + 0x4000000,
234 .end = S3C2410_CS1 + 0x4000000 + SZ_16M - 1,
235 .flags = IORESOURCE_MEM,
239 static struct platform_device vr1000_nor = {
242 .num_resources = ARRAY_SIZE(vr1000_nor_resource),
243 .resource = vr1000_nor_resource,
247 static struct platform_device *vr1000_devices[] __initdata = {
257 static struct clk *vr1000_clocks[] = {
265 static struct s3c24xx_board vr1000_board __initdata = {
266 .devices = vr1000_devices,
267 .devices_count = ARRAY_SIZE(vr1000_devices),
268 .clocks = vr1000_clocks,
269 .clocks_count = ARRAY_SIZE(vr1000_clocks),
273 void __init vr1000_map_io(void)
275 /* initialise clock sources */
277 s3c24xx_dclk0.parent = NULL;
278 s3c24xx_dclk0.rate = 12*1000*1000;
280 s3c24xx_dclk1.parent = NULL;
281 s3c24xx_dclk1.rate = 3692307;
283 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
284 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
286 s3c24xx_uclk.parent = &s3c24xx_clkout1;
288 s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
289 s3c24xx_init_clocks(0);
290 s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
291 s3c24xx_set_board(&vr1000_board);
295 void __init vr1000_init_irq(void)
300 MACHINE_START(VR1000, "Thorcom-VR1000")
301 MAINTAINER("Ben Dooks <ben@simtec.co.uk>")
302 BOOT_MEM(S3C2410_SDRAM_PA, S3C2410_PA_UART, S3C2410_VA_UART)
303 BOOT_PARAMS(S3C2410_SDRAM_PA + 0x100)
305 INITIRQ(vr1000_init_irq)
306 .timer = &s3c24xx_timer,