1 /* linux/arch/arm/mach-s3c2410/mach-vr1000.c
3 * Copyright (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * http://www.simtec.co.uk/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * 16-May-2003 BJD Created initial version
14 * 16-Aug-2003 BJD Fixed header files and copyright, added URL
15 * 05-Sep-2003 BJD Moved to v2.6 kernel
16 * 06-Jan-2003 BJD Updates for <arch/map.h>
17 * 18-Jan-2003 BJD Added serial port configuration
18 * 05-Apr-2004 BJD Copied to make mach-vr1000.c
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/interrupt.h>
24 #include <linux/list.h>
25 #include <linux/timer.h>
26 #include <linux/init.h>
28 #include <asm/mach/arch.h>
29 #include <asm/mach/map.h>
30 #include <asm/mach/irq.h>
32 #include <asm/arch/bast-map.h>
33 #include <asm/arch/vr1000-map.h>
35 #include <asm/hardware.h>
38 #include <asm/mach-types.h>
40 //#include <asm/debug-ll.h>
41 #include <asm/arch/regs-serial.h>
45 /* macros for virtual address mods for the io space entries */
46 #define VA_C5(item) ((item) + BAST_VAM_CS5)
47 #define VA_C4(item) ((item) + BAST_VAM_CS4)
48 #define VA_C3(item) ((item) + BAST_VAM_CS3)
49 #define VA_C2(item) ((item) + BAST_VAM_CS2)
51 /* macros to modify the physical addresses for io space */
53 #define PA_CS2(item) ((item) + S3C2410_CS2)
54 #define PA_CS3(item) ((item) + S3C2410_CS3)
55 #define PA_CS4(item) ((item) + S3C2410_CS4)
56 #define PA_CS5(item) ((item) + S3C2410_CS5)
58 static struct map_desc vr1000_iodesc[] __initdata = {
61 { S3C2410_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
62 { S3C2410_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
64 /* we could possibly compress the next set down into a set of smaller tables
65 * pagetables, but that would mean using an L2 section, and it still means
66 * we cannot actually feed the same register to an LDR due to 16K spacing
69 /* bast CPLD control registers, and external interrupt controls */
70 { VR1000_VA_CTRL1, VR1000_PA_CTRL1, SZ_1M, MT_DEVICE },
71 { VR1000_VA_CTRL2, VR1000_PA_CTRL2, SZ_1M, MT_DEVICE },
72 { VR1000_VA_CTRL3, VR1000_PA_CTRL3, SZ_1M, MT_DEVICE },
73 { VR1000_VA_CTRL4, VR1000_PA_CTRL4, SZ_1M, MT_DEVICE },
75 /* peripheral space... one for each of fast/slow/byte/16bit */
76 /* note, ide is only decoded in word space, even though some registers
80 { VA_C2(VR1000_VA_DM9000), PA_CS2(VR1000_PA_DM9000), SZ_1M, MT_DEVICE },
81 { VA_C2(VR1000_VA_IDEPRI), PA_CS3(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
82 { VA_C2(VR1000_VA_IDESEC), PA_CS3(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
83 { VA_C2(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
84 { VA_C2(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
87 { VA_C3(VR1000_VA_DM9000), PA_CS3(VR1000_PA_DM9000), SZ_1M, MT_DEVICE },
88 { VA_C3(VR1000_VA_IDEPRI), PA_CS3(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
89 { VA_C3(VR1000_VA_IDESEC), PA_CS3(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
90 { VA_C3(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
91 { VA_C3(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
94 { VA_C4(VR1000_VA_DM9000), PA_CS4(VR1000_PA_DM9000), SZ_1M, MT_DEVICE },
95 { VA_C4(VR1000_VA_IDEPRI), PA_CS5(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
96 { VA_C4(VR1000_VA_IDESEC), PA_CS5(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
97 { VA_C4(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
98 { VA_C4(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
101 { VA_C5(VR1000_VA_DM9000), PA_CS5(VR1000_PA_DM9000), SZ_1M, MT_DEVICE },
102 { VA_C5(VR1000_VA_IDEPRI), PA_CS5(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
103 { VA_C5(VR1000_VA_IDESEC), PA_CS5(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
104 { VA_C5(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
105 { VA_C5(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
108 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
109 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
110 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
112 /* base baud rate for all our UARTs */
113 static unsigned long vr1000_serial_clock = 3692307;
115 static struct s3c2410_uartcfg vr1000_uartcfgs[] = {
119 .clock = &vr1000_serial_clock,
127 .clock = &vr1000_serial_clock,
132 /* port 2 is not actually used */
136 .clock = &vr1000_serial_clock,
144 void __init vr1000_map_io(void)
146 s3c2410_map_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
147 s3c2410_uartcfgs = vr1000_uartcfgs;
150 void __init vr1000_init_irq(void)
152 //llprintk("vr1000init_irq:\n");
158 MACHINE_START(VR1000, "Simtec-VR1000")
159 MAINTAINER("Ben Dooks <ben@simtec.co.uk>")
160 BOOT_MEM(S3C2410_SDRAM_PA, S3C2410_PA_UART, S3C2410_VA_UART)
161 BOOT_PARAMS(S3C2410_SDRAM_PA + 0x100)
163 INITIRQ(vr1000_init_irq)