1 /* linux/arch/arm/mach-s3c2410/pm.c
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 Power Manager (Suspend-To-RAM) support
8 * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * Parts based on arch/arm/mach-pxa/pm.c
26 * Thanks to Dimitry Andric for debugging
29 #include <linux/config.h>
30 #include <linux/init.h>
31 #include <linux/suspend.h>
32 #include <linux/errno.h>
33 #include <linux/time.h>
34 #include <linux/interrupt.h>
35 #include <linux/crc32.h>
36 #include <linux/ioport.h>
37 #include <linux/delay.h>
39 #include <asm/hardware.h>
42 #include <asm/arch/regs-serial.h>
43 #include <asm/arch/regs-clock.h>
44 #include <asm/arch/regs-gpio.h>
45 #include <asm/arch/regs-mem.h>
46 #include <asm/arch/regs-irq.h>
48 #include <asm/mach/time.h>
52 /* for external use */
54 unsigned long s3c_pm_flags;
56 /* cache functions from arch/arm/mm/proc-arm920.S */
58 extern void arm920_flush_kern_cache_all(void);
60 #define PFX "s3c24xx-pm: "
62 static struct sleep_save core_save[] = {
63 SAVE_ITEM(S3C2410_LOCKTIME),
64 SAVE_ITEM(S3C2410_CLKCON),
66 /* we restore the timings here, with the proviso that the board
67 * brings the system up in an slower, or equal frequency setting
68 * to the original system.
70 * if we cannot guarantee this, then things are going to go very
71 * wrong here, as we modify the refresh and both pll settings.
74 SAVE_ITEM(S3C2410_BWSCON),
75 SAVE_ITEM(S3C2410_BANKCON0),
76 SAVE_ITEM(S3C2410_BANKCON1),
77 SAVE_ITEM(S3C2410_BANKCON2),
78 SAVE_ITEM(S3C2410_BANKCON3),
79 SAVE_ITEM(S3C2410_BANKCON4),
80 SAVE_ITEM(S3C2410_BANKCON5),
82 SAVE_ITEM(S3C2410_CLKDIVN),
83 SAVE_ITEM(S3C2410_MPLLCON),
84 SAVE_ITEM(S3C2410_UPLLCON),
85 SAVE_ITEM(S3C2410_CLKSLOW),
86 SAVE_ITEM(S3C2410_REFRESH),
89 /* this lot should be really saved by the IRQ code */
90 static struct sleep_save irq_save[] = {
91 SAVE_ITEM(S3C2410_EXTINT0),
92 SAVE_ITEM(S3C2410_EXTINT1),
93 SAVE_ITEM(S3C2410_EXTINT2),
94 SAVE_ITEM(S3C2410_EINFLT0),
95 SAVE_ITEM(S3C2410_EINFLT1),
96 SAVE_ITEM(S3C2410_EINFLT2),
97 SAVE_ITEM(S3C2410_EINFLT3),
98 SAVE_ITEM(S3C2410_EINTMASK),
99 SAVE_ITEM(S3C2410_INTMSK)
102 static struct sleep_save gpio_save[] = {
103 SAVE_ITEM(S3C2410_GPACON),
104 SAVE_ITEM(S3C2410_GPADAT),
106 SAVE_ITEM(S3C2410_GPBCON),
107 SAVE_ITEM(S3C2410_GPBDAT),
108 SAVE_ITEM(S3C2410_GPBUP),
110 SAVE_ITEM(S3C2410_GPCCON),
111 SAVE_ITEM(S3C2410_GPCDAT),
112 SAVE_ITEM(S3C2410_GPCUP),
114 SAVE_ITEM(S3C2410_GPDCON),
115 SAVE_ITEM(S3C2410_GPDDAT),
116 SAVE_ITEM(S3C2410_GPDUP),
118 SAVE_ITEM(S3C2410_GPECON),
119 SAVE_ITEM(S3C2410_GPEDAT),
120 SAVE_ITEM(S3C2410_GPEUP),
122 SAVE_ITEM(S3C2410_GPFCON),
123 SAVE_ITEM(S3C2410_GPFDAT),
124 SAVE_ITEM(S3C2410_GPFUP),
126 SAVE_ITEM(S3C2410_GPGCON),
127 SAVE_ITEM(S3C2410_GPGDAT),
128 SAVE_ITEM(S3C2410_GPGUP),
130 SAVE_ITEM(S3C2410_GPHCON),
131 SAVE_ITEM(S3C2410_GPHDAT),
132 SAVE_ITEM(S3C2410_GPHUP),
134 SAVE_ITEM(S3C2410_DCLKCON),
137 #ifdef CONFIG_S3C2410_PM_DEBUG
139 #define SAVE_UART(va) \
140 SAVE_ITEM((va) + S3C2410_ULCON), \
141 SAVE_ITEM((va) + S3C2410_UCON), \
142 SAVE_ITEM((va) + S3C2410_UFCON), \
143 SAVE_ITEM((va) + S3C2410_UMCON), \
144 SAVE_ITEM((va) + S3C2410_UBRDIV)
146 static struct sleep_save uart_save[] = {
147 SAVE_UART(S3C2410_VA_UART0),
148 SAVE_UART(S3C2410_VA_UART1),
149 SAVE_UART(S3C2410_VA_UART2),
154 * we send the debug to printascii() to allow it to be seen if the
155 * system never wakes up from the sleep
158 extern void printascii(const char *);
160 static void pm_dbg(const char *fmt, ...)
166 vsprintf(buff, fmt, va);
172 static void s3c2410_pm_debug_init(void)
174 unsigned long tmp = __raw_readl(S3C2410_CLKCON);
176 /* re-start uart clocks */
177 tmp |= S3C2410_CLKCON_UART0;
178 tmp |= S3C2410_CLKCON_UART1;
179 tmp |= S3C2410_CLKCON_UART2;
181 __raw_writel(tmp, S3C2410_CLKCON);
185 #define DBG(fmt...) pm_dbg(fmt)
187 #define DBG(fmt...) printk(KERN_DEBUG fmt)
189 #define s3c2410_pm_debug_init() do { } while(0)
191 static struct sleep_save uart_save[] = {};
194 #if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0
196 /* suspend checking code...
198 * this next area does a set of crc checks over all the installed
199 * memory, so the system can verify if the resume was ok.
201 * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
202 * increasing it will mean that the area corrupted will be less easy to spot,
203 * and reducing the size will cause the CRC save area to grow
206 #define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
208 static u32 crc_size; /* size needed for the crc block */
209 static u32 *crcs; /* allocated over suspend/resume */
211 typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
213 /* s3c2410_pm_run_res
215 * go thorugh the given resource list, and look for system ram
218 static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
220 while (ptr != NULL) {
221 if (ptr->child != NULL)
222 s3c2410_pm_run_res(ptr->child, fn, arg);
224 if ((ptr->flags & IORESOURCE_MEM) &&
225 strcmp(ptr->name, "System RAM") == 0) {
226 DBG("Found system RAM at %08lx..%08lx\n",
227 ptr->start, ptr->end);
228 arg = (fn)(ptr, arg);
235 static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg)
237 s3c2410_pm_run_res(&iomem_resource, fn, arg);
240 static u32 *s3c2410_pm_countram(struct resource *res, u32 *val)
242 u32 size = (u32)(res->end - res->start)+1;
244 size += CHECK_CHUNKSIZE-1;
245 size /= CHECK_CHUNKSIZE;
247 DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size);
249 *val += size * sizeof(u32);
253 /* s3c2410_pm_prepare_check
255 * prepare the necessary information for creating the CRCs. This
256 * must be done before the final save, as it will require memory
257 * allocating, and thus touching bits of the kernel we do not
261 static void s3c2410_pm_check_prepare(void)
265 s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size);
267 DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size);
269 crcs = kmalloc(crc_size+4, GFP_KERNEL);
271 printk(KERN_ERR "Cannot allocated CRC save area\n");
274 static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val)
276 unsigned long addr, left;
278 for (addr = res->start; addr < res->end;
279 addr += CHECK_CHUNKSIZE) {
280 left = res->end - addr;
282 if (left > CHECK_CHUNKSIZE)
283 left = CHECK_CHUNKSIZE;
285 *val = crc32_le(~0, phys_to_virt(addr), left);
292 /* s3c2410_pm_check_store
294 * compute the CRC values for the memory blocks before the final
298 static void s3c2410_pm_check_store(void)
301 s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs);
306 * return TRUE if the area defined by ptr..ptr+size contatins the
310 static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
312 if ((what+whatsz) < ptr)
315 if (what > (ptr+size))
321 static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val)
323 void *save_at = phys_to_virt(s3c2410_sleep_save_phys);
329 for (addr = res->start; addr < res->end;
330 addr += CHECK_CHUNKSIZE) {
331 left = res->end - addr;
333 if (left > CHECK_CHUNKSIZE)
334 left = CHECK_CHUNKSIZE;
336 ptr = phys_to_virt(addr);
338 if (in_region(ptr, left, crcs, crc_size)) {
339 DBG("skipping %08lx, has crc block in\n", addr);
343 if (in_region(ptr, left, save_at, 32*4 )) {
344 DBG("skipping %08lx, has save block in\n", addr);
348 /* calculate and check the checksum */
350 calc = crc32_le(~0, ptr, left);
352 printk(KERN_ERR PFX "Restore CRC error at "
353 "%08lx (%08x vs %08x)\n", addr, calc, *val);
355 DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
366 /* s3c2410_pm_check_restore
368 * check the CRCs after the restore event and free the memory used
372 static void s3c2410_pm_check_restore(void)
375 s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs);
383 #define s3c2410_pm_check_prepare() do { } while(0)
384 #define s3c2410_pm_check_restore() do { } while(0)
385 #define s3c2410_pm_check_store() do { } while(0)
388 /* helper functions to save and restore register state */
390 void s3c2410_pm_do_save(struct sleep_save *ptr, int count)
392 for (; count > 0; count--, ptr++) {
393 ptr->val = __raw_readl(ptr->reg);
394 DBG("saved %08lx value %08lx\n", ptr->reg, ptr->val);
398 /* s3c2410_pm_do_restore
400 * restore the system from the given list of saved registers
402 * Note, we do not use DBG() in here, as the system may not have
403 * restore the UARTs state yet
406 void s3c2410_pm_do_restore(struct sleep_save *ptr, int count)
408 for (; count > 0; count--, ptr++) {
409 printk(KERN_DEBUG "restore %08lx (restore %08lx, was %08x)\n",
410 ptr->reg, ptr->val, __raw_readl(ptr->reg));
412 __raw_writel(ptr->val, ptr->reg);
416 /* s3c2410_pm_do_restore_core
418 * similar to s3c2410_pm_do_restore_core
420 * WARNING: Do not put any debug in here that may effect memory or use
421 * peripherals, as things may be changing!
424 static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count)
426 for (; count > 0; count--, ptr++) {
427 __raw_writel(ptr->val, ptr->reg);
431 /* s3c2410_pm_show_resume_irqs
433 * print any IRQs asserted at resume time (ie, we woke from)
436 static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
443 for (i = 0; i <= 31; i++) {
444 if ((which) & (1L<<i)) {
445 DBG("IRQ %d asserted at resume\n", start+i);
450 /* s3c2410_pm_check_resume_pin
452 * check to see if the pin is configured correctly for sleep mode, and
453 * make any necessary adjustments if it is not
456 static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
458 unsigned long irqstate;
459 unsigned long pinstate;
460 int irq = s3c2410_gpio_getirq(pin);
463 irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
465 irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
467 pinstate = s3c2410_gpio_getcfg(pin);
468 pinstate >>= S3C2410_GPIO_OFFSET(pin)*2;
471 if (pinstate == 0x02)
472 DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
474 if (pinstate == 0x02) {
475 DBG("Disabling IRQ %d (pin %d)\n", irq, pin);
476 s3c2410_gpio_cfgpin(pin, 0x00);
481 /* s3c2410_pm_configure_extint
483 * configure all external interrupt pins
486 static void s3c2410_pm_configure_extint(void)
490 /* for each of the external interrupts (EINT0..EINT15) we
491 * need to check wether it is an external interrupt source,
492 * and then configure it as an input if it is not
495 for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
496 s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
499 for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
500 s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
504 #define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
508 * central control for sleep/resume process
511 static int s3c2410_pm_enter(suspend_state_t state)
513 unsigned long regs_save[16];
516 /* ensure the debug is initialised (if enabled) */
518 s3c2410_pm_debug_init();
520 DBG("s3c2410_pm_enter(%d)\n", state);
522 if (state != PM_SUSPEND_MEM) {
523 printk(KERN_ERR PFX "error: only PM_SUSPEND_MEM supported\n");
527 /* check if we have anything to wake-up with... bad things seem
528 * to happen if you suspend with no wakeup (system will often
529 * require a full power-cycle)
532 if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
533 !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
534 printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
535 printk(KERN_ERR PFX "Aborting sleep\n");
539 /* prepare check area if configured */
541 s3c2410_pm_check_prepare();
543 /* store the physical address of the register recovery block */
545 s3c2410_sleep_save_phys = virt_to_phys(regs_save);
547 DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys);
549 /* ensure at least GESTATUS3 has the resume address */
551 __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3);
553 DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
554 DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
556 /* save all necessary core registers not covered by the drivers */
558 s3c2410_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save));
559 s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
560 s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
561 s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
563 /* set the irq configuration for wake */
565 s3c2410_pm_configure_extint();
567 DBG("sleep: irq wakeup masks: %08lx,%08lx\n",
568 s3c_irqwake_intmask, s3c_irqwake_eintmask);
570 __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
571 __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
573 /* ack any outstanding external interrupts before we go to sleep */
575 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
577 /* flush cache back to ram */
579 arm920_flush_kern_cache_all();
581 s3c2410_pm_check_store();
583 // need to make some form of time-delta
585 /* send the cpu to sleep... */
587 __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
589 s3c2410_cpu_suspend(regs_save);
591 /* unset the return-from-sleep flag, to ensure reset */
593 tmp = __raw_readl(S3C2410_GSTATUS2);
594 tmp &= S3C2410_GSTATUS2_OFFRESET;
595 __raw_writel(tmp, S3C2410_GSTATUS2);
597 /* restore the system state */
599 s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
600 s3c2410_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save));
601 s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
602 s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
604 s3c2410_pm_debug_init();
606 /* check what irq (if any) restored the system */
608 DBG("post sleep: IRQs 0x%08x, 0x%08x\n",
609 __raw_readl(S3C2410_SRCPND),
610 __raw_readl(S3C2410_EINTPEND));
612 s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
613 s3c_irqwake_intmask);
615 s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
616 s3c_irqwake_eintmask);
618 DBG("post sleep, preparing to return\n");
620 s3c2410_pm_check_restore();
622 /* ok, let's return from sleep */
624 DBG("S3C2410 PM Resume (post-restore)\n");
629 * Called after processes are frozen, but before we shut down devices.
631 static int s3c2410_pm_prepare(suspend_state_t state)
637 * Called after devices are re-setup, but before processes are thawed.
639 static int s3c2410_pm_finish(suspend_state_t state)
645 * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
647 static struct pm_ops s3c2410_pm_ops = {
648 .pm_disk_mode = PM_DISK_FIRMWARE,
649 .prepare = s3c2410_pm_prepare,
650 .enter = s3c2410_pm_enter,
651 .finish = s3c2410_pm_finish,
656 * Attach the power management functions. This should be called
657 * from the board specific initialisation if the board supports
661 int __init s3c2410_pm_init(void)
663 printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n");
665 pm_set_ops(&s3c2410_pm_ops);