1 comment "Processor Type"
7 # Select CPU types depending on the architecture selected. This selects
8 # which CPUs we support in the kernel image, and the compiler instruction
13 bool "Support ARM610 processor"
20 The ARM610 is the successor to the ARM3 processor
21 and was produced by VLSI Technology Inc.
23 Say Y if you want support for the ARM610 processor.
28 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
29 default y if ARCH_CLPS7500
35 A 32-bit RISC microprocessor based on the ARM7 processor core
36 designed by Advanced RISC Machines Ltd. The ARM710 is the
37 successor to the ARM610 processor. It was released in
38 July 1994 by VLSI Technology Inc.
40 Say Y if you want support for the ARM710 processor.
45 bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
46 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712
53 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
54 MMU built around an ARM7TDMI core.
56 Say Y if you want support for the ARM720T processor.
61 bool "Support ARM920T processor" if !ARCH_S3C2410
62 depends on ARCH_INTEGRATOR || ARCH_S3C2410
63 default y if ARCH_S3C2410
70 The ARM920T is licensed to be produced by numerous vendors,
71 and is used in the Maverick EP9312 and the Samsung S3C2410.
73 More information on the Maverick EP9312 at
74 <http://linuxdevices.com/products/PD2382866068.html>.
76 Say Y if you want support for the ARM920T processor.
82 depends on ARCH_CAMELOT || ARCH_LH7A40X
90 The ARM922T is a version of the ARM920T, but with smaller
91 instruction and data caches. It is used in Altera's
92 Excalibur XA device family.
94 Say Y if you want support for the ARM922T processor.
100 depends on ARCH_OMAP1510
104 select CPU_CACHE_V4WT
108 The ARM925T is a mix between the ARM920T and ARM926T, but with
109 different instruction and data caches. It is used in TI's OMAP
112 Say Y if you want support for the ARM925T processor.
117 bool "Support ARM926T processor" if ARCH_INTEGRATOR
118 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || ARCH_OMAP730 || ARCH_OMAP1610 || ARCH_OMAP5912
119 default y if ARCH_VERSATILE_PB
121 select CPU_ABRT_EV5TJ
125 This is a variant of the ARM920. It has slightly different
126 instruction sequences for cache and TLB operations. Curiously,
127 there is no documentation on it at the ARM corporate website.
129 Say Y if you want support for the ARM926T processor.
132 # ARM1020 - needs validating
134 bool "Support ARM1020T (rev 0) processor"
135 depends on ARCH_INTEGRATOR
138 select CPU_CACHE_V4WT
142 The ARM1020 is the 32K cached version of the ARM10 processor,
143 with an addition of a floating-point unit.
145 Say Y if you want support for the ARM1020 processor.
148 # ARM1020E - needs validating
150 bool "Support ARM1020E processor"
151 depends on ARCH_INTEGRATOR
154 select CPU_CACHE_V4WT
161 bool "Support ARM1022E processor"
162 depends on ARCH_INTEGRATOR
165 select CPU_COPY_V4WB # can probably do better
168 The ARM1022E is an implementation of the ARMv5TE architecture
169 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
170 embedded trace macrocell, and a floating-point unit.
172 Say Y if you want support for the ARM1022E processor.
177 bool "Support ARM1026EJ-S processor"
178 depends on ARCH_INTEGRATOR
180 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
181 select CPU_COPY_V4WB # can probably do better
184 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
185 based upon the ARM10 integer core.
187 Say Y if you want support for the ARM1026EJ-S processor.
192 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
193 default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
194 select CPU_32v3 if ARCH_RPC
195 select CPU_32v4 if !ARCH_RPC
197 select CPU_CACHE_V4WB
201 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
202 is available at five speeds ranging from 100 MHz to 233 MHz.
203 More information is available at
204 <http://developer.intel.com/design/strong/sa110.htm>.
206 Say Y if you want support for the SA-110 processor.
212 depends on ARCH_SA1100
216 select CPU_CACHE_V4WB
223 depends on ARCH_IOP3XX || ARCH_PXA || ARCH_IXP4XX
232 bool "Support ARM V6 processor"
233 depends on ARCH_INTEGRATOR
240 # Figure out what processor architecture version we should be using.
241 # This defines the compiler instruction set which depends on the machine type.
267 config CPU_ABRT_EV5TJ
280 config CPU_CACHE_V4WT
283 config CPU_CACHE_V4WB
289 # The copy-page model
302 # This selects the TLB model
306 ARM Architecture Version 3 TLB.
311 ARM Architecture Version 4 TLB with writethrough cache.
316 ARM Architecture Version 4 TLB with writeback cache.
321 ARM Architecture Version 4 TLB with writeback cache and invalidate
322 instruction cache entry.
330 Processor has a minicache.
332 comment "Processor Features"
335 bool "Support Thumb user binaries"
336 depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_V6
339 Say Y if you want to include kernel support for running user space
342 The Thumb instruction set is a compressed form of the standard ARM
343 instruction set resulting in smaller binaries at the expense of
344 slightly less efficient code.
346 If you don't know what this all is, saying Y is a safe choice.
348 config CPU_BIG_ENDIAN
349 bool "Build big-endian kernel"
350 depends on ARCH_SUPPORTS_BIG_ENDIAN
352 Say Y if you plan on running a kernel in big-endian mode.
353 Note that your board must be properly built and your board
354 port must properly enable any big-endian related features
355 of your chipset/board/processor.
357 config CPU_ICACHE_DISABLE
358 bool "Disable I-Cache"
359 depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020
361 Say Y here to disable the processor instruction cache. Unless
362 you have a reason not to or are unsure, say N.
364 config CPU_DCACHE_DISABLE
365 bool "Disable D-Cache"
366 depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020
368 Say Y here to disable the processor data cache. Unless
369 you have a reason not to or are unsure, say N.
371 config CPU_DCACHE_WRITETHROUGH
372 bool "Force write through D-cache"
373 depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020) && !CPU_DISABLE_DCACHE
375 Say Y here to use the data cache in writethough mode. Unless you
376 specifically require this or are unsure, say N.
378 config CPU_CACHE_ROUND_ROBIN
379 bool "Round robin I and D cache replacement algorithm"
380 depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
382 Say Y here to use the predictable round-robin cache replacement
383 policy. Unless you specifically require this or are unsure, say N.
385 config CPU_BPREDICT_DISABLE
386 bool "Disable branch prediction"
387 depends on CPU_ARM1020
389 Say Y here to disable branch prediction. If unsure, say N.