2 * linux/arch/arm/mm/cache-v4wb.S
4 * Copyright (C) 1997-2002 Russell king
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/config.h>
11 #include <linux/linkage.h>
12 #include <linux/init.h>
13 #include <asm/hardware.h>
15 #include "proc-macros.S"
18 * The size of one data cache line.
20 #define CACHE_DLINESIZE 32
23 * The total size of the data cache.
25 #if defined(CONFIG_CPU_SA110)
26 # define CACHE_DSIZE 16384
27 #elif defined(CONFIG_CPU_SA1100)
28 # define CACHE_DSIZE 8192
30 # error Unknown cache size
34 * This is the size at which it becomes more efficient to
35 * clean the whole cache, rather than using the individual
36 * cache line maintainence instructions.
38 * Size Clean (ticks) Dirty (ticks)
39 * 4096 21 20 21 53 55 54
40 * 8192 40 41 40 106 100 102
41 * 16384 77 77 76 140 140 138
42 * 32768 150 149 150 214 216 212 <---
43 * 65536 296 297 296 351 358 361
44 * 131072 591 591 591 656 657 651
45 * Whole 132 136 132 221 217 207 <---
47 #define CACHE_DLIMIT (CACHE_DSIZE * 4)
50 * flush_user_cache_all()
52 * Clean and invalidate all cache entries in a particular address
55 ENTRY(v4wb_flush_user_cache_all)
58 * flush_kern_cache_all()
60 * Clean and invalidate the entire cache.
62 ENTRY(v4wb_flush_kern_cache_all)
64 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
67 add r1, r0, #CACHE_DSIZE
71 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
75 * flush_user_cache_range(start, end, flags)
77 * Invalidate a range of cache entries in the specified
80 * - start - start address (inclusive, page aligned)
81 * - end - end address (exclusive, page aligned)
82 * - flags - vma_area_struct flags describing address space
84 ENTRY(v4wb_flush_user_cache_range)
85 sub r3, r1, r0 @ calculate total size
86 tst r2, #VM_EXEC @ executable region?
87 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
89 cmp r3, #CACHE_DLIMIT @ total size >= limit?
90 bhs __flush_whole_cache @ flush whole D cache
92 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
93 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
94 add r0, r0, #CACHE_DLINESIZE
98 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
102 * flush_kern_dcache_page(void *page)
104 * Ensure no D cache aliasing occurs, either with itself or
107 * - addr - page aligned address
109 ENTRY(v4wb_flush_kern_dcache_page)
114 * coherent_kern_range(start, end)
116 * Ensure coherency between the Icache and the Dcache in the
117 * region described by start. If you have non-snooping
118 * Harvard caches, you need to implement this function.
120 * - start - virtual start address
121 * - end - virtual end address
123 ENTRY(v4wb_coherent_kern_range)
124 bic r0, r0, #CACHE_DLINESIZE - 1
125 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
126 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
127 add r0, r0, #CACHE_DLINESIZE
131 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
132 mcr p15, 0, ip, c7, c10, 4 @ drain WB
137 * dma_inv_range(start, end)
139 * Invalidate (discard) the specified virtual address range.
140 * May not write back any entries. If 'start' or 'end'
141 * are not cache line aligned, those lines must be written
144 * - start - virtual start address
145 * - end - virtual end address
147 ENTRY(v4wb_dma_inv_range)
148 tst r0, #CACHE_DLINESIZE - 1
149 bic r0, r0, #CACHE_DLINESIZE - 1
150 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
151 tst r1, #CACHE_DLINESIZE - 1
152 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
153 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
154 add r0, r0, #CACHE_DLINESIZE
157 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
161 * dma_clean_range(start, end)
163 * Clean (write back) the specified virtual address range.
165 * - start - virtual start address
166 * - end - virtual end address
168 ENTRY(v4wb_dma_clean_range)
169 bic r0, r0, #CACHE_DLINESIZE - 1
170 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
171 add r0, r0, #CACHE_DLINESIZE
174 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
178 * dma_flush_range(start, end)
180 * Clean and invalidate the specified virtual address range.
182 * - start - virtual start address
183 * - end - virtual end address
185 * This is actually the same as v4wb_coherent_kern_range()
187 .globl v4wb_dma_flush_range
188 .set v4wb_dma_flush_range, v4wb_coherent_kern_range
192 .type v4wb_cache_fns, #object
193 ENTRY(v4wb_cache_fns)
194 .long v4wb_flush_kern_cache_all
195 .long v4wb_flush_user_cache_all
196 .long v4wb_flush_user_cache_range
197 .long v4wb_coherent_kern_range
198 .long v4wb_flush_kern_dcache_page
199 .long v4wb_dma_inv_range
200 .long v4wb_dma_clean_range
201 .long v4wb_dma_flush_range
202 .size v4wb_cache_fns, . - v4wb_cache_fns