2 * linux/arch/arm/mm/cache-v4wt.S
4 * Copyright (C) 1997-2002 Russell king
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * ARMv4 write through cache operations support.
12 * We assume that the write buffer is not enabled.
14 #include <linux/linkage.h>
15 #include <linux/init.h>
16 #include <asm/hardware.h>
18 #include "proc-macros.S"
21 * The size of one data cache line.
23 #define CACHE_DLINESIZE 32
26 * The number of data cache segments.
28 #define CACHE_DSEGMENTS 8
31 * The number of lines in a cache segment.
33 #define CACHE_DENTRIES 64
36 * This is the size at which it becomes more efficient to
37 * clean the whole cache, rather than using the individual
38 * cache line maintainence instructions.
40 * *** This needs benchmarking
42 #define CACHE_DLIMIT 16384
45 * flush_user_cache_all()
47 * Invalidate all cache entries in a particular address
50 ENTRY(v4wt_flush_user_cache_all)
53 * flush_kern_cache_all()
55 * Clean and invalidate the entire cache.
57 ENTRY(v4wt_flush_kern_cache_all)
62 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
63 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
67 * flush_user_cache_range(start, end, flags)
69 * Clean and invalidate a range of cache entries in the specified
72 * - start - start address (inclusive, page aligned)
73 * - end - end address (exclusive, page aligned)
74 * - flags - vma_area_struct flags describing address space
76 ENTRY(v4wt_flush_user_cache_range)
77 sub r3, r1, r0 @ calculate total size
79 bhs __flush_whole_cache
81 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
83 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
84 add r0, r0, #CACHE_DLINESIZE
90 * coherent_kern_range(start, end)
92 * Ensure coherency between the Icache and the Dcache in the
93 * region described by start. If you have non-snooping
94 * Harvard caches, you need to implement this function.
96 * - start - virtual start address
97 * - end - virtual end address
99 ENTRY(v4wt_coherent_kern_range)
100 bic r0, r0, #CACHE_DLINESIZE - 1
101 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
102 add r0, r0, #CACHE_DLINESIZE
108 * flush_kern_dcache_page(void *page)
110 * Ensure no D cache aliasing occurs, either with itself or
113 * - addr - page aligned address
115 ENTRY(v4wt_flush_kern_dcache_page)
117 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
122 * dma_inv_range(start, end)
124 * Invalidate (discard) the specified virtual address range.
125 * May not write back any entries. If 'start' or 'end'
126 * are not cache line aligned, those lines must be written
129 * - start - virtual start address
130 * - end - virtual end address
132 ENTRY(v4wt_dma_inv_range)
133 bic r0, r0, #CACHE_DLINESIZE - 1
134 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
135 add r0, r0, #CACHE_DLINESIZE
141 * dma_clean_range(start, end)
143 * Clean the specified virtual address range.
145 * - start - virtual start address
146 * - end - virtual end address
148 ENTRY(v4wt_dma_clean_range)
152 * dma_flush_range(start, end)
154 * Clean and invalidate the specified virtual address range.
156 * - start - virtual start address
157 * - end - virtual end address
159 .globl v4wt_dma_flush_range
160 .equ v4wt_dma_flush_range, v4wt_dma_inv_range
164 .type v4wt_cache_fns, #object
165 ENTRY(v4wt_cache_fns)
166 .long v4wt_flush_kern_cache_all
167 .long v4wt_flush_user_cache_all
168 .long v4wt_flush_user_cache_range
169 .long v4wt_coherent_kern_range
170 .long v4wt_flush_kern_dcache_page
171 .long v4wt_dma_inv_range
172 .long v4wt_dma_clean_range
173 .long v4wt_dma_flush_range
174 .size v4wt_cache_fns, . - v4wt_cache_fns