2 * linux/arch/arm/mm/cache-v6.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This is the "shell" of the ARMv6 processor support.
12 #include <linux/linkage.h>
13 #include <linux/init.h>
14 #include <asm/assembler.h>
16 #include "proc-macros.S"
19 #define CACHE_LINE_SIZE 32
20 #define D_CACHE_LINE_SIZE 32
23 * v6_flush_cache_all()
25 * Flush the entire cache.
29 ENTRY(v6_flush_kern_cache_all)
32 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
33 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
35 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
40 * v6_flush_cache_all()
42 * Flush all TLB entries in a particular address space
44 * - mm - mm_struct describing address space
46 ENTRY(v6_flush_user_cache_all)
50 * v6_flush_cache_range(start, end, flags)
52 * Flush a range of TLB entries in the specified address space.
54 * - start - start address (may not be aligned)
55 * - end - end address (exclusive, may not be aligned)
56 * - flags - vm_area_struct flags describing address space
59 * - we have a VIPT cache.
61 ENTRY(v6_flush_user_cache_range)
65 * v6_coherent_kern_range(start,end)
67 * Ensure that the I and D caches are coherent within specified
68 * region. This is typically used when code has been written to
69 * a memory region, and will be executed.
71 * - start - virtual start address of region
72 * - end - virtual end address of region
75 * - the Icache does not read data from the write buffer
77 ENTRY(v6_coherent_kern_range)
78 bic r0, r0, #CACHE_LINE_SIZE - 1
81 mcr p15, 0, r0, c7, c10, 1 @ clean D line
82 mcr p15, 0, r0, c7, c5, 1 @ invalidate I line
84 mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
85 add r0, r0, #CACHE_LINE_SIZE
90 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
95 * v6_flush_kern_dcache_page(kaddr)
97 * Ensure that the data held in the page kaddr is written back
98 * to the page in question.
100 * - kaddr - kernel address (guaranteed to be page aligned)
102 ENTRY(v6_flush_kern_dcache_page)
106 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
108 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line
110 add r0, r0, #D_CACHE_LINE_SIZE
115 mcr p15, 0, r0, c7, c10, 4
121 * v6_dma_inv_range(start,end)
123 * Invalidate the data cache within the specified region; we will
124 * be performing a DMA operation in this region and we want to
125 * purge old data in the cache.
127 * - start - virtual start address of region
128 * - end - virtual end address of region
130 ENTRY(v6_dma_inv_range)
131 tst r0, #D_CACHE_LINE_SIZE - 1
132 bic r0, r0, #D_CACHE_LINE_SIZE - 1
134 mcrne p15, 0, r0, c7, c10, 1 @ clean D line
136 mcrne p15, 0, r0, c7, c11, 1 @ clean unified line
138 tst r1, #D_CACHE_LINE_SIZE - 1
139 bic r1, r1, #D_CACHE_LINE_SIZE - 1
141 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line
143 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
147 mcr p15, 0, r0, c7, c6, 1 @ invalidate D line
149 mcr p15, 0, r0, c7, c7, 1 @ invalidate unified line
151 add r0, r0, #D_CACHE_LINE_SIZE
155 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
159 * v6_dma_clean_range(start,end)
160 * - start - virtual start address of region
161 * - end - virtual end address of region
163 ENTRY(v6_dma_clean_range)
164 bic r0, r0, #D_CACHE_LINE_SIZE - 1
167 mcr p15, 0, r0, c7, c10, 1 @ clean D line
169 mcr p15, 0, r0, c7, c11, 1 @ clean unified line
171 add r0, r0, #D_CACHE_LINE_SIZE
175 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
179 * v6_dma_flush_range(start,end)
180 * - start - virtual start address of region
181 * - end - virtual end address of region
183 ENTRY(v6_dma_flush_range)
184 bic r0, r0, #D_CACHE_LINE_SIZE - 1
187 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
189 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate line
191 add r0, r0, #D_CACHE_LINE_SIZE
195 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
200 .type v6_cache_fns, #object
202 .long v6_flush_kern_cache_all
203 .long v6_flush_user_cache_all
204 .long v6_flush_user_cache_range
205 .long v6_coherent_kern_range
206 .long v6_flush_kern_dcache_page
207 .long v6_dma_inv_range
208 .long v6_dma_clean_range
209 .long v6_dma_flush_range
210 .size v6_cache_fns, . - v6_cache_fns