2 * linux/arch/arm/mm/proc-arm1022.S: MMU functions for ARM1022E
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 * These are the low level assembler for performing cache and TLB
14 * functions on the ARM1022E.
16 #include <linux/linkage.h>
17 #include <linux/config.h>
18 #include <linux/init.h>
19 #include <asm/assembler.h>
20 #include <asm/constants.h>
21 #include <asm/pgtable.h>
22 #include <asm/procinfo.h>
23 #include <asm/ptrace.h>
26 * This is the maximum size of an area which will be invalidated
27 * using the single invalidate entry instructions. Anything larger
28 * than this, and we go for the whole cache.
30 * This value should be chosen such that we choose the cheapest
33 #define MAX_AREA_SIZE 32768
36 * The size of one data cache line.
38 #define CACHE_DLINESIZE 32
41 * The number of data cache segments.
43 #define CACHE_DSEGMENTS 16
46 * The number of lines in a cache segment.
48 #define CACHE_DENTRIES 64
51 * This is the size at which it becomes more efficient to
52 * clean the whole cache, rather than using the individual
53 * cache line maintainence instructions.
55 #define CACHE_DLIMIT 32768
59 * cpu_arm1022_proc_init()
61 ENTRY(cpu_arm1022_proc_init)
65 * cpu_arm1022_proc_fin()
67 ENTRY(cpu_arm1022_proc_fin)
69 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
71 bl arm1022_flush_kern_cache_all
72 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
73 bic r0, r0, #0x1000 @ ...i............
74 bic r0, r0, #0x000e @ ............wca.
75 mcr p15, 0, r0, c1, c0, 0 @ disable caches
79 * cpu_arm1022_reset(loc)
81 * Perform a soft reset of the system. Put the CPU into the
82 * same state as it would be if it had been reset, and branch
83 * to what would be the reset vector.
85 * loc: location to jump to for soft reset
88 ENTRY(cpu_arm1022_reset)
90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
91 mcr p15, 0, ip, c7, c10, 4 @ drain WB
92 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
93 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
94 bic ip, ip, #0x000f @ ............wcam
95 bic ip, ip, #0x1100 @ ...i...s........
96 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
100 * cpu_arm1022_do_idle()
103 ENTRY(cpu_arm1022_do_idle)
104 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
107 /* ================================= CACHE ================================ */
111 * flush_user_cache_all()
113 * Invalidate all cache entries in a particular address
116 ENTRY(arm1022_flush_user_cache_all)
119 * flush_kern_cache_all()
121 * Clean and invalidate the entire cache.
123 ENTRY(arm1022_flush_kern_cache_all)
127 #ifndef CONFIG_CPU_DCACHE_DISABLE
128 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
129 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
130 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
131 subs r3, r3, #1 << 26
132 bcs 2b @ entries 63 to 0
134 bcs 1b @ segments 15 to 0
137 #ifndef CONFIG_CPU_ICACHE_DISABLE
138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
140 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
144 * flush_user_cache_range(start, end, flags)
146 * Invalidate a range of cache entries in the specified
149 * - start - start address (inclusive)
150 * - end - end address (exclusive)
151 * - flags - vm_flags for this space
153 ENTRY(arm1022_flush_user_cache_range)
155 sub r3, r1, r0 @ calculate total size
156 cmp r3, #CACHE_DLIMIT
157 bhs __flush_whole_cache
159 #ifndef CONFIG_CPU_DCACHE_DISABLE
160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
161 add r0, r0, #CACHE_DLINESIZE
166 #ifndef CONFIG_CPU_ICACHE_DISABLE
167 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
169 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
173 * coherent_kern_range(start, end)
175 * Ensure coherency between the Icache and the Dcache in the
176 * region described by start. If you have non-snooping
177 * Harvard caches, you need to implement this function.
179 * - start - virtual start address
180 * - end - virtual end address
182 ENTRY(arm1022_coherent_kern_range)
184 bic r0, r0, #CACHE_DLINESIZE - 1
186 #ifndef CONFIG_CPU_DCACHE_DISABLE
187 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
189 #ifndef CONFIG_CPU_ICACHE_DISABLE
190 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
192 add r0, r0, #CACHE_DLINESIZE
195 mcr p15, 0, ip, c7, c10, 4 @ drain WB
199 * flush_kern_dcache_page(void *page)
201 * Ensure no D cache aliasing occurs, either with itself or
204 * - page - page aligned address
206 ENTRY(arm1022_flush_kern_dcache_page)
208 #ifndef CONFIG_CPU_DCACHE_DISABLE
210 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
211 add r0, r0, #CACHE_DLINESIZE
215 mcr p15, 0, ip, c7, c10, 4 @ drain WB
219 * dma_inv_range(start, end)
221 * Invalidate (discard) the specified virtual address range.
222 * May not write back any entries. If 'start' or 'end'
223 * are not cache line aligned, those lines must be written
226 * - start - virtual start address
227 * - end - virtual end address
231 ENTRY(arm1022_dma_inv_range)
233 #ifndef CONFIG_CPU_DCACHE_DISABLE
234 tst r0, #CACHE_DLINESIZE - 1
235 bic r0, r0, #CACHE_DLINESIZE - 1
236 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
237 tst r1, #CACHE_DLINESIZE - 1
238 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
239 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
240 add r0, r0, #CACHE_DLINESIZE
244 mcr p15, 0, ip, c7, c10, 4 @ drain WB
248 * dma_clean_range(start, end)
250 * Clean the specified virtual address range.
252 * - start - virtual start address
253 * - end - virtual end address
257 ENTRY(arm1022_dma_clean_range)
259 #ifndef CONFIG_CPU_DCACHE_DISABLE
260 bic r0, r0, #CACHE_DLINESIZE - 1
261 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
262 add r0, r0, #CACHE_DLINESIZE
266 mcr p15, 0, ip, c7, c10, 4 @ drain WB
270 * dma_flush_range(start, end)
272 * Clean and invalidate the specified virtual address range.
274 * - start - virtual start address
275 * - end - virtual end address
277 ENTRY(arm1022_dma_flush_range)
279 #ifndef CONFIG_CPU_DCACHE_DISABLE
280 bic r0, r0, #CACHE_DLINESIZE - 1
281 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
282 add r0, r0, #CACHE_DLINESIZE
286 mcr p15, 0, ip, c7, c10, 4 @ drain WB
289 ENTRY(arm1022_cache_fns)
290 .long arm1022_flush_kern_cache_all
291 .long arm1022_flush_user_cache_all
292 .long arm1022_flush_user_cache_range
293 .long arm1022_coherent_kern_range
294 .long arm1022_flush_kern_dcache_page
295 .long arm1022_dma_inv_range
296 .long arm1022_dma_clean_range
297 .long arm1022_dma_flush_range
300 ENTRY(cpu_arm1022_dcache_clean_area)
301 #ifndef CONFIG_CPU_DCACHE_DISABLE
303 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
304 add r0, r0, #CACHE_DLINESIZE
305 subs r1, r1, #CACHE_DLINESIZE
310 /* =============================== PageTable ============================== */
313 * cpu_arm1022_switch_mm(pgd)
315 * Set the translation base pointer to be as described by pgd.
317 * pgd: new page tables
320 ENTRY(cpu_arm1022_switch_mm)
321 #ifndef CONFIG_CPU_DCACHE_DISABLE
322 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
323 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
324 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
325 subs r3, r3, #1 << 26
326 bcs 2b @ entries 63 to 0
328 bcs 1b @ segments 15 to 0
331 #ifndef CONFIG_CPU_ICACHE_DISABLE
332 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
334 mcr p15, 0, r1, c7, c10, 4 @ drain WB
335 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
336 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
340 * cpu_arm1022_set_pte(ptep, pte)
342 * Set a PTE and flush it out
345 ENTRY(cpu_arm1022_set_pte)
346 str r1, [r0], #-2048 @ linux version
348 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
350 bic r2, r1, #PTE_SMALL_AP_MASK
351 bic r2, r2, #PTE_TYPE_MASK
352 orr r2, r2, #PTE_TYPE_SMALL
354 tst r1, #L_PTE_USER @ User?
355 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
357 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
358 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
360 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
363 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
364 eor r3, r1, #0x0a @ C & small page?
368 str r2, [r0] @ hardware version
370 #ifndef CONFIG_CPU_DCACHE_DISABLE
371 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
377 .type __arm1022_setup, #function
380 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
381 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
382 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
383 mcr p15, 0, r4, c2, c0 @ load page table pointer
384 mov r0, #0x1f @ Domains 0, 1 = client
385 mcr p15, 0, r0, c3, c0 @ load domain access register
386 mrc p15, 0, r0, c1, c0 @ get control register v4
388 * Clear out 'unwanted' bits (then put them in if we need them)
390 bic r0, r0, #0x1e00 @ ...i??r.........
391 bic r0, r0, #0x000e @ ............wca.
393 * Turn on what we want
395 orr r0, r0, #0x0031 @ ..........DP...M
396 orr r0, r0, #0x2100 @ ..V....S........
398 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
399 orr r0, r0, #0x4000 @ .R..............
401 #ifndef CONFIG_CPU_BPREDICT_DISABLE
402 orr r0, r0, #0x0800 @ ....Z...........
404 #ifndef CONFIG_CPU_DCACHE_DISABLE
405 orr r0, r0, #0x0004 @ .............C..
407 #ifndef CONFIG_CPU_ICACHE_DISABLE
408 orr r0, r0, #0x1000 @ ...I............
411 .size __arm1022_setup, . - __arm1022_setup
416 * Purpose : Function pointers used to access above functions - all calls
419 .type arm1022_processor_functions, #object
420 arm1022_processor_functions:
421 .word v4t_early_abort
422 .word cpu_arm1022_proc_init
423 .word cpu_arm1022_proc_fin
424 .word cpu_arm1022_reset
425 .word cpu_arm1022_do_idle
426 .word cpu_arm1022_dcache_clean_area
427 .word cpu_arm1022_switch_mm
428 .word cpu_arm1022_set_pte
429 .size arm1022_processor_functions, . - arm1022_processor_functions
433 .type cpu_arch_name, #object
436 .size cpu_arch_name, . - cpu_arch_name
438 .type cpu_elf_name, #object
441 .size cpu_elf_name, . - cpu_elf_name
443 .type cpu_arm1022_name, #object
446 #ifndef CONFIG_CPU_ICACHE_DISABLE
449 #ifndef CONFIG_CPU_DCACHE_DISABLE
451 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
457 #ifndef CONFIG_CPU_BPREDICT_DISABLE
460 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
464 .size cpu_arm1022_name, . - cpu_arm1022_name
468 .section ".proc.info", #alloc, #execinstr
470 .type __arm1022_proc_info,#object
472 .long 0x4105a220 @ ARM 1022E (v5TE)
474 .long 0x00000c12 @ mmuflags
478 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
479 .long cpu_arm1022_name
480 .long arm1022_processor_functions
483 .long arm1022_cache_fns
484 .size __arm1022_proc_info, . - __arm1022_proc_info