2 * linux/arch/arm/mm/proc-arm920.S: MMU functions for ARM920
4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * These are the low level assembler for performing cache and TLB
23 * functions on the arm920.
25 * CONFIG_CPU_ARM920_CPU_IDLE -> nohlt
27 #include <linux/linkage.h>
28 #include <linux/config.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/pgtable.h>
32 #include <asm/procinfo.h>
33 #include <asm/hardware.h>
35 #include <asm/ptrace.h>
36 #include "proc-macros.S"
39 * The size of one data cache line.
41 #define CACHE_DLINESIZE 32
44 * The number of data cache segments.
46 #define CACHE_DSEGMENTS 8
49 * The number of lines in a cache segment.
51 #define CACHE_DENTRIES 64
54 * This is the size at which it becomes more efficient to
55 * clean the whole cache, rather than using the individual
56 * cache line maintainence instructions.
58 #define CACHE_DLIMIT 65536
63 * cpu_arm920_proc_init()
65 ENTRY(cpu_arm920_proc_init)
69 * cpu_arm920_proc_fin()
71 ENTRY(cpu_arm920_proc_fin)
73 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
75 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
76 bl arm920_flush_kern_cache_all
78 bl v4wt_flush_kern_cache_all
80 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
81 bic r0, r0, #0x1000 @ ...i............
82 bic r0, r0, #0x000e @ ............wca.
83 mcr p15, 0, r0, c1, c0, 0 @ disable caches
87 * cpu_arm920_reset(loc)
89 * Perform a soft reset of the system. Put the CPU into the
90 * same state as it would be if it had been reset, and branch
91 * to what would be the reset vector.
93 * loc: location to jump to for soft reset
96 ENTRY(cpu_arm920_reset)
98 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
99 mcr p15, 0, ip, c7, c10, 4 @ drain WB
100 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
101 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
102 bic ip, ip, #0x000f @ ............wcam
103 bic ip, ip, #0x1100 @ ...i...s........
104 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
108 * cpu_arm920_do_idle()
111 ENTRY(cpu_arm920_do_idle)
112 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
116 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
119 * flush_user_cache_all()
121 * Invalidate all cache entries in a particular address
124 ENTRY(arm920_flush_user_cache_all)
128 * flush_kern_cache_all()
130 * Clean and invalidate the entire cache.
132 ENTRY(arm920_flush_kern_cache_all)
136 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
137 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
138 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
139 subs r3, r3, #1 << 26
140 bcs 2b @ entries 63 to 0
142 bcs 1b @ segments 7 to 0
144 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
145 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
149 * flush_user_cache_range(start, end, flags)
151 * Invalidate a range of cache entries in the specified
154 * - start - start address (inclusive)
155 * - end - end address (exclusive)
156 * - flags - vm_flags for address space
158 ENTRY(arm920_flush_user_cache_range)
160 sub r3, r1, r0 @ calculate total size
161 cmp r3, #CACHE_DLIMIT
162 bhs __flush_whole_cache
164 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
166 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
167 add r0, r0, #CACHE_DLINESIZE
171 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
175 * coherent_kern_range(start, end)
177 * Ensure coherency between the Icache and the Dcache in the
178 * region described by start, end. If you have non-snooping
179 * Harvard caches, you need to implement this function.
181 * - start - virtual start address
182 * - end - virtual end address
184 ENTRY(arm920_coherent_kern_range)
185 bic r0, r0, #CACHE_DLINESIZE - 1
186 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
187 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
188 add r0, r0, #CACHE_DLINESIZE
191 mcr p15, 0, r0, c7, c10, 4 @ drain WB
195 * flush_kern_dcache_page(void *page)
197 * Ensure no D cache aliasing occurs, either with itself or
200 * - addr - page aligned address
202 ENTRY(arm920_flush_kern_dcache_page)
204 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
205 add r0, r0, #CACHE_DLINESIZE
209 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
210 mcr p15, 0, r0, c7, c10, 4 @ drain WB
214 * dma_inv_range(start, end)
216 * Invalidate (discard) the specified virtual address range.
217 * May not write back any entries. If 'start' or 'end'
218 * are not cache line aligned, those lines must be written
221 * - start - virtual start address
222 * - end - virtual end address
226 ENTRY(arm920_dma_inv_range)
227 tst r0, #CACHE_DLINESIZE - 1
228 bic r0, r0, #CACHE_DLINESIZE - 1
229 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
230 tst r1, #CACHE_DLINESIZE - 1
231 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
232 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
233 add r0, r0, #CACHE_DLINESIZE
236 mcr p15, 0, r0, c7, c10, 4 @ drain WB
240 * dma_clean_range(start, end)
242 * Clean the specified virtual address range.
244 * - start - virtual start address
245 * - end - virtual end address
249 ENTRY(arm920_dma_clean_range)
250 bic r0, r0, #CACHE_DLINESIZE - 1
251 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
252 add r0, r0, #CACHE_DLINESIZE
255 mcr p15, 0, r0, c7, c10, 4 @ drain WB
259 * dma_flush_range(start, end)
261 * Clean and invalidate the specified virtual address range.
263 * - start - virtual start address
264 * - end - virtual end address
266 ENTRY(arm920_dma_flush_range)
267 bic r0, r0, #CACHE_DLINESIZE - 1
268 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
269 add r0, r0, #CACHE_DLINESIZE
272 mcr p15, 0, r0, c7, c10, 4 @ drain WB
275 ENTRY(arm920_cache_fns)
276 .long arm920_flush_kern_cache_all
277 .long arm920_flush_user_cache_all
278 .long arm920_flush_user_cache_range
279 .long arm920_coherent_kern_range
280 .long arm920_flush_kern_dcache_page
281 .long arm920_dma_inv_range
282 .long arm920_dma_clean_range
283 .long arm920_dma_flush_range
288 ENTRY(cpu_arm920_dcache_clean_area)
289 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
290 add r0, r0, #CACHE_DLINESIZE
291 subs r1, r1, #CACHE_DLINESIZE
295 /* =============================== PageTable ============================== */
298 * cpu_arm920_switch_mm(pgd)
300 * Set the translation base pointer to be as described by pgd.
302 * pgd: new page tables
305 ENTRY(cpu_arm920_switch_mm)
307 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
308 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
310 @ && 'Clean & Invalidate whole DCache'
311 @ && Re-written to use Index Ops.
312 @ && Uses registers r1, r3 and ip
314 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
315 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
316 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
317 subs r3, r3, #1 << 26
318 bcs 2b @ entries 63 to 0
320 bcs 1b @ segments 7 to 0
322 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
323 mcr p15, 0, ip, c7, c10, 4 @ drain WB
324 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
325 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
329 * cpu_arm920_set_pte(ptep, pte)
331 * Set a PTE and flush it out
334 ENTRY(cpu_arm920_set_pte)
335 str r1, [r0], #-2048 @ linux version
337 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
339 bic r2, r1, #PTE_SMALL_AP_MASK
340 bic r2, r2, #PTE_TYPE_MASK
341 orr r2, r2, #PTE_TYPE_SMALL
343 tst r1, #L_PTE_USER @ User?
344 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
346 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
347 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
349 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
352 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
353 eor r3, r2, #0x0a @ C & small page?
357 str r2, [r0] @ hardware version
359 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
360 mcr p15, 0, r0, c7, c10, 4 @ drain WB
365 .type __arm920_setup, #function
368 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
369 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
370 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
371 mcr p15, 0, r4, c2, c0 @ load page table pointer
372 mov r0, #0x1f @ Domains 0, 1 = client
373 mcr p15, 0, r0, c3, c0 @ load domain access register
374 mrc p15, 0, r0, c1, c0 @ get control register v4
376 * Clear out 'unwanted' bits (then put them in if we need them)
382 bic r0, r0, #0x1000 @ ...0 000. .... 000.
384 * Turn on what we want
387 orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1
389 #ifndef CONFIG_CPU_DCACHE_DISABLE
390 orr r0, r0, #0x0004 @ .... .... .... .1..
392 #ifndef CONFIG_CPU_ICACHE_DISABLE
393 orr r0, r0, #0x1000 @ ...1 .... .... ....
396 .size __arm920_setup, . - __arm920_setup
401 * Purpose : Function pointers used to access above functions - all calls
404 .type arm920_processor_functions, #object
405 arm920_processor_functions:
406 .word v4t_early_abort
407 .word cpu_arm920_proc_init
408 .word cpu_arm920_proc_fin
409 .word cpu_arm920_reset
410 .word cpu_arm920_do_idle
411 .word cpu_arm920_dcache_clean_area
412 .word cpu_arm920_switch_mm
413 .word cpu_arm920_set_pte
414 .size arm920_processor_functions, . - arm920_processor_functions
418 .type cpu_arch_name, #object
421 .size cpu_arch_name, . - cpu_arch_name
423 .type cpu_elf_name, #object
426 .size cpu_elf_name, . - cpu_elf_name
428 .type cpu_arm920_name, #object
431 #ifndef CONFIG_CPU_ICACHE_DISABLE
434 #ifndef CONFIG_CPU_DCACHE_DISABLE
436 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
443 .size cpu_arm920_name, . - cpu_arm920_name
447 .section ".proc.info", #alloc, #execinstr
449 .type __arm920_proc_info,#object
453 .long 0x00000c1e @ mmuflags
457 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
458 .long cpu_arm920_name
459 .long arm920_processor_functions
462 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
463 .long arm920_cache_fns
467 .size __arm920_proc_info, . - __arm920_proc_info