2 * linux/arch/arm/mm/proc-sa1100.S
4 * Copyright (C) 1997-2002 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * MMU functions for SA110
12 * These are the low level assembler for performing cache and TLB
13 * functions on the StrongARM-1100 and StrongARM-1110.
15 * Note that SA1100 and SA1110 share everything but their name and CPU ID.
17 * 12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
18 * Flush the read buffer at context switches
20 #include <linux/linkage.h>
21 #include <linux/init.h>
22 #include <asm/assembler.h>
23 #include <asm/constants.h>
24 #include <asm/procinfo.h>
25 #include <asm/hardware.h>
26 #include <asm/pgtable.h>
29 * the cache line size of the I and D cache
31 #define DCACHELINESIZE 32
32 #define FLUSH_OFFSET 32768
34 .macro flush_1100_dcache rd, ra, re
37 eor \ra, \ra, #FLUSH_OFFSET
39 add \re, \ra, #8192 @ only necessary for 8k
40 1001: ldr \rd, [\ra], #DCACHELINESIZE
43 #ifdef FLUSH_BASE_MINICACHE
44 add \ra, \ra, #FLUSH_BASE_MINICACHE - FLUSH_BASE
45 add \re, \ra, #512 @ only 512 bytes
46 1002: ldr \rd, [\ra], #DCACHELINESIZE
60 * cpu_sa1100_proc_init()
62 ENTRY(cpu_sa1100_proc_init)
64 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
65 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
71 * cpu_sa1100_proc_fin()
73 * Prepare the CPU for reset:
74 * - Disable interrupts
75 * - Clean and turn off caches.
77 ENTRY(cpu_sa1100_proc_fin)
79 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
81 flush_1100_dcache r0, r1, r2 @ clean caches
83 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
84 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
85 bic r0, r0, #0x1000 @ ...i............
86 bic r0, r0, #0x000e @ ............wca.
87 mcr p15, 0, r0, c1, c0, 0 @ disable caches
91 * cpu_sa1100_reset(loc)
93 * Perform a soft reset of the system. Put the CPU into the
94 * same state as it would be if it had been reset, and branch
95 * to what would be the reset vector.
97 * loc: location to jump to for soft reset
100 ENTRY(cpu_sa1100_reset)
102 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
103 mcr p15, 0, ip, c7, c10, 4 @ drain WB
104 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
105 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
106 bic ip, ip, #0x000f @ ............wcam
107 bic ip, ip, #0x1100 @ ...i...s........
108 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
112 * cpu_sa1100_do_idle(type)
114 * Cause the processor to idle
119 * 2 = switch to slow processor clock
120 * 3 = switch to fast processor clock
123 ENTRY(cpu_sa1100_do_idle)
124 mov r0, r0 @ 4 nop padding
127 mov r0, r0 @ 4 nop padding
131 ldr r1, =UNCACHEABLE_ADDR @ ptr to uncacheable address
132 @ --- aligned to a cache line
133 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
134 ldr r1, [r1, #0] @ force switch to MCLK
135 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
137 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
140 /* ================================= CACHE ================================ */
143 * cpu_sa1100_dcache_clean_area(addr,sz)
145 * Clean the specified entry of any caches such that the MMU
146 * translation fetches will obtain correct data.
148 * addr: cache-unaligned virtual address
151 ENTRY(cpu_sa1100_dcache_clean_area)
152 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
153 add r0, r0, #DCACHELINESIZE
154 subs r1, r1, #DCACHELINESIZE
158 /* =============================== PageTable ============================== */
161 * cpu_sa1100_switch_mm(pgd)
163 * Set the translation base pointer to be as described by pgd.
165 * pgd: new page tables
168 ENTRY(cpu_sa1100_switch_mm)
169 flush_1100_dcache r3, ip, r1
171 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
172 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
173 mcr p15, 0, ip, c7, c10, 4 @ drain WB
174 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
175 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
179 * cpu_sa1100_set_pte(ptep, pte)
181 * Set a PTE and flush it out
184 ENTRY(cpu_sa1100_set_pte)
185 str r1, [r0], #-2048 @ linux version
187 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
189 bic r2, r1, #PTE_SMALL_AP_MASK
190 bic r2, r2, #PTE_TYPE_MASK
191 orr r2, r2, #PTE_TYPE_SMALL
193 tst r1, #L_PTE_USER @ User?
194 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
196 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
197 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
199 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
202 str r2, [r0] @ hardware version
204 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
205 mcr p15, 0, r0, c7, c10, 4 @ drain WB
210 .type __sa1100_setup, #function
213 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
214 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
215 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
216 mov r0, #0x1f @ Domains 0, 1 = client
217 mcr p15, 0, r0, c3, c0 @ load domain access register
218 mcr p15, 0, r4, c2, c0 @ load page table pointer
219 mrc p15, 0, r0, c1, c0 @ get control register v4
220 bic r0, r0, #0x0e00 @ ..VI ZFRS BLDP WCAM
221 bic r0, r0, #0x0002 @ .... 000. .... ..0.
223 orr r0, r0, #0x3100 @ ..11 ...1 ..11 11.1
225 .size __sa1100_setup, . - __sa1100_setup
230 * Purpose : Function pointers used to access above functions - all calls
235 * SA1100 and SA1110 share the same function calls
237 .type sa1100_processor_functions, #object
238 ENTRY(sa1100_processor_functions)
240 .word cpu_sa1100_proc_init
241 .word cpu_sa1100_proc_fin
242 .word cpu_sa1100_reset
243 .word cpu_sa1100_do_idle
244 .word cpu_sa1100_dcache_clean_area
245 .word cpu_sa1100_switch_mm
246 .word cpu_sa1100_set_pte
247 .size sa1100_processor_functions, . - sa1100_processor_functions
251 .type cpu_arch_name, #object
254 .size cpu_arch_name, . - cpu_arch_name
256 .type cpu_elf_name, #object
259 .size cpu_elf_name, . - cpu_elf_name
261 .type cpu_sa1100_name, #object
263 .asciz "StrongARM-1100"
264 .size cpu_sa1100_name, . - cpu_sa1100_name
266 .type cpu_sa1110_name, #object
268 .asciz "StrongARM-1110"
269 .size cpu_sa1110_name, . - cpu_sa1110_name
273 .section ".proc.info", #alloc, #execinstr
275 .type __sa1100_proc_info,#object
283 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
284 .long cpu_sa1100_name
285 .long sa1100_processor_functions
289 .size __sa1100_proc_info, . - __sa1100_proc_info
291 .type __sa1110_proc_info,#object
299 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
300 .long cpu_sa1110_name
301 .long sa1100_processor_functions
305 .size __sa1110_proc_info, . - __sa1110_proc_info