2 * linux/arch/arm/mm/proc-v6.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This is the "shell" of the ARMv6 processor support.
12 #include <linux/linkage.h>
13 #include <asm/assembler.h>
14 #include <asm/constants.h>
15 #include <asm/procinfo.h>
16 #include <asm/pgtable.h>
18 #include "proc-macros.S"
20 #define D_CACHE_LINE_SIZE 32
54 ENTRY(cpu_v6_proc_init)
57 ENTRY(cpu_v6_proc_fin)
63 * Perform a soft reset of the system. Put the CPU into the
64 * same state as it would be if it had been reset, and branch
65 * to what would be the reset vector.
67 * - loc - location to jump to for soft reset
78 * Idle the processor (eg, wait for interrupt).
80 * IRQs are already disabled.
83 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
86 ENTRY(cpu_v6_dcache_clean_area)
87 #ifndef TLB_CAN_READ_FROM_L1_CACHE
88 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
89 add r0, r0, #D_CACHE_LINE_SIZE
90 subs r1, r1, #D_CACHE_LINE_SIZE
96 * cpu_arm926_switch_mm(pgd_phys, tsk)
98 * Set the translation table base pointer to be pgd_phys
100 * - pgd_phys - physical address of new TTB
102 * It is assumed that:
103 * - we are not using split page tables
105 ENTRY(cpu_v6_switch_mm)
107 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
108 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
109 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
110 mcr p15, 0, r1, c13, c0, 1 @ set context ID
120 * cpu_v6_set_pte(ptep, pte)
122 * Set a level 2 translation table entry.
124 * - ptep - pointer to level 2 translation table entry
125 * (hardware version is stored at -1024 bytes)
126 * - pte - PTE value to store
129 * YUWD APX AP1 AP0 SVC User
130 * 0xxx 0 0 0 no acc no acc
131 * 100x 1 0 1 r/o no acc
132 * 10x0 1 0 1 r/o no acc
133 * 1011 0 0 1 r/w no acc
138 ENTRY(cpu_v6_set_pte)
139 str r1, [r0], #-2048 @ linux version
141 bic r2, r1, #0x00000ff0
142 bic r2, r2, #0x00000003
146 tstne r1, #L_PTE_DIRTY
150 orrne r2, r2, #AP1 | nG
155 biceq r2, r2, #APX | AP1 | AP0
157 @ tst r1, #L_PTE_EXEC
160 tst r1, #L_PTE_PRESENT
164 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
171 .asciz "Some Random V6 Processor"
174 .section ".text.init", #alloc, #execinstr
179 * Initialise TLB, Caches, and MMU state ready to switch the MMU
180 * on. Return in r0 the new CP15 C1 control register setting.
182 * We automatically detect if we have a Harvard cache, and use the
183 * Harvard cache control instructions insead of the unified cache
184 * control instructions.
186 * This should be able to cover all ARMv6 cores.
188 * It is assumed that:
189 * - cache type register is implemented
193 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D cache
194 mcr p15, 0, r10, c7, c5, 0 @ invalidate I cache
195 mcr p15, 0, r10, c7, c15, 0 @ clean+invalidate cache
196 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer
197 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
198 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
199 mcr p15, 0, r4, c2, c0, 0 @ load TTB0
200 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
201 mov r10, #0x1f @ domains 0, 1 = manager
202 mcr p15, 0, r10, c3, c0, 0 @ load domain access register
203 mrc p15, 0, r0, c1, c0, 0 @ read control register
205 mrc p15, 0, r10, c1, c0, 2
206 orr r10, r10, #(3 << 20)
207 mcr p15, 0, r10, c1, c0, 2 @ Enable full access to VFP
209 ldr r10, cr1_clear @ get mask for bits to clear
210 bic r0, r0, r10 @ clear bits them
211 ldr r10, cr1_set @ get mask for bits to set
212 orr r0, r0, r10 @ set them
213 mov pc, lr @ return to head.S:__ret
217 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
218 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
219 * 0 110 0011 1.00 .111 1101 < we want
221 .type cr1_clear, #object
222 .type cr1_set, #object
228 .type v6_processor_functions, #object
229 ENTRY(v6_processor_functions)
231 .word cpu_v6_proc_init
232 .word cpu_v6_proc_fin
235 .word cpu_v6_dcache_clean_area
236 .word cpu_v6_switch_mm
238 .size v6_processor_functions, . - v6_processor_functions
240 .type cpu_arch_name, #object
243 .size cpu_arch_name, . - cpu_arch_name
245 .type cpu_elf_name, #object
248 .size cpu_elf_name, . - cpu_elf_name
251 .section ".proc.info", #alloc, #execinstr
254 * Match any ARMv6 processor core.
256 .type __v6_proc_info, #object
264 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_VFP|HWCAP_EDSP|HWCAP_JAVA
266 .long v6_processor_functions
270 .size __v6_proc_info, . - __v6_proc_info