2 * linux/arch/arm/mm/proc-xscale.S
4 * Author: Nicolas Pitre
5 * Created: November 2000
6 * Copyright: (C) 2000, 2001 MontaVista Software Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * MMU functions for the Intel XScale CPUs
15 * some contributions by Brett Gaines <brett.w.gaines@intel.com>
16 * Copyright 2001 by Intel Corp.
19 * Completely revisited, many important fixes
20 * Nicolas Pitre <nico@cam.org>
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <asm/assembler.h>
26 #include <asm/procinfo.h>
27 #include <asm/hardware.h>
28 #include <asm/pgtable.h>
30 #include <asm/ptrace.h>
31 #include "proc-macros.S"
34 * This is the maximum size of an area which will be flushed. If the area
35 * is larger than this, then we flush the whole cache
37 #define MAX_AREA_SIZE 32768
40 * the cache line size of the I and D cache
42 #define CACHELINESIZE 32
45 * the size of the data cache
47 #define CACHESIZE 32768
50 * Virtual address used to allocate the cache when flushed
52 * This must be an address range which is _never_ used. It should
53 * apparently have a mapping in the corresponding page table for
54 * compatibility with future CPUs that _could_ require it. For instance we
57 * This must be aligned on a 2*CACHESIZE boundary. The code selects one of
58 * the 2 areas in alternance each time the clean_d_cache macro is used.
59 * Without this the XScale core exhibits cache eviction problems and no one
62 * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
64 #define CLEAN_ADDR 0xfffe0000
67 * This macro is used to wait for a CP15 write and is needed
68 * when we have to ensure that the last operation to the co-pro
69 * was completed before continuing with operation.
72 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
73 mov \rd, \rd @ wait for completion
74 sub pc, pc, #4 @ flush instruction pipeline
77 .macro cpwait_ret, lr, rd
78 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
79 sub pc, \lr, \rd, LSR #32 @ wait for completion and
80 @ flush instruction pipeline
84 * This macro cleans the entire dcache using line allocate.
85 * The main loop has been unrolled to reduce loop overhead.
86 * rd and rs are two scratch registers.
88 .macro clean_d_cache, rd, rs
91 eor \rd, \rd, #CACHESIZE
93 add \rs, \rd, #CACHESIZE
94 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
95 add \rd, \rd, #CACHELINESIZE
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
97 add \rd, \rd, #CACHELINESIZE
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
99 add \rd, \rd, #CACHELINESIZE
100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
101 add \rd, \rd, #CACHELINESIZE
107 clean_addr: .word CLEAN_ADDR
112 * cpu_xscale_proc_init()
114 * Nothing too exciting at the moment
116 ENTRY(cpu_xscale_proc_init)
120 * cpu_xscale_proc_fin()
122 ENTRY(cpu_xscale_proc_fin)
124 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
126 bl xscale_flush_kern_cache_all @ clean caches
127 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
128 bic r0, r0, #0x1800 @ ...IZ...........
129 bic r0, r0, #0x0006 @ .............CA.
130 mcr p15, 0, r0, c1, c0, 0 @ disable caches
134 * cpu_xscale_reset(loc)
136 * Perform a soft reset of the system. Put the CPU into the
137 * same state as it would be if it had been reset, and branch
138 * to what would be the reset vector.
140 * loc: location to jump to for soft reset
143 ENTRY(cpu_xscale_reset)
144 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
145 msr cpsr_c, r1 @ reset CPSR
146 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
147 bic r1, r1, #0x0086 @ ........B....CA.
148 bic r1, r1, #0x3900 @ ..VIZ..S........
149 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
150 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
151 bic r1, r1, #0x0001 @ ...............M
152 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
153 @ CAUTION: MMU turned off from this point. We count on the pipeline
154 @ already containing those two last instructions to survive.
155 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
159 * cpu_xscale_do_idle()
161 * Cause the processor to idle
163 * For now we do nothing but go to idle mode for every case
165 * XScale supports clock switching, but using idle mode support
166 * allows external hardware to react to system state changes.
170 ENTRY(cpu_xscale_do_idle)
172 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
175 /* ================================= CACHE ================================ */
178 * flush_user_cache_all()
180 * Invalidate all cache entries in a particular address
183 ENTRY(xscale_flush_user_cache_all)
187 * flush_kern_cache_all()
189 * Clean and invalidate the entire cache.
191 ENTRY(xscale_flush_kern_cache_all)
197 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
198 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
202 * flush_user_cache_range(start, end, vm_flags)
204 * Invalidate a range of cache entries in the specified
207 * - start - start address (may not be aligned)
208 * - end - end address (exclusive, may not be aligned)
209 * - vma - vma_area_struct describing address space
212 ENTRY(xscale_flush_user_cache_range)
214 sub r3, r1, r0 @ calculate total size
215 cmp r3, #MAX_AREA_SIZE
216 bhs __flush_whole_cache
219 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
220 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
221 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
222 add r0, r0, #CACHELINESIZE
226 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
227 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
231 * coherent_kern_range(start, end)
233 * Ensure coherency between the Icache and the Dcache in the
234 * region described by start. If you have non-snooping
235 * Harvard caches, you need to implement this function.
237 * - start - virtual start address
238 * - end - virtual end address
240 * Note: single I-cache line invalidation isn't used here since
241 * it also trashes the mini I-cache used by JTAG debuggers.
243 ENTRY(xscale_coherent_kern_range)
244 bic r0, r0, #CACHELINESIZE - 1
245 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
246 add r0, r0, #CACHELINESIZE
250 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
251 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
255 * flush_kern_dcache_page(void *page)
257 * Ensure no D cache aliasing occurs, either with itself or
260 * - addr - page aligned address
262 ENTRY(xscale_flush_kern_dcache_page)
264 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
265 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
266 add r0, r0, #CACHELINESIZE
270 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
271 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
275 * dma_inv_range(start, end)
277 * Invalidate (discard) the specified virtual address range.
278 * May not write back any entries. If 'start' or 'end'
279 * are not cache line aligned, those lines must be written
282 * - start - virtual start address
283 * - end - virtual end address
285 ENTRY(xscale_dma_inv_range)
286 mrc p15, 0, r2, c0, c0, 0 @ read ID
287 eor r2, r2, #0x69000000
288 eor r2, r2, #0x00052000
290 beq xscale_dma_flush_range
292 tst r0, #CACHELINESIZE - 1
293 bic r0, r0, #CACHELINESIZE - 1
294 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
295 tst r1, #CACHELINESIZE - 1
296 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
297 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
298 add r0, r0, #CACHELINESIZE
301 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
305 * dma_clean_range(start, end)
307 * Clean the specified virtual address range.
309 * - start - virtual start address
310 * - end - virtual end address
312 ENTRY(xscale_dma_clean_range)
313 bic r0, r0, #CACHELINESIZE - 1
314 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
315 add r0, r0, #CACHELINESIZE
318 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
322 * dma_flush_range(start, end)
324 * Clean and invalidate the specified virtual address range.
326 * - start - virtual start address
327 * - end - virtual end address
329 ENTRY(xscale_dma_flush_range)
330 bic r0, r0, #CACHELINESIZE - 1
331 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
332 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
333 add r0, r0, #CACHELINESIZE
336 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
339 ENTRY(xscale_cache_fns)
340 .long xscale_flush_kern_cache_all
341 .long xscale_flush_user_cache_all
342 .long xscale_flush_user_cache_range
343 .long xscale_coherent_kern_range
344 .long xscale_flush_kern_dcache_page
345 .long xscale_dma_inv_range
346 .long xscale_dma_clean_range
347 .long xscale_dma_flush_range
349 ENTRY(cpu_xscale_dcache_clean_area)
350 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
351 add r0, r0, #CACHELINESIZE
352 subs r1, r1, #CACHELINESIZE
356 /* ================================ CACHE LOCKING============================
358 * The XScale MicroArchitecture implements support for locking entries into
359 * the data and instruction cache. The following functions implement the core
360 * low level instructions needed to accomplish the locking. The developer's
361 * manual states that the code that performs the locking must be in non-cached
362 * memory. To accomplish this, the code in xscale-cache-lock.c copies the
363 * following functions from the cache into a non-cached memory region that
364 * is allocated through consistent_alloc().
371 * r0: starting address to lock
372 * r1: end address to lock
374 ENTRY(xscale_icache_lock)
377 bic r0, r0, #CACHELINESIZE - 1
378 mcr p15, 0, r0, c9, c1, 0 @ lock into cache
379 cmp r0, r1 @ are we done?
380 add r0, r0, #CACHELINESIZE @ advance to next cache line
385 * xscale_icache_unlock
387 ENTRY(xscale_icache_unlock)
388 mcr p15, 0, r0, c9, c1, 1 @ Unlock icache
394 * r0: starting address to lock
395 * r1: end address to lock
397 ENTRY(xscale_dcache_lock)
398 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
400 mcr p15, 0, r2, c9, c2, 0 @ Put dcache in lock mode
401 cpwait ip @ Wait for completion
404 orr r3, r2, #PSR_F_BIT | PSR_I_BIT
407 mcr p15, 0, r0, c7, c10, 1 @ Write back line if it is dirty
408 mcr p15, 0, r0, c7, c6, 1 @ Flush/invalidate line
410 ldr ip, [r0], #CACHELINESIZE @ Preload 32 bytes into cache from
411 @ location [r0]. Post-increment
412 @ r3 to next cache line
413 cmp r0, r1 @ Are we done?
416 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
418 mcr p15, 0, r2, c9, c2, 0 @ Get out of lock mode
422 * xscale_dcache_unlock
424 ENTRY(xscale_dcache_unlock)
425 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
426 mcr p15, 0, ip, c9, c2, 1 @ Unlock cache
430 * Needed to determine the length of the code that needs to be copied.
433 ENTRY(xscale_cache_dummy)
436 /* ================================ TLB LOCKING==============================
438 * The XScale MicroArchitecture implements support for locking entries into
439 * the Instruction and Data TLBs. The following functions provide the
440 * low level support for supporting these under Linux. xscale-lock.c
441 * implements some higher level management code. Most of the following
442 * is taken straight out of the Developer's Manual.
448 * r0: Virtual address to translate and lock
451 ENTRY(xscale_itlb_lock)
453 orr r3, r2, #PSR_F_BIT | PSR_I_BIT
454 msr cpsr_c, r3 @ Disable interrupts
455 mcr p15, 0, r0, c8, c5, 1 @ Invalidate I-TLB entry
456 mcr p15, 0, r0, c10, c4, 0 @ Translate and lock
457 msr cpsr_c, r2 @ Restore interrupts
463 * r0: Virtual address to translate and lock
466 ENTRY(xscale_dtlb_lock)
468 orr r3, r2, #PSR_F_BIT | PSR_I_BIT
469 msr cpsr_c, r3 @ Disable interrupts
470 mcr p15, 0, r0, c8, c6, 1 @ Invalidate D-TLB entry
471 mcr p15, 0, r0, c10, c8, 0 @ Translate and lock
472 msr cpsr_c, r2 @ Restore interrupts
476 * Unlock all I-TLB entries
479 ENTRY(xscale_itlb_unlock)
480 mcr p15, 0, ip, c10, c4, 1 @ Unlock I-TLB
481 mcr p15, 0, ip, c8, c5, 0 @ Invalidate I-TLB
485 * Unlock all D-TLB entries
487 ENTRY(xscale_dtlb_unlock)
488 mcr p15, 0, ip, c10, c8, 1 @ Unlock D-TBL
489 mcr p15, 0, ip, c8, c6, 0 @ Invalidate D-TLB
492 /* =============================== PageTable ============================== */
494 #define PTE_CACHE_WRITE_ALLOCATE 0
497 * cpu_xscale_switch_mm(pgd)
499 * Set the translation base pointer to be as described by pgd.
501 * pgd: new page tables
504 ENTRY(cpu_xscale_switch_mm)
506 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
507 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
508 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
509 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
513 * cpu_xscale_set_pte(ptep, pte)
515 * Set a PTE and flush it out
517 * Errata 40: must set memory to write-through for user read-only pages.
520 ENTRY(cpu_xscale_set_pte)
521 str r1, [r0], #-2048 @ linux version
524 orr r2, r2, #PTE_TYPE_EXT @ extended page
526 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
528 tst r3, #L_PTE_USER @ User?
529 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
531 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
532 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
533 @ combined with user -> user r/w
536 @ Handle the X bit. We want to set this bit for the minicache
537 @ (U = E = B = W = 0, C = 1) or when write allocate is enabled,
538 @ and we have a writeable, cacheable region. If we ignore the
539 @ U and E bits, we can allow user space to use the minicache as
542 @ X = (C & ~W & ~B) | (C & W & B & write_allocate)
544 eor ip, r1, #L_PTE_CACHEABLE
545 tst ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
546 #if PTE_CACHE_WRITE_ALLOCATE
547 eorne ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
548 tstne ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
550 orreq r2, r2, #PTE_EXT_TEX(1)
553 @ Erratum 40: The B bit must be cleared for a user read-only
556 @ B = B & ~(U & C & ~W)
558 and ip, r1, #L_PTE_USER | L_PTE_WRITE | L_PTE_CACHEABLE
559 teq ip, #L_PTE_USER | L_PTE_CACHEABLE
560 biceq r2, r2, #PTE_BUFFERABLE
562 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
563 movne r2, #0 @ no -> fault
565 str r2, [r0] @ hardware version
567 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
568 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
578 .type __xscale_setup, #function
580 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
582 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
583 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
584 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
585 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
586 mov r0, #0x1f @ Domains 0, 1 = client
587 mcr p15, 0, r0, c3, c0, 0 @ load domain access register
588 mov r0, #1 @ Allow access to CP0 and CP13
589 orr r0, r0, #1 << 13 @ Its undefined whether this
590 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
591 mrc p15, 0, r0, c1, c0, 0 @ get control register
592 bic r0, r0, #0x0200 @ .... ..R. .... ....
593 bic r0, r0, #0x0002 @ .... .... .... ..A.
594 orr r0, r0, #0x0005 @ .... .... .... .C.M
595 orr r0, r0, #0x3900 @ ..VI Z..S .... ....
597 .size __xscale_setup, . - __xscale_setup
602 * Purpose : Function pointers used to access above functions - all calls
606 .type xscale_processor_functions, #object
607 ENTRY(xscale_processor_functions)
608 .word v5t_early_abort
609 .word cpu_xscale_proc_init
610 .word cpu_xscale_proc_fin
611 .word cpu_xscale_reset
612 .word cpu_xscale_do_idle
613 .word cpu_xscale_dcache_clean_area
614 .word cpu_xscale_switch_mm
615 .word cpu_xscale_set_pte
616 .size xscale_processor_functions, . - xscale_processor_functions
620 .type cpu_arch_name, #object
623 .size cpu_arch_name, . - cpu_arch_name
625 .type cpu_elf_name, #object
628 .size cpu_elf_name, . - cpu_elf_name
630 .type cpu_80200_name, #object
632 .asciz "XScale-80200"
633 .size cpu_80200_name, . - cpu_80200_name
635 .type cpu_80321_name, #object
637 .asciz "XScale-IOP80321"
638 .size cpu_80321_name, . - cpu_80321_name
640 .type cpu_pxa250_name, #object
642 .asciz "XScale-PXA250"
643 .size cpu_pxa250_name, . - cpu_pxa250_name
645 .type cpu_pxa210_name, #object
647 .asciz "XScale-PXA210"
648 .size cpu_pxa210_name, . - cpu_pxa210_name
650 .type cpu_ixp42x_name, #object
652 .asciz "XScale-IXP42x Family"
653 .size cpu_ixp42x_name, . - cpu_ixp42x_name
655 .type cpu_pxa255_name, #object
657 .asciz "XScale-PXA255"
658 .size cpu_pxa255_name, . - cpu_pxa255_name
660 .type cpu_pxa270_name, #object
662 .asciz "XScale-PXA270"
663 .size cpu_pxa270_name, . - cpu_pxa270_name
667 .section ".proc.info", #alloc, #execinstr
669 .type __80200_proc_info,#object
677 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
679 .long xscale_processor_functions
681 .long xscale_mc_user_fns
682 .long xscale_cache_fns
683 .size __80200_proc_info, . - __80200_proc_info
685 .type __80321_proc_info,#object
693 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
695 .long xscale_processor_functions
697 .long xscale_mc_user_fns
698 .long xscale_cache_fns
699 .size __80321_proc_info, . - __80321_proc_info
701 .type __pxa250_proc_info,#object
709 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
710 .long cpu_pxa250_name
711 .long xscale_processor_functions
713 .long xscale_mc_user_fns
714 .long xscale_cache_fns
715 .size __pxa250_proc_info, . - __pxa250_proc_info
717 .type __pxa210_proc_info,#object
725 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
726 .long cpu_pxa210_name
727 .long xscale_processor_functions
729 .long xscale_mc_user_fns
730 .long xscale_cache_fns
731 .size __pxa210_proc_info, . - __pxa210_proc_info
733 .type __ixp42x_proc_info, #object
741 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
742 .long cpu_ixp42x_name
743 .long xscale_processor_functions
745 .long xscale_mc_user_fns
746 .long xscale_cache_fns
747 .size __ixp42x_proc_info, . - __ixp42x_proc_info
749 .type __pxa255_proc_info,#object
757 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
758 .long cpu_pxa255_name
759 .long xscale_processor_functions
761 .long xscale_mc_user_fns
762 .long xscale_cache_fns
763 .size __pxa255_proc_info, . - __pxa255_proc_info
765 .type __pxa270_proc_info,#object
773 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
774 .long cpu_pxa270_name
775 .long xscale_processor_functions
777 .long xscale_mc_user_fns
778 .long xscale_cache_fns
779 .size __pxa270_proc_info, . - __pxa270_proc_info