1 /* $Id: ide.c,v 1.1 2004/01/22 08:22:58 starvik Exp $
3 * Etrax specific IDE functions, like init and PIO-mode setting etc.
4 * Almost the entire ide.c is used for the rest of the Etrax ATA driver.
5 * Copyright (c) 2000-2004 Axis Communications AB
7 * Authors: Bjorn Wesen (initial version)
8 * Mikael Starvik (pio setup stuff, Linux 2.6 port)
13 * There are two forms of DMA - "DMA handshaking" between the interface and the drive,
14 * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's
15 * something built-in in the Etrax. However only some drives support the DMA-mode handshaking
16 * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the
17 * device can't do DMA handshaking for some stupid reason. We don't need to do that.
20 #undef REALLY_SLOW_IO /* most systems can safely undef this */
22 #include <linux/config.h>
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/timer.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/blkdev.h>
30 #include <linux/hdreg.h>
31 #include <linux/ide.h>
32 #include <linux/init.h>
35 #include <asm/arch/svinto.h>
38 /* number of Etrax DMA descriptors */
39 #define MAX_DMA_DESCRS 64
41 /* number of times to retry busy-flags when reading/writing IDE-registers
42 * this can't be too high because a hung harddisk might cause the watchdog
43 * to trigger (sometimes INB and OUTB are called with irq's disabled)
46 #define IDE_REGISTER_TIMEOUT 300
48 #ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
49 /* address where the memory-mapped IDE reset bit lives, if used */
50 static volatile unsigned long *reset_addr;
53 static int e100_read_command = 0;
59 etrax100_ide_outw(unsigned short data, ide_ioreg_t reg) {
61 LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg));
63 /* note the lack of handling any timeouts. we stop waiting, but we don't
64 * really notify anybody.
67 timeleft = IDE_REGISTER_TIMEOUT;
68 /* wait for busy flag */
69 while(timeleft && (*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)))
73 * Fall through at a timeout, so the ongoing command will be
74 * aborted by the write below, which is expected to be a dummy
75 * command to the command register. This happens when a faulty
76 * drive times out on a command. See comment on timeout in
80 printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data);
82 *R_ATA_CTRL_DATA = reg | data; /* write data to the drive's register */
84 timeleft = IDE_REGISTER_TIMEOUT;
85 /* wait for transmitter ready */
86 while(timeleft && !(*R_ATA_STATUS_DATA &
87 IO_MASK(R_ATA_STATUS_DATA, tr_rdy)))
92 etrax100_ide_outb(unsigned char data, ide_ioreg_t reg)
94 etrax100_ide_outw(data, reg);
98 etrax100_ide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port)
100 etrax100_ide_outw(addr, port);
104 etrax100_ide_inw(ide_ioreg_t reg) {
108 timeleft = IDE_REGISTER_TIMEOUT;
109 /* wait for busy flag */
110 while(timeleft && (*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)))
115 * If we're asked to read the status register, like for
116 * example when a command does not complete for an
117 * extended time, but the ATA interface is stuck in a
118 * busy state at the *ETRAX* ATA interface level (as has
119 * happened repeatedly with at least one bad disk), then
120 * the best thing to do is to pretend that we read
121 * "busy" in the status register, so the IDE driver will
122 * time-out, abort the ongoing command and perform a
123 * reset sequence. Note that the subsequent OUT_BYTE
124 * call will also timeout on busy, but as long as the
125 * write is still performed, everything will be fine.
127 if ((reg & IO_MASK (R_ATA_CTRL_DATA, addr))
128 == IO_FIELD (R_ATA_CTRL_DATA, addr, IDE_STATUS_OFFSET))
131 /* For other rare cases we assume 0 is good enough. */
135 *R_ATA_CTRL_DATA = reg | IO_STATE(R_ATA_CTRL_DATA, rw, read); /* read data */
137 timeleft = IDE_REGISTER_TIMEOUT;
138 /* wait for available */
139 while(timeleft && !((status = *R_ATA_STATUS_DATA) &
140 IO_MASK(R_ATA_STATUS_DATA, dav)))
146 LOWDB(printk("inb: 0x%x from reg 0x%x\n", status & 0xff, reg));
148 return (unsigned short)status;
152 etrax100_ide_inb(ide_ioreg_t reg)
154 return (unsigned char)etrax100_ide_inw(reg);
157 /* PIO timing (in R_ATA_CONFIG)
159 * _____________________________
160 * ADDRESS : ________/
163 * DIOR : ____________/ \__________
166 * DATA : XXXXXXXXXXXXXXXX_______________XXXXXXXX
169 * DIOR is unbuffered while address and data is buffered.
170 * This creates two problems:
171 * 1. The DIOR pulse is to early (because it is unbuffered)
172 * 2. The rise time of DIOR is long
174 * There are at least three different plausible solutions
175 * 1. Use a pad capable of larger currents in Etrax
176 * 2. Use an external buffer
177 * 3. Make the strobe pulse longer
179 * Some of the strobe timings below are modified to compensate
180 * for this. This implies a slight performance decrease.
182 * THIS SHOULD NEVER BE CHANGED!
184 * TODO: Is this true for the latest LX boards still ?
187 #define ATA_DMA2_STROBE 4
188 #define ATA_DMA2_HOLD 0
189 #define ATA_DMA1_STROBE 4
190 #define ATA_DMA1_HOLD 1
191 #define ATA_DMA0_STROBE 12
192 #define ATA_DMA0_HOLD 9
193 #define ATA_PIO4_SETUP 1
194 #define ATA_PIO4_STROBE 5
195 #define ATA_PIO4_HOLD 0
196 #define ATA_PIO3_SETUP 1
197 #define ATA_PIO3_STROBE 5
198 #define ATA_PIO3_HOLD 1
199 #define ATA_PIO2_SETUP 1
200 #define ATA_PIO2_STROBE 6
201 #define ATA_PIO2_HOLD 2
202 #define ATA_PIO1_SETUP 2
203 #define ATA_PIO1_STROBE 11
204 #define ATA_PIO1_HOLD 4
205 #define ATA_PIO0_SETUP 4
206 #define ATA_PIO0_STROBE 19
207 #define ATA_PIO0_HOLD 4
209 static int e100_dma_check (ide_drive_t *drive);
210 static int e100_dma_begin (ide_drive_t *drive);
211 static int e100_dma_end (ide_drive_t *drive);
212 static int e100_dma_read (ide_drive_t *drive);
213 static int e100_dma_write (ide_drive_t *drive);
214 static void e100_ide_input_data (ide_drive_t *drive, void *, unsigned int);
215 static void e100_ide_output_data (ide_drive_t *drive, void *, unsigned int);
216 static void e100_atapi_input_bytes(ide_drive_t *drive, void *, unsigned int);
217 static void e100_atapi_output_bytes(ide_drive_t *drive, void *, unsigned int);
218 static int e100_dma_off (ide_drive_t *drive);
219 static int e100_dma_verbose (ide_drive_t *drive);
223 * good_dma_drives() lists the model names (from "hdparm -i")
224 * of drives which do not support mword2 DMA but which are
225 * known to work fine with this interface under Linux.
228 const char *good_dma_drives[] = {"Micropolis 2112A",
233 static void tune_e100_ide(ide_drive_t *drive, byte pio)
236 /* pio = ide_get_best_pio_mode(drive, pio, 4, NULL); */
242 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
243 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
244 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) |
245 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO0_SETUP ) |
246 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO0_STROBE ) |
247 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO0_HOLD ) );
250 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
251 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
252 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) |
253 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO1_SETUP ) |
254 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO1_STROBE ) |
255 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO1_HOLD ) );
258 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
259 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
260 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) |
261 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO2_SETUP ) |
262 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO2_STROBE ) |
263 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO2_HOLD ) );
266 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
267 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
268 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) |
269 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO3_SETUP ) |
270 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO3_STROBE ) |
271 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO3_HOLD ) );
274 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
275 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
276 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) |
277 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO4_SETUP ) |
278 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO4_STROBE ) |
279 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO4_HOLD ) );
287 volatile unsigned int dummy;
290 printk("ide: ETRAX 100LX built-in ATA DMA controller\n");
292 /* first fill in some stuff in the ide_hwifs fields */
294 for(h = 0; h < MAX_HWIFS; h++) {
295 ide_hwif_t *hwif = &ide_hwifs[h];
297 hwif->chipset = ide_etrax100;
298 hwif->tuneproc = &tune_e100_ide;
299 hwif->ata_input_data = &e100_ide_input_data;
300 hwif->ata_output_data = &e100_ide_output_data;
301 hwif->atapi_input_bytes = &e100_atapi_input_bytes;
302 hwif->atapi_output_bytes = &e100_atapi_output_bytes;
303 hwif->ide_dma_check = &e100_dma_check;
304 hwif->ide_dma_end = &e100_dma_end;
305 hwif->ide_dma_write = &e100_dma_write;
306 hwif->ide_dma_read = &e100_dma_read;
307 hwif->ide_dma_begin = &e100_dma_begin;
308 hwif->OUTB = &etrax100_ide_outb;
309 hwif->OUTW = &etrax100_ide_outw;
310 hwif->OUTBSYNC = &etrax100_ide_outbsync;
311 hwif->INB = &etrax100_ide_inb;
312 hwif->INW = &etrax100_ide_inw;
313 hwif->ide_dma_off_quietly = &e100_dma_off;
314 hwif->ide_dma_verbose = &e100_dma_verbose;
316 kmalloc(sizeof(struct scatterlist) * PRD_ENTRIES, GFP_KERNEL);
319 /* actually reset and configure the etrax100 ide/ata interface */
321 *R_ATA_CTRL_DATA = 0;
322 *R_ATA_TRANSFER_CNT = 0;
325 genconfig_shadow = (genconfig_shadow &
326 ~IO_MASK(R_GEN_CONFIG, dma2) &
327 ~IO_MASK(R_GEN_CONFIG, dma3) &
328 ~IO_MASK(R_GEN_CONFIG, ata)) |
329 ( IO_STATE( R_GEN_CONFIG, dma3, ata ) |
330 IO_STATE( R_GEN_CONFIG, dma2, ata ) |
331 IO_STATE( R_GEN_CONFIG, ata, select ) );
333 *R_GEN_CONFIG = genconfig_shadow;
335 /* pull the chosen /reset-line low */
337 #ifdef CONFIG_ETRAX_IDE_G27_RESET
338 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, 0);
340 #ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
341 REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, 0);
343 #ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET
344 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, 0);
346 #ifdef CONFIG_ETRAX_IDE_PB7_RESET
347 port_pb_dir_shadow = port_pb_dir_shadow |
348 IO_STATE(R_PORT_PB_DIR, dir7, output);
349 *R_PORT_PB_DIR = port_pb_dir_shadow;
350 REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, 1);
357 /* de-assert bus-reset */
359 #ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
360 REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, 1);
362 #ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET
363 REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, 1);
365 #ifdef CONFIG_ETRAX_IDE_G27_RESET
366 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, 1);
369 /* make a dummy read to set the ata controller in a proper state */
370 dummy = *R_ATA_STATUS_DATA;
372 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
373 IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
374 IO_FIELD( R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD ) |
375 IO_FIELD( R_ATA_CONFIG, pio_setup, ATA_PIO4_SETUP ) |
376 IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO4_STROBE ) |
377 IO_FIELD( R_ATA_CONFIG, pio_hold, ATA_PIO4_HOLD ) );
379 *R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw, read) |
380 IO_FIELD( R_ATA_CTRL_DATA, addr, 1 ) );
382 while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/
384 *R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) |
385 IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) |
386 IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) |
387 IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) );
389 printk("ide: waiting %d seconds for drives to regain consciousness\n",
390 CONFIG_ETRAX_IDE_DELAY);
392 h = jiffies + (CONFIG_ETRAX_IDE_DELAY * HZ);
393 while(time_before(jiffies, h)) /* nothing */ ;
395 /* reset the dma channels we will use */
397 RESET_DMA(ATA_TX_DMA_NBR);
398 RESET_DMA(ATA_RX_DMA_NBR);
399 WAIT_DMA(ATA_TX_DMA_NBR);
400 WAIT_DMA(ATA_RX_DMA_NBR);
404 static int e100_dma_off (ide_drive_t *drive)
409 static int e100_dma_verbose (ide_drive_t *drive)
411 printk(", DMA(mode 2)");
415 static etrax_dma_descr mydescr;
418 * The following routines are mainly used by the ATAPI drivers.
420 * These routines will round up any request for an odd number of bytes,
421 * so if an odd bytecount is specified, be sure that there's at least one
422 * extra byte allocated for the buffer.
425 e100_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
427 ide_ioreg_t data_reg = IDE_DATA_REG;
429 D(printk("atapi_input_bytes, dreg 0x%x, buffer 0x%x, count %d\n",
430 data_reg, buffer, bytecount));
433 printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount);
434 bytecount++; /* to round off */
437 /* make sure the DMA channel is available */
438 RESET_DMA(ATA_RX_DMA_NBR);
439 WAIT_DMA(ATA_RX_DMA_NBR);
441 /* setup DMA descriptor */
443 mydescr.sw_len = bytecount;
444 mydescr.ctrl = d_eol;
445 mydescr.buf = virt_to_phys(buffer);
447 /* start the dma channel */
449 *R_DMA_CH3_FIRST = virt_to_phys(&mydescr);
450 *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start);
452 /* initiate a multi word dma read using PIO handshaking */
454 *R_ATA_TRANSFER_CNT = IO_FIELD(R_ATA_TRANSFER_CNT, count, bytecount >> 1);
456 *R_ATA_CTRL_DATA = data_reg |
457 IO_STATE(R_ATA_CTRL_DATA, rw, read) |
458 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
459 IO_STATE(R_ATA_CTRL_DATA, handsh, pio) |
460 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
461 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
463 /* wait for completion */
466 WAIT_DMA(ATA_RX_DMA_NBR);
470 /* old polled transfer code
471 * this should be moved into a new function that can do polled
472 * transfers if DMA is not available
475 /* initiate a multi word read */
477 *R_ATA_TRANSFER_CNT = wcount << 1;
479 *R_ATA_CTRL_DATA = data_reg |
480 IO_STATE(R_ATA_CTRL_DATA, rw, read) |
481 IO_STATE(R_ATA_CTRL_DATA, src_dst, register) |
482 IO_STATE(R_ATA_CTRL_DATA, handsh, pio) |
483 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
484 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
486 /* svinto has a latency until the busy bit actually is set */
494 /* unit should be busy during multi transfer */
495 while((status = *R_ATA_STATUS_DATA) & IO_MASK(R_ATA_STATUS_DATA, busy)) {
496 while(!(status & IO_MASK(R_ATA_STATUS_DATA, dav)))
497 status = *R_ATA_STATUS_DATA;
498 *ptr++ = (unsigned short)(status & 0xffff);
504 e100_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
506 ide_ioreg_t data_reg = IDE_DATA_REG;
508 D(printk("atapi_output_bytes, dreg 0x%x, buffer 0x%x, count %d\n",
509 data_reg, buffer, bytecount));
512 printk("odd bytecount %d in atapi_out_bytes!\n", bytecount);
516 /* make sure the DMA channel is available */
517 RESET_DMA(ATA_TX_DMA_NBR);
518 WAIT_DMA(ATA_TX_DMA_NBR);
520 /* setup DMA descriptor */
522 mydescr.sw_len = bytecount;
523 mydescr.ctrl = d_eol;
524 mydescr.buf = virt_to_phys(buffer);
526 /* start the dma channel */
528 *R_DMA_CH2_FIRST = virt_to_phys(&mydescr);
529 *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start);
531 /* initiate a multi word dma write using PIO handshaking */
533 *R_ATA_TRANSFER_CNT = IO_FIELD(R_ATA_TRANSFER_CNT, count, bytecount >> 1);
535 *R_ATA_CTRL_DATA = data_reg |
536 IO_STATE(R_ATA_CTRL_DATA, rw, write) |
537 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
538 IO_STATE(R_ATA_CTRL_DATA, handsh, pio) |
539 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
540 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
542 /* wait for completion */
545 WAIT_DMA(ATA_TX_DMA_NBR);
549 /* old polled write code - see comment in input_bytes */
551 /* wait for busy flag */
552 while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy));
554 /* initiate a multi word write */
556 *R_ATA_TRANSFER_CNT = bytecount >> 1;
559 IO_STATE(R_ATA_CTRL_DATA, rw, write) |
560 IO_STATE(R_ATA_CTRL_DATA, src_dst, register) |
561 IO_STATE(R_ATA_CTRL_DATA, handsh, pio) |
562 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
563 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
567 /* Etrax will set busy = 1 until the multi pio transfer has finished
568 * and tr_rdy = 1 after each successful word transfer.
569 * When the last byte has been transferred Etrax will first set tr_tdy = 1
570 * and then busy = 0 (not in the same cycle). If we read busy before it
571 * has been set to 0 we will think that we should transfer more bytes
572 * and then tr_rdy would be 0 forever. This is solved by checking busy
577 *R_ATA_CTRL_DATA = ctrl | *ptr++;
578 while(!(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy)) &&
579 (*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)));
580 } while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy));
588 * This is used for most PIO data transfers *from* the IDE interface
591 e100_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
593 e100_atapi_input_bytes(drive, buffer, wcount << 2);
597 * This is used for most PIO data transfers *to* the IDE interface
600 e100_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
602 e100_atapi_output_bytes(drive, buffer, wcount << 2);
605 /* we only have one DMA channel on the chip for ATA, so we can keep these statically */
606 static etrax_dma_descr ata_descrs[MAX_DMA_DESCRS];
607 static unsigned int ata_tot_size;
610 * e100_ide_build_dmatable() prepares a dma request.
611 * Returns 0 if all went okay, returns 1 otherwise.
613 static int e100_ide_build_dmatable (ide_drive_t *drive)
615 ide_hwif_t *hwif = HWIF(drive);
616 struct scatterlist* sg;
617 struct request *rq = HWGROUP(drive)->rq;
618 unsigned long size, addr;
619 unsigned int count = 0;
626 if (HWGROUP(drive)->rq->flags & REQ_DRIVE_TASKFILE) {
627 u8 *virt_addr = rq->buffer;
628 int sector_count = rq->nr_sectors;
629 memset(&sg[0], 0, sizeof(*sg));
630 sg[0].page = virt_to_page(virt_addr);
631 sg[0].offset = offset_in_page(virt_addr);
632 sg[0].length = sector_count * SECTOR_SIZE;
633 hwif->sg_nents = i = 1;
637 hwif->sg_nents = i = blk_rq_map_sg(drive->queue, rq, hwif->sg_table);
643 * Determine addr and size of next buffer area. We assume that
644 * individual virtual buffers are always composed linearly in
645 * physical memory. For example, we assume that any 8kB buffer
646 * is always composed of two adjacent physical 4kB pages rather
647 * than two possibly non-adjacent physical 4kB pages.
649 /* group sequential buffers into one large buffer */
650 addr = page_to_phys(sg->page) + sg->offset;
651 size = sg_dma_len(sg);
653 if ((addr + size) != page_to_phys(sg->page) + sg->offset)
655 size += sg_dma_len(sg);
658 /* did we run out of descriptors? */
660 if(count >= MAX_DMA_DESCRS) {
661 printk("%s: too few DMA descriptors\n", drive->name);
665 /* however, this case is more difficult - R_ATA_TRANSFER_CNT cannot be more
666 than 65536 words per transfer, so in that case we need to either
667 1) use a DMA interrupt to re-trigger R_ATA_TRANSFER_CNT and continue with
669 2) simply do the request here, and get dma_intr to only ide_end_request on
670 those blocks that were actually set-up for transfer.
673 if(ata_tot_size + size > 131072) {
674 printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size);
678 /* If size > 65536 it has to be splitted into new descriptors. Since we don't handle
679 size > 131072 only one split is necessary */
682 /* ok we want to do IO at addr, size bytes. set up a new descriptor entry */
683 ata_descrs[count].sw_len = 0; /* 0 means 65536, this is a 16-bit field */
684 ata_descrs[count].ctrl = 0;
685 ata_descrs[count].buf = addr;
686 ata_descrs[count].next = virt_to_phys(&ata_descrs[count + 1]);
688 ata_tot_size += 65536;
689 /* size and addr should refere to not handled data */
693 /* ok we want to do IO at addr, size bytes. set up a new descriptor entry */
695 ata_descrs[count].sw_len = 0; /* 0 means 65536, this is a 16-bit field */
697 ata_descrs[count].sw_len = size;
699 ata_descrs[count].ctrl = 0;
700 ata_descrs[count].buf = addr;
701 ata_descrs[count].next = virt_to_phys(&ata_descrs[count + 1]);
703 ata_tot_size += size;
707 /* set the end-of-list flag on the last descriptor */
708 ata_descrs[count - 1].ctrl |= d_eol;
709 /* return and say all is ok */
713 printk("%s: empty DMA table?\n", drive->name);
714 return 1; /* let the PIO routines handle this weirdness */
717 static int config_drive_for_dma (ide_drive_t *drive)
720 struct hd_driveid *id = drive->id;
722 if (id && (id->capability & 1)) {
723 /* Enable DMA on any drive that supports mword2 DMA */
724 if ((id->field_valid & 2) && (id->dma_mword & 0x404) == 0x404) {
725 drive->using_dma = 1;
726 return 0; /* DMA enabled */
729 /* Consult the list of known "good" drives */
730 list = good_dma_drives;
732 if (!strcmp(*list++,id->model)) {
733 drive->using_dma = 1;
734 return 0; /* DMA enabled */
738 return 1; /* DMA not enabled */
742 * etrax_dma_intr() is the handler for disk read/write DMA interrupts
744 static ide_startstop_t etrax_dma_intr (ide_drive_t *drive)
752 dma_stat = HWIF(drive)->ide_dma_end(drive);
753 stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */
754 if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
757 rq = HWGROUP(drive)->rq;
758 for (i = rq->nr_sectors; i > 0;) {
759 i -= rq->current_nr_sectors;
760 DRIVER(drive)->end_request(drive, 1, rq->nr_sectors);
764 printk("%s: bad DMA status\n", drive->name);
766 return DRIVER(drive)->error(drive, "dma_intr", stat);
770 * Functions below initiates/aborts DMA read/write operations on a drive.
772 * The caller is assumed to have selected the drive and programmed the drive's
773 * sector address using CHS or LBA. All that remains is to prepare for DMA
774 * and then issue the actual read/write DMA/PIO command to the drive.
776 * For ATAPI devices, we just prepare for DMA and return. The caller should
777 * then issue the packet command to the drive and call us again with
778 * ide_dma_begin afterwards.
780 * Returns 0 if all went well.
781 * Returns 1 if DMA read/write could not be started, in which case
782 * the caller should revert to PIO for the current request.
785 static int e100_dma_check(ide_drive_t *drive)
787 return config_drive_for_dma (drive);
790 static int e100_dma_end(ide_drive_t *drive)
792 /* TODO: check if something went wrong with the DMA */
796 static int e100_start_dma(ide_drive_t *drive, int atapi, int reading)
800 RESET_DMA(ATA_RX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
801 WAIT_DMA(ATA_RX_DMA_NBR);
803 /* set up the Etrax DMA descriptors */
805 if(e100_ide_build_dmatable (drive))
809 /* set the irq handler which will finish the request when DMA is done */
811 ide_set_handler(drive, &etrax_dma_intr, WAIT_CMD, NULL);
813 /* issue cmd to drive */
814 if ((HWGROUP(drive)->rq->cmd == IDE_DRIVE_TASKFILE) &&
815 (drive->addressing == 1)) {
816 ide_task_t *args = HWGROUP(drive)->rq->special;
817 etrax100_ide_outb(args->tfRegister[IDE_COMMAND_OFFSET], IDE_COMMAND_REG);
818 } else if (drive->addressing) {
819 etrax100_ide_outb(WIN_READDMA_EXT, IDE_COMMAND_REG);
821 etrax100_ide_outb(WIN_READDMA, IDE_COMMAND_REG);
827 /* need to do this before RX DMA due to a chip bug
828 * it is enough to just flush the part of the cache that
829 * corresponds to the buffers we start, but since HD transfers
830 * usually are more than 8 kB, it is easier to optimize for the
831 * normal case and just flush the entire cache. its the only
832 * way to be sure! (OB movie quote)
835 *R_DMA_CH3_FIRST = virt_to_phys(ata_descrs);
836 *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start);
838 /* initiate a multi word dma read using DMA handshaking */
840 *R_ATA_TRANSFER_CNT =
841 IO_FIELD(R_ATA_TRANSFER_CNT, count, ata_tot_size >> 1);
844 IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) |
845 IO_STATE(R_ATA_CTRL_DATA, rw, read) |
846 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
847 IO_STATE(R_ATA_CTRL_DATA, handsh, dma) |
848 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
849 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
853 D(printk("dma read of %d bytes.\n", ata_tot_size));
858 RESET_DMA(ATA_TX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
859 WAIT_DMA(ATA_TX_DMA_NBR);
861 /* set up the Etrax DMA descriptors */
863 if(e100_ide_build_dmatable (drive))
867 /* set the irq handler which will finish the request when DMA is done */
869 ide_set_handler(drive, &etrax_dma_intr, WAIT_CMD, NULL);
871 /* issue cmd to drive */
872 if ((HWGROUP(drive)->rq->cmd == IDE_DRIVE_TASKFILE) &&
873 (drive->addressing == 1)) {
874 ide_task_t *args = HWGROUP(drive)->rq->special;
875 etrax100_ide_outb(args->tfRegister[IDE_COMMAND_OFFSET], IDE_COMMAND_REG);
876 } else if (drive->addressing) {
877 etrax100_ide_outb(WIN_WRITEDMA_EXT, IDE_COMMAND_REG);
879 etrax100_ide_outb(WIN_WRITEDMA, IDE_COMMAND_REG);
885 *R_DMA_CH2_FIRST = virt_to_phys(ata_descrs);
886 *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start);
888 /* initiate a multi word dma write using DMA handshaking */
890 *R_ATA_TRANSFER_CNT =
891 IO_FIELD(R_ATA_TRANSFER_CNT, count, ata_tot_size >> 1);
894 IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) |
895 IO_STATE(R_ATA_CTRL_DATA, rw, write) |
896 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
897 IO_STATE(R_ATA_CTRL_DATA, handsh, dma) |
898 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
899 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
903 D(printk("dma write of %d bytes.\n", ata_tot_size));
908 static int e100_dma_write(ide_drive_t *drive)
910 e100_read_command = 0;
911 /* ATAPI-devices (not disks) first call ide_dma_read/write to set the direction
912 * then they call ide_dma_begin after they have issued the appropriate drive command
913 * themselves to actually start the chipset DMA. so we just return here if we're
916 if (drive->media != ide_disk)
918 return e100_start_dma(drive, 0, 0);
921 static int e100_dma_read(ide_drive_t *drive)
923 e100_read_command = 1;
924 /* ATAPI-devices (not disks) first call ide_dma_read/write to set the direction
925 * then they call ide_dma_begin after they have issued the appropriate drive command
926 * themselves to actually start the chipset DMA. so we just return here if we're
929 if (drive->media != ide_disk)
931 return e100_start_dma(drive, 0, 1);
934 static int e100_dma_begin(ide_drive_t *drive)
936 /* begin DMA, used by ATAPI devices which want to issue the
937 * appropriate IDE command themselves.
939 * they have already called ide_dma_read/write to set the
940 * static reading flag, now they call ide_dma_begin to do
941 * the real stuff. we tell our code below not to issue
942 * any IDE commands itself and jump into it.
944 return e100_start_dma(drive, 1, e100_read_command);