1 /* $Id: time.c,v 1.2 2003/07/04 08:27:41 starvik Exp $
3 * linux/arch/cris/arch-v10/kernel/time.c
5 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
6 * Copyright (C) 1999-2002 Axis Communications AB
10 #include <linux/config.h>
11 #include <linux/timex.h>
12 #include <linux/time.h>
13 #include <linux/jiffies.h>
14 #include <linux/interrupt.h>
15 #include <linux/swap.h>
16 #include <linux/sched.h>
17 #include <linux/init.h>
18 #include <asm/arch/svinto.h>
19 #include <asm/types.h>
20 #include <asm/signal.h>
22 #include <asm/delay.h>
25 /* define this if you need to use print_timestamp */
26 /* it will make jiffies at 96 hz instead of 100 hz though */
27 #undef USE_CASCADE_TIMERS
29 extern void update_xtime_from_cmos(void);
30 extern int set_rtc_mmss(unsigned long nowtime);
31 extern int setup_irq(int, struct irqaction *);
34 unsigned long get_ns_in_jiffie(void)
36 unsigned char timer_count, t1;
37 unsigned short presc_count;
41 local_irq_save(flags);
43 timer_count = *R_TIMER0_DATA;
44 presc_count = *R_TIM_PRESC_STATUS;
45 /* presc_count might be wrapped */
48 if (timer_count != t1){
49 /* it wrapped, read prescaler again... */
50 presc_count = *R_TIM_PRESC_STATUS;
53 local_irq_restore(flags);
54 if (presc_count >= PRESCALE_VALUE/2 ){
55 presc_count = PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
57 presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
60 ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) +
61 ( (presc_count) * (1000000000/PRESCALE_FREQ));
65 unsigned long do_slow_gettimeoffset(void)
67 unsigned long count, t1;
68 unsigned long usec_count = 0;
69 unsigned short presc_count;
71 static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */
72 static unsigned long jiffies_p = 0;
75 * cache volatile jiffies temporarily; we have IRQs turned off.
77 unsigned long jiffies_t;
79 /* The timer interrupt comes from Etrax timer 0. In order to get
80 * better precision, we check the current value. It might have
81 * underflowed already though.
84 #ifndef CONFIG_SVINTO_SIM
85 /* Not available in the xsim simulator. */
86 count = *R_TIMER0_DATA;
87 presc_count = *R_TIM_PRESC_STATUS;
88 /* presc_count might be wrapped */
91 /* it wrapped, read prescaler again... */
92 presc_count = *R_TIM_PRESC_STATUS;
103 * avoiding timer inconsistencies (they are rare, but they happen)...
104 * there are one problem that must be avoided here:
105 * 1. the timer counter underflows
107 if( jiffies_t == jiffies_p ) {
108 if( count > count_p ) {
109 /* Timer wrapped, use new count and prescale
110 * increase the time corresponding to one jiffie
112 usec_count = 1000000/HZ;
115 jiffies_p = jiffies_t;
117 if (presc_count >= PRESCALE_VALUE/2 ){
118 presc_count = PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
120 presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
122 /* Convert timer value to usec */
123 usec_count += ( (TIMER0_DIV - count) * (1000000/HZ)/TIMER0_DIV ) +
124 (( (presc_count) * (1000000000/PRESCALE_FREQ))/1000);
129 /* Excerpt from the Etrax100 HSDD about the built-in watchdog:
131 * 3.10.4 Watchdog timer
133 * When the watchdog timer is started, it generates an NMI if the watchdog
134 * isn't restarted or stopped within 0.1 s. If it still isn't restarted or
135 * stopped after an additional 3.3 ms, the watchdog resets the chip.
136 * The watchdog timer is stopped after reset. The watchdog timer is controlled
137 * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
138 * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
139 * described in the table below:
141 * Watchdog Value written:
142 * state: To enable: To key: Operation:
143 * -------- ---------- ------- ----------
144 * stopped 0 X No effect.
145 * stopped 1 key_val Start watchdog with key = key_val.
146 * started 0 ~key Stop watchdog
147 * started 1 ~key Restart watchdog with key = ~key.
148 * started X new_key_val Change key to new_key_val.
150 * Note: '~' is the bitwise NOT operator.
154 /* right now, starting the watchdog is the same as resetting it */
155 #define start_watchdog reset_watchdog
157 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
158 static int watchdog_key = 0; /* arbitrary number */
161 /* number of pages to consider "out of memory". it is normal that the memory
162 * is used though, so put this really low.
165 #define WATCHDOG_MIN_FREE_PAGES 8
170 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
171 /* only keep watchdog happy as long as we have memory left! */
172 if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
173 /* reset the watchdog with the inverse of the old key */
174 watchdog_key ^= 0x7; /* invert key, which is 3 bits */
175 *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
176 IO_STATE(R_WATCHDOG, enable, start);
181 /* stop the watchdog - we still need the correct key */
186 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
187 watchdog_key ^= 0x7; /* invert key, which is 3 bits */
188 *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
189 IO_STATE(R_WATCHDOG, enable, stop);
193 /* last time the cmos clock got updated */
194 static long last_rtc_update = 0;
197 * timer_interrupt() needs to keep up the real-time clock,
198 * as well as call the "do_timer()" routine every clocktick
201 //static unsigned short myjiff; /* used by our debug routine print_timestamp */
203 static inline irqreturn_t
204 timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
206 /* acknowledge the timer irq */
208 #ifdef USE_CASCADE_TIMERS
210 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
211 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
212 IO_STATE( R_TIMER_CTRL, i1, clr) |
213 IO_STATE( R_TIMER_CTRL, tm1, run) |
214 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
215 IO_STATE( R_TIMER_CTRL, i0, clr) |
216 IO_STATE( R_TIMER_CTRL, tm0, run) |
217 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
219 *R_TIMER_CTRL = r_timer_ctrl_shadow |
220 IO_STATE(R_TIMER_CTRL, i0, clr);
223 /* reset watchdog otherwise it resets us! */
227 /* call the real timer interrupt handler */
232 * If we have an externally synchronized Linux clock, then update
233 * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
234 * called as close as possible to 500 ms before the new second starts.
236 * The division here is not time critical since it will run once in
239 if ((time_status & STA_UNSYNC) == 0 &&
240 xtime.tv_sec > last_rtc_update + 660 &&
241 (xtime.tv_nsec / 1000) >= 500000 - (tick_nsec / 1000) / 2 &&
242 (xtime.tv_nsec / 1000) <= 500000 + (tick_nsec / 1000) / 2) {
243 if (set_rtc_mmss(xtime.tv_sec) == 0)
244 last_rtc_update = xtime.tv_sec;
246 last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
251 /* timer is SA_SHIRQ so drivers can add stuff to the timer irq chain
252 * it needs to be SA_INTERRUPT to make the jiffies update work properly
255 static struct irqaction irq2 = { timer_interrupt, SA_SHIRQ | SA_INTERRUPT,
256 0, "timer", NULL, NULL};
261 /* probe for the RTC and read it if it exists
262 * Before the RTC can be probed the loops_per_usec variable needs
263 * to be initialized to make usleep work. A better value for
264 * loops_per_usec is calculated by the kernel later once the
270 /* no RTC, start at 1980 */
275 /* get the current time */
277 update_xtime_from_cmos();
280 /* Setup the etrax timers
281 * Base frequency is 25000 hz, divider 250 -> 100 HZ
282 * In normal mode, we use timer0, so timer1 is free. In cascade
283 * mode (which we sometimes use for debugging) both timers are used.
284 * Remember that linux/timex.h contains #defines that rely on the
285 * timer settings below (hz and divide factor) !!!
288 #ifdef USE_CASCADE_TIMERS
290 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
291 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
292 IO_STATE( R_TIMER_CTRL, i1, nop) |
293 IO_STATE( R_TIMER_CTRL, tm1, stop_ld) |
294 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
295 IO_STATE( R_TIMER_CTRL, i0, nop) |
296 IO_STATE( R_TIMER_CTRL, tm0, stop_ld) |
297 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
299 *R_TIMER_CTRL = r_timer_ctrl_shadow =
300 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
301 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
302 IO_STATE( R_TIMER_CTRL, i1, nop) |
303 IO_STATE( R_TIMER_CTRL, tm1, run) |
304 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
305 IO_STATE( R_TIMER_CTRL, i0, nop) |
306 IO_STATE( R_TIMER_CTRL, tm0, run) |
307 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
310 IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) |
311 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) |
312 IO_STATE(R_TIMER_CTRL, i1, nop) |
313 IO_STATE(R_TIMER_CTRL, tm1, stop_ld) |
314 IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) |
315 IO_STATE(R_TIMER_CTRL, i0, nop) |
316 IO_STATE(R_TIMER_CTRL, tm0, stop_ld) |
317 IO_STATE(R_TIMER_CTRL, clksel0, flexible);
319 *R_TIMER_CTRL = r_timer_ctrl_shadow =
320 IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) |
321 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) |
322 IO_STATE(R_TIMER_CTRL, i1, nop) |
323 IO_STATE(R_TIMER_CTRL, tm1, run) |
324 IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) |
325 IO_STATE(R_TIMER_CTRL, i0, nop) |
326 IO_STATE(R_TIMER_CTRL, tm0, run) |
327 IO_STATE(R_TIMER_CTRL, clksel0, flexible);
329 *R_TIMER_PRESCALE = PRESCALE_VALUE;
333 IO_STATE(R_IRQ_MASK0_SET, timer0, set); /* unmask the timer irq */
335 /* now actually register the timer irq handler that calls timer_interrupt() */
337 setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */
339 /* enable watchdog if we should use one */
341 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
342 printk("Enabling watchdog...\n");
345 /* If we use the hardware watchdog, we want to trap it as an NMI
346 and dump registers before it resets us. For this to happen, we
347 must set the "m" NMI enable flag (which once set, is unset only
348 when an NMI is taken).
350 The same goes for the external NMI, but that doesn't have any
351 driver or infrastructure support yet. */
355 IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
357 IO_STATE(R_VECT_MASK_SET, nmi, set);