1 /* $Id: dram_init.S,v 1.3 2003/03/31 09:38:37 starvik Exp $
3 * DRAM/SDRAM initialization - alter with care
4 * This file is intended to be included from other assembler files
6 * Note: This file may not modify r9 because r9 is used to carry
7 * information from the decompresser to the kernel
9 * Copyright (C) 2000, 2001 Axis Communications AB
11 * Authors: Mikael Starvik (starvik@axis.com)
13 * $Log: dram_init.S,v $
14 * Revision 1.3 2003/03/31 09:38:37 starvik
15 * Corrected calculation of end of sdram init commands
17 * Revision 1.2 2002/11/19 13:33:29 starvik
18 * Changes from Linux 2.4
20 * Revision 1.13 2002/10/30 07:42:28 starvik
21 * Always read SDRAM command sequence from flash
23 * Revision 1.12 2002/08/09 11:37:37 orjanf
24 * Added double initialization work-around for Samsung SDRAMs.
26 * Revision 1.11 2002/06/04 11:43:21 starvik
27 * Check if mrs_data is specified in kernelconfig (necessary for MCM)
29 * Revision 1.10 2001/10/04 12:00:21 martinnn
30 * Added missing underscores.
32 * Revision 1.9 2001/10/01 14:47:35 bjornw
33 * Added register prefixes and removed underscores
35 * Revision 1.8 2001/05/15 07:12:45 hp
36 * Copy warning from head.S about r8 and r9
38 * Revision 1.7 2001/04/18 12:05:39 bjornw
39 * Fixed comments, and explicitely include config.h to be sure its there
41 * Revision 1.6 2001/04/10 06:20:16 starvik
42 * Delay should be 200us, not 200ns
44 * Revision 1.5 2001/04/09 06:01:13 starvik
45 * Added support for 100 MHz SDRAMs
47 * Revision 1.4 2001/03/26 14:24:01 bjornw
48 * Namechange of some config options
50 * Revision 1.3 2001/03/23 08:29:41 starvik
51 * Corrected calculation of mrs_data
53 * Revision 1.2 2001/02/08 15:20:00 starvik
54 * Corrected SDRAM initialization
55 * Should now be included as inline
57 * Revision 1.1 2001/01/29 13:08:02 starvik
59 * This file should be included from all assembler files that needs to
60 * initialize DRAM/SDRAM.
64 /* Just to be certain the config file is included, we include it here
65 * explicitely instead of depending on it being included in the file that
69 #include <linux/config.h>
71 ;; WARNING! The registers r8 and r9 are used as parameters carrying
72 ;; information from the decompressor (if the kernel was compressed).
73 ;; They should not be used in the code below.
75 #ifndef CONFIG_SVINTO_SIM
76 move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
77 move.d $r0, [R_WAITSTATES]
79 move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
80 move.d $r0, [R_BUS_CONFIG]
82 #ifndef CONFIG_ETRAX_SDRAM
83 move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
84 move.d $r0, [R_DRAM_CONFIG]
86 move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
87 move.d $r0, [R_DRAM_TIMING]
89 ;; Samsung SDRAMs seem to require to be initialized twice to work properly.
93 ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
96 move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0
97 move.d $r0, [R_SDRAM_CONFIG]
99 ; Calculate value of mrs_data
100 ; CAS latency = 2 && bus_width = 32 => 0x40
101 ; CAS latency = 3 && bus_width = 32 => 0x60
102 ; CAS latency = 2 && bus_width = 16 => 0x20
103 ; CAS latency = 3 && bus_width = 16 => 0x30
105 ; Check if value is already supplied in kernel config
106 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r2
107 and.d 0x00ff0000, $r2
111 move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
112 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
114 and.d 0x03, $r1 ; Get CAS latency
115 and.d 0x1000, $r3 ; 50 or 100 MHz?
119 cmp.d 0x00, $r1 ; CAS latency = 2?
122 or.d 0x20, $r2 ; CAS latency = 3
126 cmp.d 0x01, $r1 ; CAS latency = 2?
129 or.d 0x20, $r2 ; CAS latency = 3
131 move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r1
132 and.d 0x800000, $r1 ; DRAM width is bit 23
135 lsrq 1, $r2 ; 16 bits. Shift down value.
137 ; Set timing parameters. Starts master clock
139 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
140 and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
141 or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
143 or.d 0x0000c000, $r1 ; ref = disable
144 lslq 16, $r2 ; mrs data starts at bit 16
146 move.d $r1, [R_SDRAM_TIMING]
153 ; Issue initialization command sequence
154 move.d _sdram_commands_start, $r2
155 and.d 0x00ffffff, $r2 ; Make sure commands are read from flash
156 move.d _sdram_commands_end, $r3
157 and.d 0x00ffffff, $r3
160 lslq 9, $r4 ; Command starts at bit 9
162 move.d $r4, [R_SDRAM_TIMING]
163 nop ; Wait five nop cycles between each command
171 move.d $r5, [R_SDRAM_TIMING]
175 ba _sdram_commands_end
178 _sdram_commands_start: