2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/config.h>
18 #include <linux/init.h>
21 #include <linux/irq.h>
22 #include <linux/delay.h>
23 #include <linux/bootmem.h>
24 #include <linux/smp_lock.h>
25 #include <linux/interrupt.h>
26 #include <linux/mc146818rtc.h>
27 #include <linux/kernel_stat.h>
28 #include <linux/sysdev.h>
30 #include <asm/atomic.h>
33 #include <asm/mpspec.h>
35 #include <asm/arch_hooks.h>
38 #include <mach_apic.h>
42 static void apic_pm_activate(void);
44 void __init apic_intr_init(void)
49 /* self generated IPI for local APIC timer */
50 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
52 /* IPI vectors for APIC spurious and error interrupts */
53 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
54 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
56 /* thermal monitor LVT interrupt */
57 #ifdef CONFIG_X86_MCE_P4THERMAL
58 set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
62 /* Using APIC to generate smp_local_timer_interrupt? */
63 int using_apic_timer = 0;
65 static DEFINE_PER_CPU(int, prof_multiplier) = 1;
66 static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
67 static DEFINE_PER_CPU(int, prof_counter) = 1;
69 static int enabled_via_apicbase;
71 void enable_NMI_through_LVT0 (void * dummy)
75 ver = apic_read(APIC_LVR);
76 ver = GET_APIC_VERSION(ver);
77 v = APIC_DM_NMI; /* unmask and set to NMI */
78 if (!APIC_INTEGRATED(ver)) /* 82489DX */
79 v |= APIC_LVT_LEVEL_TRIGGER;
80 apic_write_around(APIC_LVT0, v);
83 int get_physical_broadcast(void)
85 unsigned int lvr, version;
86 lvr = apic_read(APIC_LVR);
87 version = GET_APIC_VERSION(lvr);
96 unsigned int v, ver, maxlvt;
98 v = apic_read(APIC_LVR);
99 ver = GET_APIC_VERSION(v);
100 /* 82489DXs do not report # of LVT entries. */
101 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
105 void clear_local_APIC(void)
110 maxlvt = get_maxlvt();
113 * Masking an LVT entry on a P6 can trigger a local APIC error
114 * if the vector is zero. Mask LVTERR first to prevent this.
117 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
118 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
121 * Careful: we have to set masks only first to deassert
122 * any level-triggered sources.
124 v = apic_read(APIC_LVTT);
125 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
126 v = apic_read(APIC_LVT0);
127 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
128 v = apic_read(APIC_LVT1);
129 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
131 v = apic_read(APIC_LVTPC);
132 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
135 /* lets not touch this if we didn't frob it */
136 #ifdef CONFIG_X86_MCE_P4THERMAL
138 v = apic_read(APIC_LVTTHMR);
139 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
143 * Clean APIC state for other OSs:
145 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
146 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
147 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
149 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
151 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
153 #ifdef CONFIG_X86_MCE_P4THERMAL
155 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
157 v = GET_APIC_VERSION(apic_read(APIC_LVR));
158 if (APIC_INTEGRATED(v)) { /* !82489DX */
159 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
160 apic_write(APIC_ESR, 0);
165 void __init connect_bsp_APIC(void)
169 * Do not trust the local APIC being empty at bootup.
173 * PIC mode, enable APIC mode in the IMCR, i.e.
174 * connect BSP's local APIC to INT and NMI lines.
176 printk("leaving PIC mode, enabling APIC mode.\n");
183 void disconnect_bsp_APIC(void)
187 * Put the board back into PIC mode (has an effect
188 * only on certain older boards). Note that APIC
189 * interrupts, including IPIs, won't work beyond
190 * this point! The only exception are INIT IPIs.
192 printk("disabling APIC mode, entering PIC mode.\n");
197 /* Go back to Virtual Wire compatibility mode */
200 /* For the spurious interrupt use vector F, and enable it */
201 value = apic_read(APIC_SPIV);
202 value &= ~APIC_VECTOR_MASK;
203 value |= APIC_SPIV_APIC_ENABLED;
205 apic_write_around(APIC_SPIV, value);
207 /* For LVT0 make it edge triggered, active high, external and enabled */
208 value = apic_read(APIC_LVT0);
209 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
210 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
211 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
212 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
213 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXINT);
214 apic_write_around(APIC_LVT0, value);
216 /* For LVT1 make it edge triggered, active high, nmi and enabled */
217 value = apic_read(APIC_LVT1);
219 APIC_MODE_MASK | APIC_SEND_PENDING |
220 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
221 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
222 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
223 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
224 apic_write_around(APIC_LVT1, value);
228 void disable_local_APIC(void)
235 * Disable APIC (implies clearing of registers
238 value = apic_read(APIC_SPIV);
239 value &= ~APIC_SPIV_APIC_ENABLED;
240 apic_write_around(APIC_SPIV, value);
242 if (enabled_via_apicbase) {
244 rdmsr(MSR_IA32_APICBASE, l, h);
245 l &= ~MSR_IA32_APICBASE_ENABLE;
246 wrmsr(MSR_IA32_APICBASE, l, h);
251 * This is to verify that we're looking at a real local APIC.
252 * Check these against your board if the CPUs aren't getting
253 * started for no apparent reason.
255 int __init verify_local_APIC(void)
257 unsigned int reg0, reg1;
260 * The version register is read-only in a real APIC.
262 reg0 = apic_read(APIC_LVR);
263 Dprintk("Getting VERSION: %x\n", reg0);
264 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
265 reg1 = apic_read(APIC_LVR);
266 Dprintk("Getting VERSION: %x\n", reg1);
269 * The two version reads above should print the same
270 * numbers. If the second one is different, then we
271 * poke at a non-APIC.
277 * Check if the version looks reasonably.
279 reg1 = GET_APIC_VERSION(reg0);
280 if (reg1 == 0x00 || reg1 == 0xff)
283 if (reg1 < 0x02 || reg1 == 0xff)
287 * The ID register is read/write in a real APIC.
289 reg0 = apic_read(APIC_ID);
290 Dprintk("Getting ID: %x\n", reg0);
293 * The next two are just to see if we have sane values.
294 * They're only really relevant if we're in Virtual Wire
295 * compatibility mode, but most boxes are anymore.
297 reg0 = apic_read(APIC_LVT0);
298 Dprintk("Getting LVT0: %x\n", reg0);
299 reg1 = apic_read(APIC_LVT1);
300 Dprintk("Getting LVT1: %x\n", reg1);
305 void __init sync_Arb_IDs(void)
310 apic_wait_icr_idle();
312 Dprintk("Synchronizing Arb IDs.\n");
313 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
317 extern void __error_in_apic_c (void);
320 * An initial setup of the virtual wire mode.
322 void __init init_bsp_APIC(void)
324 unsigned long value, ver;
327 * Don't do the setup now if we have a SMP BIOS as the
328 * through-I/O-APIC virtual wire mode might be active.
330 if (smp_found_config || !cpu_has_apic)
333 value = apic_read(APIC_LVR);
334 ver = GET_APIC_VERSION(value);
337 * Do not trust the local APIC being empty at bootup.
344 value = apic_read(APIC_SPIV);
345 value &= ~APIC_VECTOR_MASK;
346 value |= APIC_SPIV_APIC_ENABLED;
348 /* This bit is reserved on P4/Xeon and should be cleared */
349 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
350 value &= ~APIC_SPIV_FOCUS_DISABLED;
352 value |= APIC_SPIV_FOCUS_DISABLED;
353 value |= SPURIOUS_APIC_VECTOR;
354 apic_write_around(APIC_SPIV, value);
357 * Set up the virtual wire mode.
359 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
361 if (!APIC_INTEGRATED(ver)) /* 82489DX */
362 value |= APIC_LVT_LEVEL_TRIGGER;
363 apic_write_around(APIC_LVT1, value);
366 void __init setup_local_APIC (void)
368 unsigned long value, ver, maxlvt;
370 /* Pound the ESR really hard over the head with a big hammer - mbligh */
372 apic_write(APIC_ESR, 0);
373 apic_write(APIC_ESR, 0);
374 apic_write(APIC_ESR, 0);
375 apic_write(APIC_ESR, 0);
378 value = apic_read(APIC_LVR);
379 ver = GET_APIC_VERSION(value);
381 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
385 * Double-check whether this APIC is really registered.
387 if (!apic_id_registered())
391 * Intel recommends to set DFR, LDR and TPR before enabling
392 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
393 * document number 292116). So here it goes...
398 * Set Task Priority to 'accept all'. We never change this
401 value = apic_read(APIC_TASKPRI);
402 value &= ~APIC_TPRI_MASK;
403 apic_write_around(APIC_TASKPRI, value);
406 * Now that we are all set up, enable the APIC
408 value = apic_read(APIC_SPIV);
409 value &= ~APIC_VECTOR_MASK;
413 value |= APIC_SPIV_APIC_ENABLED;
416 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
417 * certain networking cards. If high frequency interrupts are
418 * happening on a particular IOAPIC pin, plus the IOAPIC routing
419 * entry is masked/unmasked at a high rate as well then sooner or
420 * later IOAPIC line gets 'stuck', no more interrupts are received
421 * from the device. If focus CPU is disabled then the hang goes
424 * [ This bug can be reproduced easily with a level-triggered
425 * PCI Ne2000 networking cards and PII/PIII processors, dual
429 * Actually disabling the focus CPU check just makes the hang less
430 * frequent as it makes the interrupt distributon model be more
431 * like LRU than MRU (the short-term load is more even across CPUs).
432 * See also the comment in end_level_ioapic_irq(). --macro
435 /* Enable focus processor (bit==0) */
436 value &= ~APIC_SPIV_FOCUS_DISABLED;
438 /* Disable focus processor (bit==1) */
439 value |= APIC_SPIV_FOCUS_DISABLED;
442 * Set spurious IRQ vector
444 value |= SPURIOUS_APIC_VECTOR;
445 apic_write_around(APIC_SPIV, value);
450 * set up through-local-APIC on the BP's LINT0. This is not
451 * strictly necessery in pure symmetric-IO mode, but sometimes
452 * we delegate interrupts to the 8259A.
455 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
457 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
458 if (!smp_processor_id() && (pic_mode || !value)) {
459 value = APIC_DM_EXTINT;
460 printk("enabled ExtINT on CPU#%d\n", smp_processor_id());
462 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
463 printk("masked ExtINT on CPU#%d\n", smp_processor_id());
465 apic_write_around(APIC_LVT0, value);
468 * only the BP should see the LINT1 NMI signal, obviously.
470 if (!smp_processor_id())
473 value = APIC_DM_NMI | APIC_LVT_MASKED;
474 if (!APIC_INTEGRATED(ver)) /* 82489DX */
475 value |= APIC_LVT_LEVEL_TRIGGER;
476 apic_write_around(APIC_LVT1, value);
478 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
479 maxlvt = get_maxlvt();
480 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
481 apic_write(APIC_ESR, 0);
482 value = apic_read(APIC_ESR);
483 printk("ESR value before enabling vector: %08lx\n", value);
485 value = ERROR_APIC_VECTOR; // enables sending errors
486 apic_write_around(APIC_LVTERR, value);
488 * spec says clear errors after enabling vector.
491 apic_write(APIC_ESR, 0);
492 value = apic_read(APIC_ESR);
493 printk("ESR value after enabling vector: %08lx\n", value);
497 * Something untraceble is creating bad interrupts on
498 * secondary quads ... for the moment, just leave the
499 * ESR disabled - we can't do anything useful with the
500 * errors anyway - mbligh
502 printk("Leaving ESR disabled.\n");
504 printk("No ESR for 82489DX.\n");
507 if (nmi_watchdog == NMI_LOCAL_APIC)
508 setup_apic_nmi_watchdog();
515 /* 'active' is true if the local APIC was enabled by us and
516 not the BIOS; this signifies that we are also responsible
517 for disabling it before entering apm/acpi suspend */
519 /* r/w apic fields */
520 unsigned int apic_id;
521 unsigned int apic_taskpri;
522 unsigned int apic_ldr;
523 unsigned int apic_dfr;
524 unsigned int apic_spiv;
525 unsigned int apic_lvtt;
526 unsigned int apic_lvtpc;
527 unsigned int apic_lvt0;
528 unsigned int apic_lvt1;
529 unsigned int apic_lvterr;
530 unsigned int apic_tmict;
531 unsigned int apic_tdcr;
532 unsigned int apic_thmr;
535 static int lapic_suspend(struct sys_device *dev, u32 state)
539 if (!apic_pm_state.active)
542 apic_pm_state.apic_id = apic_read(APIC_ID);
543 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
544 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
545 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
546 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
547 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
548 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
549 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
550 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
551 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
552 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
553 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
554 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
556 local_irq_save(flags);
557 disable_local_APIC();
558 local_irq_restore(flags);
562 static int lapic_resume(struct sys_device *dev)
567 if (!apic_pm_state.active)
570 local_irq_save(flags);
573 * Make sure the APICBASE points to the right address
575 * FIXME! This will be wrong if we ever support suspend on
576 * SMP! We'll need to do this as part of the CPU restore!
578 rdmsr(MSR_IA32_APICBASE, l, h);
579 l &= ~MSR_IA32_APICBASE_BASE;
580 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
581 wrmsr(MSR_IA32_APICBASE, l, h);
583 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
584 apic_write(APIC_ID, apic_pm_state.apic_id);
585 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
586 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
587 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
588 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
589 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
590 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
591 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
592 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
593 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
594 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
595 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
596 apic_write(APIC_ESR, 0);
598 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
599 apic_write(APIC_ESR, 0);
601 local_irq_restore(flags);
606 static struct sysdev_class lapic_sysclass = {
607 set_kset_name("lapic"),
608 .resume = lapic_resume,
609 .suspend = lapic_suspend,
612 static struct sys_device device_lapic = {
614 .cls = &lapic_sysclass,
617 static void __init apic_pm_activate(void)
619 apic_pm_state.active = 1;
622 static int __init init_lapic_sysfs(void)
628 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
630 error = sysdev_class_register(&lapic_sysclass);
632 error = sysdev_register(&device_lapic);
635 device_initcall(init_lapic_sysfs);
637 #else /* CONFIG_PM */
639 static void apic_pm_activate(void) { }
641 #endif /* CONFIG_PM */
644 * Detect and enable local APICs on non-SMP boards.
645 * Original code written by Keir Fraser.
649 * Knob to control our willingness to enable the local APIC.
651 int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */
653 static int __init lapic_disable(char *str)
655 enable_local_apic = -1;
656 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
659 __setup("nolapic", lapic_disable);
661 static int __init lapic_enable(char *str)
663 enable_local_apic = 1;
666 __setup("lapic", lapic_enable);
668 static int __init detect_init_APIC (void)
671 extern void get_cpu_vendor(struct cpuinfo_x86*);
673 /* Disabled by DMI scan or kernel option? */
674 if (enable_local_apic < 0)
677 /* Workaround for us being called before identify_cpu(). */
678 get_cpu_vendor(&boot_cpu_data);
680 switch (boot_cpu_data.x86_vendor) {
682 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
683 (boot_cpu_data.x86 == 15))
686 case X86_VENDOR_INTEL:
687 if (boot_cpu_data.x86 == 6 ||
688 (boot_cpu_data.x86 == 15 && (cpu_has_apic || enable_local_apic > 0)) ||
689 (boot_cpu_data.x86 == 5 && cpu_has_apic))
698 * Some BIOSes disable the local APIC in the
699 * APIC_BASE MSR. This can only be done in
700 * software for Intel P6 and AMD K7 (Model > 1).
702 rdmsr(MSR_IA32_APICBASE, l, h);
703 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
704 printk("Local APIC disabled by BIOS -- reenabling.\n");
705 l &= ~MSR_IA32_APICBASE_BASE;
706 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
707 wrmsr(MSR_IA32_APICBASE, l, h);
708 enabled_via_apicbase = 1;
712 * The APIC feature bit should now be enabled
715 features = cpuid_edx(1);
716 if (!(features & (1 << X86_FEATURE_APIC))) {
717 printk("Could not enable APIC!\n");
720 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
721 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
723 /* The BIOS may have set up the APIC at some other address */
724 rdmsr(MSR_IA32_APICBASE, l, h);
725 if (l & MSR_IA32_APICBASE_ENABLE)
726 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
728 if (nmi_watchdog != NMI_NONE)
729 nmi_watchdog = NMI_LOCAL_APIC;
731 printk("Found and enabled local APIC!\n");
738 printk("No local APIC present or hardware disabled\n");
742 void __init init_apic_mappings(void)
744 unsigned long apic_phys;
747 * If no local APIC can be found then set up a fake all
748 * zeroes page to simulate the local APIC and another
749 * one for the IO-APIC.
751 if (!smp_found_config && detect_init_APIC()) {
752 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
753 apic_phys = __pa(apic_phys);
755 apic_phys = mp_lapic_addr;
757 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
758 Dprintk("mapped APIC to %08lx (%08lx)\n", APIC_BASE, apic_phys);
761 * Fetch the APIC ID of the BSP in case we have a
762 * default configuration (or the MP table is broken).
764 if (boot_cpu_physical_apicid == -1U)
765 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
767 #ifdef CONFIG_X86_IO_APIC
769 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
772 for (i = 0; i < nr_ioapics; i++) {
773 if (smp_found_config) {
774 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
776 printk(KERN_ERR "WARNING: bogus zero IO-APIC address found in MPTABLE, disabling IO/APIC support!\n");
778 smp_found_config = 0;
779 skip_ioapic_setup = 1;
780 goto fake_ioapic_page;
784 ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
785 ioapic_phys = __pa(ioapic_phys);
787 set_fixmap_nocache(idx, ioapic_phys);
788 Dprintk("mapped IOAPIC to %08lx (%08lx)\n",
789 __fix_to_virt(idx), ioapic_phys);
797 * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts
798 * per second. We assume that the caller has already set up the local
801 * The APIC timer is not exactly sync with the external timer chip, it
802 * closely follows bus clocks.
806 * The timer chip is already set up at HZ interrupts per second here,
807 * but we do not accept timer interrupts yet. We only allow the BP
810 static unsigned int __init get_8254_timer_count(void)
812 extern spinlock_t i8253_lock;
817 spin_lock_irqsave(&i8253_lock, flags);
819 outb_p(0x00, PIT_MODE);
820 count = inb_p(PIT_CH0);
821 count |= inb_p(PIT_CH0) << 8;
823 spin_unlock_irqrestore(&i8253_lock, flags);
828 /* next tick in 8254 can be caught by catching timer wraparound */
829 static void __init wait_8254_wraparound(void)
831 unsigned int curr_count, prev_count=~0;
834 curr_count = get_8254_timer_count();
837 prev_count = curr_count;
838 curr_count = get_8254_timer_count();
839 delta = curr_count-prev_count;
842 * This limit for delta seems arbitrary, but it isn't, it's
843 * slightly above the level of error a buggy Mercury/Neptune
844 * chipset timer can cause.
847 } while (delta < 300);
851 * Default initialization for 8254 timers. If we use other timers like HPET,
852 * we override this later
854 void (*wait_timer_tick)(void) = wait_8254_wraparound;
857 * This function sets up the local APIC timer, with a timeout of
858 * 'clocks' APIC bus clock. During calibration we actually call
859 * this function twice on the boot CPU, once with a bogus timeout
860 * value, second time for real. The other (noncalibrating) CPUs
861 * call this function only once, with the real, calibrated value.
863 * We do reads before writes even if unnecessary, to get around the
864 * P5 APIC double write bug.
867 #define APIC_DIVISOR 16
869 void __setup_APIC_LVTT(unsigned int clocks)
871 unsigned int lvtt_value, tmp_value, ver;
873 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
874 lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR;
875 if (!APIC_INTEGRATED(ver))
876 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
877 apic_write_around(APIC_LVTT, lvtt_value);
882 tmp_value = apic_read(APIC_TDCR);
883 apic_write_around(APIC_TDCR, (tmp_value
884 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
887 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
890 static void setup_APIC_timer(unsigned int clocks)
894 local_irq_save(flags);
897 * Wait for IRQ0's slice:
901 __setup_APIC_LVTT(clocks);
903 local_irq_restore(flags);
907 * In this function we calibrate APIC bus clocks to the external
908 * timer. Unfortunately we cannot use jiffies and the timer irq
909 * to calibrate, since some later bootup code depends on getting
910 * the first irq? Ugh.
912 * We want to do the calibration only once since we
913 * want to have local timer irqs syncron. CPUs connected
914 * by the same APIC bus have the very same bus frequency.
915 * And we want to have irqs off anyways, no accidental
919 int __init calibrate_APIC_clock(void)
921 unsigned long long t1 = 0, t2 = 0;
925 const int LOOPS = HZ/10;
927 printk("calibrating APIC timer ...\n");
930 * Put whatever arbitrary (but long enough) timeout
931 * value into the APIC clock, we just want to get the
932 * counter running for calibration.
934 __setup_APIC_LVTT(1000000000);
937 * The timer chip counts down to zero. Let's wait
938 * for a wraparound to start exact measurement:
939 * (the current tick might have been already half done)
945 * We wrapped around just now. Let's start:
949 tt1 = apic_read(APIC_TMCCT);
952 * Let's wait LOOPS wraprounds:
954 for (i = 0; i < LOOPS; i++)
957 tt2 = apic_read(APIC_TMCCT);
962 * The APIC bus clock counter is 32 bits only, it
963 * might have overflown, but note that we use signed
964 * longs, thus no extra care needed.
966 * underflown to be exact, as the timer counts down ;)
969 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
972 printk("..... CPU clock speed is %ld.%04ld MHz.\n",
973 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
974 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
976 printk("..... host bus clock speed is %ld.%04ld MHz.\n",
978 result%(1000000/HZ));
983 static unsigned int calibration_result;
985 void __init setup_boot_APIC_clock(void)
987 printk("Using local APIC timer interrupts.\n");
988 using_apic_timer = 1;
992 calibration_result = calibrate_APIC_clock();
994 * Now set up the timer for real.
996 setup_APIC_timer(calibration_result);
1001 void __init setup_secondary_APIC_clock(void)
1003 local_irq_disable(); /* FIXME: Do we need this? --RR */
1004 setup_APIC_timer(calibration_result);
1008 void __init disable_APIC_timer(void)
1010 if (using_apic_timer) {
1013 v = apic_read(APIC_LVTT);
1014 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
1018 void enable_APIC_timer(void)
1020 if (using_apic_timer) {
1023 v = apic_read(APIC_LVTT);
1024 apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
1029 * the frequency of the profiling timer can be changed
1030 * by writing a multiplier value into /proc/profile.
1032 int setup_profiling_timer(unsigned int multiplier)
1037 * Sanity check. [at least 500 APIC cycles should be
1038 * between APIC interrupts as a rule of thumb, to avoid
1041 if ( (!multiplier) || (calibration_result/multiplier < 500))
1045 * Set the new multiplier for each CPU. CPUs don't start using the
1046 * new values until the next timer interrupt in which they do process
1047 * accounting. At that time they also adjust their APIC timers
1050 for (i = 0; i < NR_CPUS; ++i)
1051 per_cpu(prof_multiplier, i) = multiplier;
1059 * Local timer interrupt handler. It does both profiling and
1060 * process statistics/rescheduling.
1062 * We do profiling in every local tick, statistics/rescheduling
1063 * happen only every 'profiling multiplier' ticks. The default
1064 * multiplier is 1 and it can be changed by writing the new multiplier
1065 * value into /proc/profile.
1068 inline void smp_local_timer_interrupt(struct pt_regs * regs)
1070 int cpu = smp_processor_id();
1072 x86_do_profile(regs);
1074 if (--per_cpu(prof_counter, cpu) <= 0) {
1076 * The multiplier may have changed since the last time we got
1077 * to this point as a result of the user writing to
1078 * /proc/profile. In this case we need to adjust the APIC
1079 * timer accordingly.
1081 * Interrupts are already masked off at this point.
1083 per_cpu(prof_counter, cpu) = per_cpu(prof_multiplier, cpu);
1084 if (per_cpu(prof_counter, cpu) !=
1085 per_cpu(prof_old_multiplier, cpu)) {
1088 per_cpu(prof_counter, cpu));
1089 per_cpu(prof_old_multiplier, cpu) =
1090 per_cpu(prof_counter, cpu);
1094 update_process_times(user_mode(regs));
1099 * We take the 'long' return path, and there every subsystem
1100 * grabs the apropriate locks (kernel lock/ irq lock).
1102 * we might want to decouple profiling from the 'long path',
1103 * and do the profiling totally in assembly.
1105 * Currently this isn't too much of an issue (performance wise),
1106 * we can take more than 100K local irqs per second on a 100 MHz P5.
1111 * Local APIC timer interrupt. This is the most natural way for doing
1112 * local interrupts, but local timer interrupts can be emulated by
1113 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1115 * [ if a single-CPU system runs an SMP kernel then we call the local
1116 * interrupt as well. Thus we cannot inline the local irq ... ]
1119 void smp_apic_timer_interrupt(struct pt_regs regs)
1121 int cpu = smp_processor_id();
1124 * the NMI deadlock-detector uses this.
1126 irq_stat[cpu].apic_timer_irqs++;
1129 * NOTE! We'd better ACK the irq immediately,
1130 * because timer handling can be slow.
1134 * update_process_times() expects us to have done irq_enter().
1135 * Besides, if we don't timer interrupts ignore the global
1136 * interrupt lock, which is the WrongThing (tm) to do.
1139 smp_local_timer_interrupt(®s);
1144 * This interrupt should _never_ happen with our APIC/SMP architecture
1146 asmlinkage void smp_spurious_interrupt(void)
1152 * Check if this really is a spurious interrupt and ACK it
1153 * if it is a vectored one. Just in case...
1154 * Spurious interrupts should not be ACKed.
1156 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1157 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1160 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1161 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n",
1162 smp_processor_id());
1167 * This interrupt should never happen with our APIC/SMP architecture
1170 asmlinkage void smp_error_interrupt(void)
1172 unsigned long v, v1;
1175 /* First tickle the hardware, only then report what went on. -- REW */
1176 v = apic_read(APIC_ESR);
1177 apic_write(APIC_ESR, 0);
1178 v1 = apic_read(APIC_ESR);
1180 atomic_inc(&irq_err_count);
1182 /* Here is what the APIC error bits mean:
1185 2: Send accept error
1186 3: Receive accept error
1188 5: Send illegal vector
1189 6: Received illegal vector
1190 7: Illegal register address
1192 printk (KERN_INFO "APIC error on CPU%d: %02lx(%02lx)\n",
1193 smp_processor_id(), v , v1);
1198 * This initializes the IO-APIC and APIC hardware if this is
1201 int __init APIC_init_uniprocessor (void)
1203 if (enable_local_apic < 0)
1204 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1206 if (!smp_found_config && !cpu_has_apic)
1210 * Complain if the BIOS pretends there is one.
1212 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1213 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1214 boot_cpu_physical_apicid);
1218 verify_local_APIC();
1222 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
1226 if (nmi_watchdog == NMI_LOCAL_APIC)
1227 check_nmi_watchdog();
1228 #ifdef CONFIG_X86_IO_APIC
1229 if (smp_found_config)
1230 if (!skip_ioapic_setup && nr_ioapics)
1233 setup_boot_APIC_clock();