2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/config.h>
18 #include <linux/init.h>
21 #include <linux/irq.h>
22 #include <linux/delay.h>
23 #include <linux/bootmem.h>
24 #include <linux/smp_lock.h>
25 #include <linux/interrupt.h>
26 #include <linux/mc146818rtc.h>
27 #include <linux/kernel_stat.h>
28 #include <linux/sysdev.h>
30 #include <asm/atomic.h>
33 #include <asm/mpspec.h>
35 #include <asm/arch_hooks.h>
38 #include <mach_apic.h>
42 static void apic_pm_activate(void);
44 void __init apic_intr_init(void)
49 /* self generated IPI for local APIC timer */
50 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
52 /* IPI vectors for APIC spurious and error interrupts */
53 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
54 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
56 /* thermal monitor LVT interrupt */
57 #ifdef CONFIG_X86_MCE_P4THERMAL
58 set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
62 /* Using APIC to generate smp_local_timer_interrupt? */
63 int using_apic_timer = 0;
65 static DEFINE_PER_CPU(int, prof_multiplier) = 1;
66 static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
67 static DEFINE_PER_CPU(int, prof_counter) = 1;
69 static int enabled_via_apicbase;
71 void enable_NMI_through_LVT0 (void * dummy)
75 ver = apic_read(APIC_LVR);
76 ver = GET_APIC_VERSION(ver);
77 v = APIC_DM_NMI; /* unmask and set to NMI */
78 if (!APIC_INTEGRATED(ver)) /* 82489DX */
79 v |= APIC_LVT_LEVEL_TRIGGER;
80 apic_write_around(APIC_LVT0, v);
83 int get_physical_broadcast(void)
85 unsigned int lvr, version;
86 lvr = apic_read(APIC_LVR);
87 version = GET_APIC_VERSION(lvr);
96 unsigned int v, ver, maxlvt;
98 v = apic_read(APIC_LVR);
99 ver = GET_APIC_VERSION(v);
100 /* 82489DXs do not report # of LVT entries. */
101 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
105 void clear_local_APIC(void)
110 maxlvt = get_maxlvt();
113 * Masking an LVT entry on a P6 can trigger a local APIC error
114 * if the vector is zero. Mask LVTERR first to prevent this.
117 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
118 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
121 * Careful: we have to set masks only first to deassert
122 * any level-triggered sources.
124 v = apic_read(APIC_LVTT);
125 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
126 v = apic_read(APIC_LVT0);
127 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
128 v = apic_read(APIC_LVT1);
129 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
131 v = apic_read(APIC_LVTPC);
132 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
135 /* lets not touch this if we didn't frob it */
136 #ifdef CONFIG_X86_MCE_P4THERMAL
138 v = apic_read(APIC_LVTTHMR);
139 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
143 * Clean APIC state for other OSs:
145 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
146 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
147 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
149 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
151 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
153 #ifdef CONFIG_X86_MCE_P4THERMAL
155 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
157 v = GET_APIC_VERSION(apic_read(APIC_LVR));
158 if (APIC_INTEGRATED(v)) { /* !82489DX */
159 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
160 apic_write(APIC_ESR, 0);
165 void __init connect_bsp_APIC(void)
169 * Do not trust the local APIC being empty at bootup.
173 * PIC mode, enable APIC mode in the IMCR, i.e.
174 * connect BSP's local APIC to INT and NMI lines.
176 printk("leaving PIC mode, enabling APIC mode.\n");
183 void disconnect_bsp_APIC(void)
187 * Put the board back into PIC mode (has an effect
188 * only on certain older boards). Note that APIC
189 * interrupts, including IPIs, won't work beyond
190 * this point! The only exception are INIT IPIs.
192 printk("disabling APIC mode, entering PIC mode.\n");
198 void disable_local_APIC(void)
205 * Disable APIC (implies clearing of registers
208 value = apic_read(APIC_SPIV);
209 value &= ~APIC_SPIV_APIC_ENABLED;
210 apic_write_around(APIC_SPIV, value);
212 if (enabled_via_apicbase) {
214 rdmsr(MSR_IA32_APICBASE, l, h);
215 l &= ~MSR_IA32_APICBASE_ENABLE;
216 wrmsr(MSR_IA32_APICBASE, l, h);
221 * This is to verify that we're looking at a real local APIC.
222 * Check these against your board if the CPUs aren't getting
223 * started for no apparent reason.
225 int __init verify_local_APIC(void)
227 unsigned int reg0, reg1;
230 * The version register is read-only in a real APIC.
232 reg0 = apic_read(APIC_LVR);
233 Dprintk("Getting VERSION: %x\n", reg0);
234 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
235 reg1 = apic_read(APIC_LVR);
236 Dprintk("Getting VERSION: %x\n", reg1);
239 * The two version reads above should print the same
240 * numbers. If the second one is different, then we
241 * poke at a non-APIC.
247 * Check if the version looks reasonably.
249 reg1 = GET_APIC_VERSION(reg0);
250 if (reg1 == 0x00 || reg1 == 0xff)
253 if (reg1 < 0x02 || reg1 == 0xff)
257 * The ID register is read/write in a real APIC.
259 reg0 = apic_read(APIC_ID);
260 Dprintk("Getting ID: %x\n", reg0);
263 * The next two are just to see if we have sane values.
264 * They're only really relevant if we're in Virtual Wire
265 * compatibility mode, but most boxes are anymore.
267 reg0 = apic_read(APIC_LVT0);
268 Dprintk("Getting LVT0: %x\n", reg0);
269 reg1 = apic_read(APIC_LVT1);
270 Dprintk("Getting LVT1: %x\n", reg1);
275 void __init sync_Arb_IDs(void)
280 apic_wait_icr_idle();
282 Dprintk("Synchronizing Arb IDs.\n");
283 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
287 extern void __error_in_apic_c (void);
290 * An initial setup of the virtual wire mode.
292 void __init init_bsp_APIC(void)
294 unsigned long value, ver;
297 * Don't do the setup now if we have a SMP BIOS as the
298 * through-I/O-APIC virtual wire mode might be active.
300 if (smp_found_config || !cpu_has_apic)
303 value = apic_read(APIC_LVR);
304 ver = GET_APIC_VERSION(value);
307 * Do not trust the local APIC being empty at bootup.
314 value = apic_read(APIC_SPIV);
315 value &= ~APIC_VECTOR_MASK;
316 value |= APIC_SPIV_APIC_ENABLED;
318 /* This bit is reserved on P4/Xeon and should be cleared */
319 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
320 value &= ~APIC_SPIV_FOCUS_DISABLED;
322 value |= APIC_SPIV_FOCUS_DISABLED;
323 value |= SPURIOUS_APIC_VECTOR;
324 apic_write_around(APIC_SPIV, value);
327 * Set up the virtual wire mode.
329 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
331 if (!APIC_INTEGRATED(ver)) /* 82489DX */
332 value |= APIC_LVT_LEVEL_TRIGGER;
333 apic_write_around(APIC_LVT1, value);
336 void __init setup_local_APIC (void)
338 unsigned long value, ver, maxlvt;
340 /* Pound the ESR really hard over the head with a big hammer - mbligh */
342 apic_write(APIC_ESR, 0);
343 apic_write(APIC_ESR, 0);
344 apic_write(APIC_ESR, 0);
345 apic_write(APIC_ESR, 0);
348 value = apic_read(APIC_LVR);
349 ver = GET_APIC_VERSION(value);
351 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
355 * Double-check whether this APIC is really registered.
357 if (!apic_id_registered())
361 * Intel recommends to set DFR, LDR and TPR before enabling
362 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
363 * document number 292116). So here it goes...
368 * Set Task Priority to 'accept all'. We never change this
371 value = apic_read(APIC_TASKPRI);
372 value &= ~APIC_TPRI_MASK;
373 apic_write_around(APIC_TASKPRI, value);
376 * Now that we are all set up, enable the APIC
378 value = apic_read(APIC_SPIV);
379 value &= ~APIC_VECTOR_MASK;
383 value |= APIC_SPIV_APIC_ENABLED;
386 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
387 * certain networking cards. If high frequency interrupts are
388 * happening on a particular IOAPIC pin, plus the IOAPIC routing
389 * entry is masked/unmasked at a high rate as well then sooner or
390 * later IOAPIC line gets 'stuck', no more interrupts are received
391 * from the device. If focus CPU is disabled then the hang goes
394 * [ This bug can be reproduced easily with a level-triggered
395 * PCI Ne2000 networking cards and PII/PIII processors, dual
399 * Actually disabling the focus CPU check just makes the hang less
400 * frequent as it makes the interrupt distributon model be more
401 * like LRU than MRU (the short-term load is more even across CPUs).
402 * See also the comment in end_level_ioapic_irq(). --macro
405 /* Enable focus processor (bit==0) */
406 value &= ~APIC_SPIV_FOCUS_DISABLED;
408 /* Disable focus processor (bit==1) */
409 value |= APIC_SPIV_FOCUS_DISABLED;
412 * Set spurious IRQ vector
414 value |= SPURIOUS_APIC_VECTOR;
415 apic_write_around(APIC_SPIV, value);
420 * set up through-local-APIC on the BP's LINT0. This is not
421 * strictly necessery in pure symmetric-IO mode, but sometimes
422 * we delegate interrupts to the 8259A.
425 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
427 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
428 if (!smp_processor_id() && (pic_mode || !value)) {
429 value = APIC_DM_EXTINT;
430 printk("enabled ExtINT on CPU#%d\n", smp_processor_id());
432 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
433 printk("masked ExtINT on CPU#%d\n", smp_processor_id());
435 apic_write_around(APIC_LVT0, value);
438 * only the BP should see the LINT1 NMI signal, obviously.
440 if (!smp_processor_id())
443 value = APIC_DM_NMI | APIC_LVT_MASKED;
444 if (!APIC_INTEGRATED(ver)) /* 82489DX */
445 value |= APIC_LVT_LEVEL_TRIGGER;
446 apic_write_around(APIC_LVT1, value);
448 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
449 maxlvt = get_maxlvt();
450 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
451 apic_write(APIC_ESR, 0);
452 value = apic_read(APIC_ESR);
453 printk("ESR value before enabling vector: %08lx\n", value);
455 value = ERROR_APIC_VECTOR; // enables sending errors
456 apic_write_around(APIC_LVTERR, value);
458 * spec says clear errors after enabling vector.
461 apic_write(APIC_ESR, 0);
462 value = apic_read(APIC_ESR);
463 printk("ESR value after enabling vector: %08lx\n", value);
467 * Something untraceble is creating bad interrupts on
468 * secondary quads ... for the moment, just leave the
469 * ESR disabled - we can't do anything useful with the
470 * errors anyway - mbligh
472 printk("Leaving ESR disabled.\n");
474 printk("No ESR for 82489DX.\n");
477 if (nmi_watchdog == NMI_LOCAL_APIC)
478 setup_apic_nmi_watchdog();
485 /* 'active' is true if the local APIC was enabled by us and
486 not the BIOS; this signifies that we are also responsible
487 for disabling it before entering apm/acpi suspend */
489 /* r/w apic fields */
490 unsigned int apic_id;
491 unsigned int apic_taskpri;
492 unsigned int apic_ldr;
493 unsigned int apic_dfr;
494 unsigned int apic_spiv;
495 unsigned int apic_lvtt;
496 unsigned int apic_lvtpc;
497 unsigned int apic_lvt0;
498 unsigned int apic_lvt1;
499 unsigned int apic_lvterr;
500 unsigned int apic_tmict;
501 unsigned int apic_tdcr;
502 unsigned int apic_thmr;
505 static int lapic_suspend(struct sys_device *dev, u32 state)
509 if (!apic_pm_state.active)
512 apic_pm_state.apic_id = apic_read(APIC_ID);
513 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
514 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
515 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
516 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
517 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
518 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
519 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
520 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
521 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
522 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
523 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
524 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
526 local_irq_save(flags);
527 disable_local_APIC();
528 local_irq_restore(flags);
532 static int lapic_resume(struct sys_device *dev)
537 if (!apic_pm_state.active)
540 local_irq_save(flags);
543 * Make sure the APICBASE points to the right address
545 * FIXME! This will be wrong if we ever support suspend on
546 * SMP! We'll need to do this as part of the CPU restore!
548 rdmsr(MSR_IA32_APICBASE, l, h);
549 l &= ~MSR_IA32_APICBASE_BASE;
550 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
551 wrmsr(MSR_IA32_APICBASE, l, h);
553 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
554 apic_write(APIC_ID, apic_pm_state.apic_id);
555 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
556 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
557 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
558 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
559 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
560 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
561 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
562 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
563 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
564 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
565 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
566 apic_write(APIC_ESR, 0);
568 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
569 apic_write(APIC_ESR, 0);
571 local_irq_restore(flags);
576 static struct sysdev_class lapic_sysclass = {
577 set_kset_name("lapic"),
578 .resume = lapic_resume,
579 .suspend = lapic_suspend,
582 static struct sys_device device_lapic = {
584 .cls = &lapic_sysclass,
587 static void __init apic_pm_activate(void)
589 apic_pm_state.active = 1;
592 static int __init init_lapic_sysfs(void)
598 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
600 error = sysdev_class_register(&lapic_sysclass);
602 error = sysdev_register(&device_lapic);
605 device_initcall(init_lapic_sysfs);
607 #else /* CONFIG_PM */
609 static void apic_pm_activate(void) { }
611 #endif /* CONFIG_PM */
614 * Detect and enable local APICs on non-SMP boards.
615 * Original code written by Keir Fraser.
619 * Knob to control our willingness to enable the local APIC.
621 int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */
623 static int __init lapic_disable(char *str)
625 enable_local_apic = -1;
626 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
629 __setup("nolapic", lapic_disable);
631 static int __init lapic_enable(char *str)
633 enable_local_apic = 1;
636 __setup("lapic", lapic_enable);
638 static int __init detect_init_APIC (void)
641 extern void get_cpu_vendor(struct cpuinfo_x86*);
643 /* Disabled by DMI scan or kernel option? */
644 if (enable_local_apic < 0)
647 /* Workaround for us being called before identify_cpu(). */
648 get_cpu_vendor(&boot_cpu_data);
650 switch (boot_cpu_data.x86_vendor) {
652 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
653 (boot_cpu_data.x86 == 15))
656 case X86_VENDOR_INTEL:
657 if (boot_cpu_data.x86 == 6 ||
658 (boot_cpu_data.x86 == 15 && (cpu_has_apic || enable_local_apic > 0)) ||
659 (boot_cpu_data.x86 == 5 && cpu_has_apic))
668 * Some BIOSes disable the local APIC in the
669 * APIC_BASE MSR. This can only be done in
670 * software for Intel P6 and AMD K7 (Model > 1).
672 rdmsr(MSR_IA32_APICBASE, l, h);
673 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
674 printk("Local APIC disabled by BIOS -- reenabling.\n");
675 l &= ~MSR_IA32_APICBASE_BASE;
676 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
677 wrmsr(MSR_IA32_APICBASE, l, h);
678 enabled_via_apicbase = 1;
682 * The APIC feature bit should now be enabled
685 features = cpuid_edx(1);
686 if (!(features & (1 << X86_FEATURE_APIC))) {
687 printk("Could not enable APIC!\n");
690 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
691 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
693 /* The BIOS may have set up the APIC at some other address */
694 rdmsr(MSR_IA32_APICBASE, l, h);
695 if (l & MSR_IA32_APICBASE_ENABLE)
696 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
698 if (nmi_watchdog != NMI_NONE)
699 nmi_watchdog = NMI_LOCAL_APIC;
701 printk("Found and enabled local APIC!\n");
708 printk("No local APIC present or hardware disabled\n");
712 void __init init_apic_mappings(void)
714 unsigned long apic_phys;
717 * If no local APIC can be found then set up a fake all
718 * zeroes page to simulate the local APIC and another
719 * one for the IO-APIC.
721 if (!smp_found_config && detect_init_APIC()) {
722 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
723 apic_phys = __pa(apic_phys);
725 apic_phys = mp_lapic_addr;
727 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
728 Dprintk("mapped APIC to %08lx (%08lx)\n", APIC_BASE, apic_phys);
731 * Fetch the APIC ID of the BSP in case we have a
732 * default configuration (or the MP table is broken).
734 if (boot_cpu_physical_apicid == -1U)
735 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
737 #ifdef CONFIG_X86_IO_APIC
739 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
742 for (i = 0; i < nr_ioapics; i++) {
743 if (smp_found_config) {
744 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
746 printk(KERN_ERR "WARNING: bogus zero IO-APIC address found in MPTABLE, disabling IO/APIC support!\n");
748 smp_found_config = 0;
749 skip_ioapic_setup = 1;
750 goto fake_ioapic_page;
754 ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
755 ioapic_phys = __pa(ioapic_phys);
757 set_fixmap_nocache(idx, ioapic_phys);
758 Dprintk("mapped IOAPIC to %08lx (%08lx)\n",
759 __fix_to_virt(idx), ioapic_phys);
767 * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts
768 * per second. We assume that the caller has already set up the local
771 * The APIC timer is not exactly sync with the external timer chip, it
772 * closely follows bus clocks.
776 * The timer chip is already set up at HZ interrupts per second here,
777 * but we do not accept timer interrupts yet. We only allow the BP
780 static unsigned int __init get_8254_timer_count(void)
782 extern spinlock_t i8253_lock;
787 spin_lock_irqsave(&i8253_lock, flags);
789 outb_p(0x00, PIT_MODE);
790 count = inb_p(PIT_CH0);
791 count |= inb_p(PIT_CH0) << 8;
793 spin_unlock_irqrestore(&i8253_lock, flags);
798 /* next tick in 8254 can be caught by catching timer wraparound */
799 static void __init wait_8254_wraparound(void)
801 unsigned int curr_count, prev_count=~0;
804 curr_count = get_8254_timer_count();
807 prev_count = curr_count;
808 curr_count = get_8254_timer_count();
809 delta = curr_count-prev_count;
812 * This limit for delta seems arbitrary, but it isn't, it's
813 * slightly above the level of error a buggy Mercury/Neptune
814 * chipset timer can cause.
817 } while (delta < 300);
821 * Default initialization for 8254 timers. If we use other timers like HPET,
822 * we override this later
824 void (*wait_timer_tick)(void) = wait_8254_wraparound;
827 * This function sets up the local APIC timer, with a timeout of
828 * 'clocks' APIC bus clock. During calibration we actually call
829 * this function twice on the boot CPU, once with a bogus timeout
830 * value, second time for real. The other (noncalibrating) CPUs
831 * call this function only once, with the real, calibrated value.
833 * We do reads before writes even if unnecessary, to get around the
834 * P5 APIC double write bug.
837 #define APIC_DIVISOR 16
839 void __setup_APIC_LVTT(unsigned int clocks)
841 unsigned int lvtt_value, tmp_value, ver;
843 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
844 lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR;
845 if (!APIC_INTEGRATED(ver))
846 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
847 apic_write_around(APIC_LVTT, lvtt_value);
852 tmp_value = apic_read(APIC_TDCR);
853 apic_write_around(APIC_TDCR, (tmp_value
854 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
857 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
860 static void setup_APIC_timer(unsigned int clocks)
864 local_irq_save(flags);
867 * Wait for IRQ0's slice:
871 __setup_APIC_LVTT(clocks);
873 local_irq_restore(flags);
877 * In this function we calibrate APIC bus clocks to the external
878 * timer. Unfortunately we cannot use jiffies and the timer irq
879 * to calibrate, since some later bootup code depends on getting
880 * the first irq? Ugh.
882 * We want to do the calibration only once since we
883 * want to have local timer irqs syncron. CPUs connected
884 * by the same APIC bus have the very same bus frequency.
885 * And we want to have irqs off anyways, no accidental
889 int __init calibrate_APIC_clock(void)
891 unsigned long long t1 = 0, t2 = 0;
895 const int LOOPS = HZ/10;
897 printk("calibrating APIC timer ...\n");
900 * Put whatever arbitrary (but long enough) timeout
901 * value into the APIC clock, we just want to get the
902 * counter running for calibration.
904 __setup_APIC_LVTT(1000000000);
907 * The timer chip counts down to zero. Let's wait
908 * for a wraparound to start exact measurement:
909 * (the current tick might have been already half done)
915 * We wrapped around just now. Let's start:
919 tt1 = apic_read(APIC_TMCCT);
922 * Let's wait LOOPS wraprounds:
924 for (i = 0; i < LOOPS; i++)
927 tt2 = apic_read(APIC_TMCCT);
932 * The APIC bus clock counter is 32 bits only, it
933 * might have overflown, but note that we use signed
934 * longs, thus no extra care needed.
936 * underflown to be exact, as the timer counts down ;)
939 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
942 printk("..... CPU clock speed is %ld.%04ld MHz.\n",
943 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
944 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
946 printk("..... host bus clock speed is %ld.%04ld MHz.\n",
948 result%(1000000/HZ));
953 static unsigned int calibration_result;
955 void __init setup_boot_APIC_clock(void)
957 printk("Using local APIC timer interrupts.\n");
958 using_apic_timer = 1;
962 calibration_result = calibrate_APIC_clock();
964 * Now set up the timer for real.
966 setup_APIC_timer(calibration_result);
971 void __init setup_secondary_APIC_clock(void)
973 local_irq_disable(); /* FIXME: Do we need this? --RR */
974 setup_APIC_timer(calibration_result);
978 void __init disable_APIC_timer(void)
980 if (using_apic_timer) {
983 v = apic_read(APIC_LVTT);
984 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
988 void enable_APIC_timer(void)
990 if (using_apic_timer) {
993 v = apic_read(APIC_LVTT);
994 apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
999 * the frequency of the profiling timer can be changed
1000 * by writing a multiplier value into /proc/profile.
1002 int setup_profiling_timer(unsigned int multiplier)
1007 * Sanity check. [at least 500 APIC cycles should be
1008 * between APIC interrupts as a rule of thumb, to avoid
1011 if ( (!multiplier) || (calibration_result/multiplier < 500))
1015 * Set the new multiplier for each CPU. CPUs don't start using the
1016 * new values until the next timer interrupt in which they do process
1017 * accounting. At that time they also adjust their APIC timers
1020 for (i = 0; i < NR_CPUS; ++i)
1021 per_cpu(prof_multiplier, i) = multiplier;
1029 * Local timer interrupt handler. It does both profiling and
1030 * process statistics/rescheduling.
1032 * We do profiling in every local tick, statistics/rescheduling
1033 * happen only every 'profiling multiplier' ticks. The default
1034 * multiplier is 1 and it can be changed by writing the new multiplier
1035 * value into /proc/profile.
1038 inline void smp_local_timer_interrupt(struct pt_regs * regs)
1040 int cpu = smp_processor_id();
1042 x86_do_profile(regs);
1044 if (--per_cpu(prof_counter, cpu) <= 0) {
1046 * The multiplier may have changed since the last time we got
1047 * to this point as a result of the user writing to
1048 * /proc/profile. In this case we need to adjust the APIC
1049 * timer accordingly.
1051 * Interrupts are already masked off at this point.
1053 per_cpu(prof_counter, cpu) = per_cpu(prof_multiplier, cpu);
1054 if (per_cpu(prof_counter, cpu) !=
1055 per_cpu(prof_old_multiplier, cpu)) {
1058 per_cpu(prof_counter, cpu));
1059 per_cpu(prof_old_multiplier, cpu) =
1060 per_cpu(prof_counter, cpu);
1064 update_process_times(user_mode(regs));
1069 * We take the 'long' return path, and there every subsystem
1070 * grabs the apropriate locks (kernel lock/ irq lock).
1072 * we might want to decouple profiling from the 'long path',
1073 * and do the profiling totally in assembly.
1075 * Currently this isn't too much of an issue (performance wise),
1076 * we can take more than 100K local irqs per second on a 100 MHz P5.
1081 * Local APIC timer interrupt. This is the most natural way for doing
1082 * local interrupts, but local timer interrupts can be emulated by
1083 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1085 * [ if a single-CPU system runs an SMP kernel then we call the local
1086 * interrupt as well. Thus we cannot inline the local irq ... ]
1089 void smp_apic_timer_interrupt(struct pt_regs regs)
1091 int cpu = smp_processor_id();
1094 * the NMI deadlock-detector uses this.
1096 irq_stat[cpu].apic_timer_irqs++;
1099 * NOTE! We'd better ACK the irq immediately,
1100 * because timer handling can be slow.
1104 * update_process_times() expects us to have done irq_enter().
1105 * Besides, if we don't timer interrupts ignore the global
1106 * interrupt lock, which is the WrongThing (tm) to do.
1109 smp_local_timer_interrupt(®s);
1114 * This interrupt should _never_ happen with our APIC/SMP architecture
1116 asmlinkage void smp_spurious_interrupt(void)
1122 * Check if this really is a spurious interrupt and ACK it
1123 * if it is a vectored one. Just in case...
1124 * Spurious interrupts should not be ACKed.
1126 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1127 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1130 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1131 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n",
1132 smp_processor_id());
1137 * This interrupt should never happen with our APIC/SMP architecture
1140 asmlinkage void smp_error_interrupt(void)
1142 unsigned long v, v1;
1145 /* First tickle the hardware, only then report what went on. -- REW */
1146 v = apic_read(APIC_ESR);
1147 apic_write(APIC_ESR, 0);
1148 v1 = apic_read(APIC_ESR);
1150 atomic_inc(&irq_err_count);
1152 /* Here is what the APIC error bits mean:
1155 2: Send accept error
1156 3: Receive accept error
1158 5: Send illegal vector
1159 6: Received illegal vector
1160 7: Illegal register address
1162 printk (KERN_INFO "APIC error on CPU%d: %02lx(%02lx)\n",
1163 smp_processor_id(), v , v1);
1168 * This initializes the IO-APIC and APIC hardware if this is
1171 int __init APIC_init_uniprocessor (void)
1173 if (enable_local_apic < 0)
1174 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1176 if (!smp_found_config && !cpu_has_apic)
1180 * Complain if the BIOS pretends there is one.
1182 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1183 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1184 boot_cpu_physical_apicid);
1188 verify_local_APIC();
1192 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
1196 if (nmi_watchdog == NMI_LOCAL_APIC)
1197 check_nmi_watchdog();
1198 #ifdef CONFIG_X86_IO_APIC
1199 if (smp_found_config)
1200 if (!skip_ioapic_setup && nr_ioapics)
1203 setup_boot_APIC_clock();