1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/semaphore.h>
9 #include <asm/processor.h>
13 #include <asm/mmu_context.h>
16 #ifdef CONFIG_X86_LOCAL_APIC
17 #include <asm/mpspec.h>
19 #include <mach_apic.h>
21 #include <asm/hypervisor.h>
25 DEFINE_PER_CPU(struct Xgt_desc_struct, cpu_gdt_descr);
26 EXPORT_PER_CPU_SYMBOL(cpu_gdt_descr);
29 DEFINE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]);
30 EXPORT_PER_CPU_SYMBOL(cpu_16bit_stack);
33 static int cachesize_override __cpuinitdata = -1;
34 static int disable_x86_fxsr __cpuinitdata;
35 static int disable_x86_serial_nr __cpuinitdata = 1;
36 static int disable_x86_sep __cpuinitdata;
38 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
40 extern int disable_pse;
42 static void default_init(struct cpuinfo_x86 * c)
44 /* Not much we can do here... */
45 /* Check if at least it has cpuid */
46 if (c->cpuid_level == -1) {
47 /* No cpuid. It must be an ancient CPU */
49 strcpy(c->x86_model_id, "486");
51 strcpy(c->x86_model_id, "386");
55 static struct cpu_dev default_cpu = {
56 .c_init = default_init,
57 .c_vendor = "Unknown",
59 static struct cpu_dev * this_cpu = &default_cpu;
61 static int __init cachesize_setup(char *str)
63 get_option (&str, &cachesize_override);
66 __setup("cachesize=", cachesize_setup);
68 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
73 if (cpuid_eax(0x80000000) < 0x80000004)
76 v = (unsigned int *) c->x86_model_id;
77 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
78 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
79 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
80 c->x86_model_id[48] = 0;
82 /* Intel chips right-justify this string for some dumb reason;
83 undo that brain damage */
84 p = q = &c->x86_model_id[0];
90 while ( q <= &c->x86_model_id[48] )
91 *q++ = '\0'; /* Zero-pad the rest */
98 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
100 unsigned int n, dummy, ecx, edx, l2size;
102 n = cpuid_eax(0x80000000);
104 if (n >= 0x80000005) {
105 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
106 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
107 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
108 c->x86_cache_size=(ecx>>24)+(edx>>24);
111 if (n < 0x80000006) /* Some chips just has a large L1. */
114 ecx = cpuid_ecx(0x80000006);
117 /* do processor-specific cache resizing */
118 if (this_cpu->c_size_cache)
119 l2size = this_cpu->c_size_cache(c,l2size);
121 /* Allow user to override all this if necessary. */
122 if (cachesize_override != -1)
123 l2size = cachesize_override;
126 return; /* Again, no L2 cache is possible */
128 c->x86_cache_size = l2size;
130 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
134 /* Naming convention should be: <Name> [(<Codename>)] */
135 /* This table only is used unless init_<vendor>() below doesn't set it; */
136 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
138 /* Look up CPU names by table lookup. */
139 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
141 struct cpu_model_info *info;
143 if ( c->x86_model >= 16 )
144 return NULL; /* Range check */
149 info = this_cpu->c_models;
151 while (info && info->family) {
152 if (info->family == c->x86)
153 return info->model_names[c->x86_model];
156 return NULL; /* Not found */
160 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
162 char *v = c->x86_vendor_id;
166 for (i = 0; i < X86_VENDOR_NUM; i++) {
168 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
169 (cpu_devs[i]->c_ident[1] &&
170 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
173 this_cpu = cpu_devs[i];
180 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
181 printk(KERN_ERR "CPU: Your system may be unstable.\n");
183 c->x86_vendor = X86_VENDOR_UNKNOWN;
184 this_cpu = &default_cpu;
188 static int __init x86_fxsr_setup(char * s)
190 disable_x86_fxsr = 1;
193 __setup("nofxsr", x86_fxsr_setup);
196 static int __init x86_sep_setup(char * s)
201 __setup("nosep", x86_sep_setup);
204 /* Standard macro to see if a specific flag is changeable */
205 static inline int flag_is_changeable_p(u32 flag)
219 : "=&r" (f1), "=&r" (f2)
222 return ((f1^f2) & flag) != 0;
226 /* Probe for the CPUID instruction */
227 static int __cpuinit have_cpuid_p(void)
229 return flag_is_changeable_p(X86_EFLAGS_ID);
232 /* Do minimum CPU detection early.
233 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
234 The others are not touched to avoid unwanted side effects.
236 WARNING: this function is only called on the BP. Don't add code here
237 that is supposed to run on all CPUs. */
238 static void __init early_cpu_detect(void)
240 struct cpuinfo_x86 *c = &boot_cpu_data;
242 c->x86_cache_alignment = 32;
247 /* Get vendor name */
248 cpuid(0x00000000, &c->cpuid_level,
249 (int *)&c->x86_vendor_id[0],
250 (int *)&c->x86_vendor_id[8],
251 (int *)&c->x86_vendor_id[4]);
253 get_cpu_vendor(c, 1);
256 if (c->cpuid_level >= 0x00000001) {
257 u32 junk, tfms, cap0, misc;
258 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
259 c->x86 = (tfms >> 8) & 15;
260 c->x86_model = (tfms >> 4) & 15;
262 c->x86 += (tfms >> 20) & 0xff;
264 c->x86_model += ((tfms >> 16) & 0xF) << 4;
265 c->x86_mask = tfms & 15;
267 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
271 void __cpuinit generic_identify(struct cpuinfo_x86 * c)
276 if (have_cpuid_p()) {
277 /* Get vendor name */
278 cpuid(0x00000000, &c->cpuid_level,
279 (int *)&c->x86_vendor_id[0],
280 (int *)&c->x86_vendor_id[8],
281 (int *)&c->x86_vendor_id[4]);
283 get_cpu_vendor(c, 0);
284 /* Initialize the standard set of capabilities */
285 /* Note that the vendor-specific code below might override */
287 /* Intel-defined flags: level 0x00000001 */
288 if ( c->cpuid_level >= 0x00000001 ) {
289 u32 capability, excap;
290 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
291 c->x86_capability[0] = capability;
292 c->x86_capability[4] = excap;
293 c->x86 = (tfms >> 8) & 15;
294 c->x86_model = (tfms >> 4) & 15;
296 c->x86 += (tfms >> 20) & 0xff;
298 c->x86_model += ((tfms >> 16) & 0xF) << 4;
299 c->x86_mask = tfms & 15;
301 c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
303 c->apicid = (ebx >> 24) & 0xFF;
306 /* Have CPUID level 0 only - unheard of */
310 /* AMD-defined flags: level 0x80000001 */
311 xlvl = cpuid_eax(0x80000000);
312 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
313 if ( xlvl >= 0x80000001 ) {
314 c->x86_capability[1] = cpuid_edx(0x80000001);
315 c->x86_capability[6] = cpuid_ecx(0x80000001);
317 if ( xlvl >= 0x80000004 )
318 get_model_name(c); /* Default name */
322 early_intel_workaround(c);
325 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
329 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
331 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
332 /* Disable processor serial number */
334 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
336 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
337 printk(KERN_NOTICE "CPU serial number disabled.\n");
338 clear_bit(X86_FEATURE_PN, c->x86_capability);
340 /* Disabling the serial number may affect the cpuid level */
341 c->cpuid_level = cpuid_eax(0);
345 static int __init x86_serial_nr_setup(char *s)
347 disable_x86_serial_nr = 0;
350 __setup("serialnumber", x86_serial_nr_setup);
355 * This does the hard work of actually picking apart the CPU stuff...
357 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
361 c->loops_per_jiffy = loops_per_jiffy;
362 c->x86_cache_size = -1;
363 c->x86_vendor = X86_VENDOR_UNKNOWN;
364 c->cpuid_level = -1; /* CPUID not detected */
365 c->x86_model = c->x86_mask = 0; /* So far unknown... */
366 c->x86_vendor_id[0] = '\0'; /* Unset */
367 c->x86_model_id[0] = '\0'; /* Unset */
368 c->x86_max_cores = 1;
369 memset(&c->x86_capability, 0, sizeof c->x86_capability);
371 if (!have_cpuid_p()) {
372 /* First of all, decide if this is a 486 or higher */
373 /* It's a 486 if we can modify the AC flag */
374 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
382 printk(KERN_DEBUG "CPU: After generic identify, caps:");
383 for (i = 0; i < NCAPINTS; i++)
384 printk(" %08lx", c->x86_capability[i]);
387 if (this_cpu->c_identify) {
388 this_cpu->c_identify(c);
390 printk(KERN_DEBUG "CPU: After vendor identify, caps:");
391 for (i = 0; i < NCAPINTS; i++)
392 printk(" %08lx", c->x86_capability[i]);
397 * Vendor-specific initialization. In this section we
398 * canonicalize the feature flags, meaning if there are
399 * features a certain CPU supports which CPUID doesn't
400 * tell us, CPUID claiming incorrect flags, or other bugs,
401 * we handle them here.
403 * At the end of this section, c->x86_capability better
404 * indicate the features this CPU genuinely supports!
406 if (this_cpu->c_init)
409 /* Disable the PN if appropriate */
410 squash_the_stupid_serial_number(c);
413 * The vendor-specific functions might have changed features. Now
414 * we do "generic changes."
419 clear_bit(X86_FEATURE_TSC, c->x86_capability);
422 if (disable_x86_fxsr) {
423 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
424 clear_bit(X86_FEATURE_XMM, c->x86_capability);
429 clear_bit(X86_FEATURE_SEP, c->x86_capability);
432 clear_bit(X86_FEATURE_PSE, c->x86_capability);
434 if (exec_shield != 0) {
435 #ifdef CONFIG_HIGHMEM64G /* NX implies PAE */
436 if (!test_bit(X86_FEATURE_NX, c->x86_capability))
438 clear_bit(X86_FEATURE_SEP, c->x86_capability);
441 /* If the model name is still unset, do table lookup. */
442 if ( !c->x86_model_id[0] ) {
444 p = table_lookup_model(c);
446 strcpy(c->x86_model_id, p);
449 sprintf(c->x86_model_id, "%02x/%02x",
450 c->x86, c->x86_model);
453 /* Now the feature flags better reflect actual CPU features! */
455 printk(KERN_DEBUG "CPU: After all inits, caps:");
456 for (i = 0; i < NCAPINTS; i++)
457 printk(" %08lx", c->x86_capability[i]);
461 * On SMP, boot_cpu_data holds the common feature set between
462 * all CPUs; so make sure that we indicate which features are
463 * common between the CPUs. The first time this routine gets
464 * executed, c == &boot_cpu_data.
466 if ( c != &boot_cpu_data ) {
467 /* AND the already accumulated flags with these */
468 for ( i = 0 ; i < NCAPINTS ; i++ )
469 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
472 /* Init Machine Check Exception if available. */
475 if (c == &boot_cpu_data)
479 if (c == &boot_cpu_data)
486 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
488 u32 eax, ebx, ecx, edx;
489 int index_msb, core_bits;
491 cpuid(1, &eax, &ebx, &ecx, &edx);
493 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
496 smp_num_siblings = (ebx & 0xff0000) >> 16;
498 if (smp_num_siblings == 1) {
499 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
500 } else if (smp_num_siblings > 1 ) {
502 if (smp_num_siblings > NR_CPUS) {
503 printk(KERN_WARNING "CPU: Unsupported number of the "
504 "siblings %d", smp_num_siblings);
505 smp_num_siblings = 1;
509 index_msb = get_count_order(smp_num_siblings);
510 c->phys_proc_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
512 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
515 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
517 index_msb = get_count_order(smp_num_siblings) ;
519 core_bits = get_count_order(c->x86_max_cores);
521 c->cpu_core_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &
522 ((1 << core_bits) - 1);
524 if (c->x86_max_cores > 1)
525 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
531 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
535 if (c->x86_vendor < X86_VENDOR_NUM)
536 vendor = this_cpu->c_vendor;
537 else if (c->cpuid_level >= 0)
538 vendor = c->x86_vendor_id;
540 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
541 printk("%s ", vendor);
543 if (!c->x86_model_id[0])
544 printk("%d86", c->x86);
546 printk("%s", c->x86_model_id);
548 if (c->x86_mask || c->cpuid_level >= 0)
549 printk(" stepping %02x\n", c->x86_mask);
554 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
557 * We're emulating future behavior.
558 * In the future, the cpu-specific init functions will be called implicitly
559 * via the magic of initcalls.
560 * They will insert themselves into the cpu_devs structure.
561 * Then, when cpu_init() is called, we can just iterate over that array.
564 extern int intel_cpu_init(void);
565 extern int cyrix_init_cpu(void);
566 extern int nsc_init_cpu(void);
567 extern int amd_init_cpu(void);
568 extern int centaur_init_cpu(void);
569 extern int transmeta_init_cpu(void);
570 extern int rise_init_cpu(void);
571 extern int nexgen_init_cpu(void);
572 extern int umc_init_cpu(void);
574 void __init early_cpu_init(void)
581 transmeta_init_cpu();
587 #ifdef CONFIG_DEBUG_PAGEALLOC
588 /* pse is not compatible with on-the-fly unmapping,
589 * disable it even if the cpus claim to support it.
591 clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
596 void __cpuinit cpu_gdt_init(struct Xgt_desc_struct *gdt_descr)
598 unsigned long frames[16];
602 for (va = gdt_descr->address, f = 0;
603 va < gdt_descr->address + gdt_descr->size;
604 va += PAGE_SIZE, f++) {
605 frames[f] = virt_to_mfn(va);
606 make_lowmem_page_readonly(
607 (void *)va, XENFEAT_writable_descriptor_tables);
609 if (HYPERVISOR_set_gdt(frames, gdt_descr->size / 8))
614 * cpu_init() initializes state that is per-CPU. Some data is already
615 * initialized (naturally) in the bootstrap process, such as the GDT
616 * and IDT. We reload them nevertheless, this function acts as a
617 * 'CPU state barrier', nothing should get across.
619 void __cpuinit cpu_init(void)
621 int cpu = smp_processor_id();
622 #ifndef CONFIG_X86_NO_TSS
623 struct tss_struct * t = &per_cpu(init_tss, cpu);
625 struct thread_struct *thread = ¤t->thread;
626 struct desc_struct *gdt;
627 struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu);
629 if (cpu_test_and_set(cpu, cpu_initialized)) {
630 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
631 for (;;) local_irq_enable();
633 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
635 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
636 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
637 if (tsc_disable && cpu_has_tsc) {
638 printk(KERN_NOTICE "Disabling TSC...\n");
639 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
640 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
641 set_in_cr4(X86_CR4_TSD);
645 /* The CPU hotplug case */
646 if (cpu_gdt_descr->address) {
647 gdt = (struct desc_struct *)cpu_gdt_descr->address;
648 memset(gdt, 0, PAGE_SIZE);
652 * This is a horrible hack to allocate the GDT. The problem
653 * is that cpu_init() is called really early for the boot CPU
654 * (and hence needs bootmem) but much later for the secondary
655 * CPUs, when bootmem will have gone away
657 if (NODE_DATA(0)->bdata->node_bootmem_map) {
658 gdt = (struct desc_struct *)alloc_bootmem_pages(PAGE_SIZE);
659 /* alloc_bootmem_pages panics on failure, so no check */
660 memset(gdt, 0, PAGE_SIZE);
662 gdt = (struct desc_struct *)get_zeroed_page(GFP_KERNEL);
663 if (unlikely(!gdt)) {
664 printk(KERN_CRIT "CPU%d failed to allocate GDT\n", cpu);
671 * Initialize the per-CPU GDT with the boot GDT,
672 * and set up the GDT descriptor:
674 memcpy(gdt, cpu_gdt_table, GDT_SIZE);
676 /* Set up GDT entry for 16bit stack */
677 *(__u64 *)(&gdt[GDT_ENTRY_ESPFIX_SS]) |=
678 ((((__u64)stk16_off) << 16) & 0x000000ffffff0000ULL) |
679 ((((__u64)stk16_off) << 32) & 0xff00000000000000ULL) |
680 (CPU_16BIT_STACK_SIZE - 1);
682 cpu_gdt_descr->size = GDT_SIZE - 1;
683 cpu_gdt_descr->address = (unsigned long)gdt;
685 if (cpu == 0 && cpu_gdt_descr->address == 0) {
686 gdt = (struct desc_struct *)alloc_bootmem_pages(PAGE_SIZE);
687 /* alloc_bootmem_pages panics on failure, so no check */
688 memset(gdt, 0, PAGE_SIZE);
690 memcpy(gdt, cpu_gdt_table, GDT_SIZE);
692 cpu_gdt_descr->size = GDT_SIZE;
693 cpu_gdt_descr->address = (unsigned long)gdt;
697 cpu_gdt_init(cpu_gdt_descr);
700 * Set up and load the per-CPU TSS and LDT
702 atomic_inc(&init_mm.mm_count);
703 current->active_mm = &init_mm;
706 enter_lazy_tlb(&init_mm, current);
708 load_esp0(t, thread);
710 load_LDT(&init_mm.context);
712 #ifdef CONFIG_DOUBLEFAULT
713 /* Set up doublefault TSS pointer in the GDT */
714 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
717 /* Clear %fs and %gs. */
718 asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
720 /* Clear all 6 debug registers: */
729 * Force FPU initialization:
731 current_thread_info()->status = 0;
733 mxcsr_feature_mask_init();
736 #ifdef CONFIG_HOTPLUG_CPU
737 void __cpuinit cpu_uninit(void)
739 int cpu = raw_smp_processor_id();
740 cpu_clear(cpu, cpu_initialized);
743 per_cpu(cpu_tlbstate, cpu).state = 0;
744 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;