2 * (c) 2003, 2004 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
8 struct powernow_k8_data {
11 u32 numps; /* number of p-states */
12 u32 batps; /* number of p-states supported on battery */
14 /* these values are constant when the PSB is used to determine
15 * vid/fid pairings, but are modified during the ->target() call
16 * when ACPI is used */
17 u32 rvo; /* ramp voltage offset */
18 u32 irt; /* isochronous relief time */
19 u32 vidmvs; /* usable value calculated from mvs */
20 u32 vstable; /* voltage stabilization time, units 20 us */
21 u32 plllock; /* pll lock time, units 1 us */
23 /* keep track of the current fid / vid */
27 /* the powernow_table includes all frequency and vid/fid pairings:
28 * fid are the lower 8 bits of the index, vid are the upper 8 bits.
29 * frequency is in kHz */
30 struct cpufreq_frequency_table *powernow_table;
32 #ifdef CONFIG_X86_POWERNOW_K8_ACPI
33 /* the acpi table needs to be kept. it's only available if ACPI was
34 * used to determine valid frequency/vid/fid states */
35 struct acpi_processor_performance acpi_data;
40 /* processor's cpuid instruction support */
41 #define CPUID_PROCESSOR_SIGNATURE 1 /* function 1 */
42 #define CPUID_XFAM 0x0ff00000 /* extended family */
43 #define CPUID_XFAM_K8 0
44 #define CPUID_XMOD 0x000f0000 /* extended model */
45 #define CPUID_XMOD_REV_E 0x00020000
46 #define CPUID_USE_XFAM_XMOD 0x00000f00
47 #define CPUID_GET_MAX_CAPABILITIES 0x80000000
48 #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
49 #define P_STATE_TRANSITION_CAPABLE 6
51 /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */
52 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
53 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
54 /* the register number is placed in ecx, and the data is returned in edx:eax. */
56 #define MSR_FIDVID_CTL 0xc0010041
57 #define MSR_FIDVID_STATUS 0xc0010042
59 /* Field definitions within the FID VID Low Control MSR : */
60 #define MSR_C_LO_INIT_FID_VID 0x00010000
61 #define MSR_C_LO_NEW_VID 0x00001f00
62 #define MSR_C_LO_NEW_FID 0x0000002f
63 #define MSR_C_LO_VID_SHIFT 8
65 /* Field definitions within the FID VID High Control MSR : */
66 #define MSR_C_HI_STP_GNT_TO 0x000fffff
68 /* Field definitions within the FID VID Low Status MSR : */
69 #define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */
70 #define MSR_S_LO_MAX_RAMP_VID 0x1f000000
71 #define MSR_S_LO_MAX_FID 0x003f0000
72 #define MSR_S_LO_START_FID 0x00003f00
73 #define MSR_S_LO_CURRENT_FID 0x0000003f
75 /* Field definitions within the FID VID High Status MSR : */
76 #define MSR_S_HI_MAX_WORKING_VID 0x001f0000
77 #define MSR_S_HI_START_VID 0x00001f00
78 #define MSR_S_HI_CURRENT_VID 0x0000001f
79 #define MSR_C_HI_STP_GNT_BENIGN 0x00000001
82 * There are restrictions frequencies have to follow:
83 * - only 1 entry in the low fid table ( <=1.4GHz )
84 * - lowest entry in the high fid table must be >= 2 * the entry in the
86 * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry
87 * in the low fid table
88 * - the parts can only step at 200 MHz intervals, so 1.9 GHz is never valid
89 * - lowest frequency must be >= interprocessor hypertransport link speed
90 * (only applies to MP systems obviously)
93 /* fids (frequency identifiers) are arranged in 2 tables - lo and hi */
94 #define LO_FID_TABLE_TOP 6 /* fid values marking the boundary */
95 #define HI_FID_TABLE_BOTTOM 8 /* between the low and high tables */
97 #define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */
98 #define HI_VCOFREQ_TABLE_BOTTOM 1600
100 #define MIN_FREQ_RESOLUTION 200 /* fids jump by 2 matching freq jumps by 200 */
102 #define MAX_FID 0x2a /* Spec only gives FID values as far as 5 GHz */
103 #define LEAST_VID 0x1e /* Lowest (numerically highest) useful vid value */
105 #define MIN_FREQ 800 /* Min and max freqs, per spec */
106 #define MAX_FREQ 5000
108 #define INVALID_FID_MASK 0xffffffc1 /* not a valid fid if these bits are set */
109 #define INVALID_VID_MASK 0xffffffe0 /* not a valid vid if these bits are set */
111 #define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */
113 #define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */
115 #define MAXIMUM_VID_STEPS 1 /* Current cpus only allow a single step of 25mV */
116 #define VST_UNITS_20US 20 /* Voltage Stabalization Time is in units of 20us */
119 * Most values of interest are enocoded in a single field of the _PSS
120 * entries: the "control" value.
125 #define PLL_L_SHIFT 20
131 #define PLL_L_MASK 0x7f
133 #define VST_MASK 0x7f
134 #define VID_MASK 0x1f
135 #define FID_MASK 0x3f
139 * Version 1.4 of the PSB table. This table is constructed by BIOS and is
140 * to tell the OS's power management driver which VIDs and FIDs are
141 * supported by this particular processor.
142 * If the data in the PSB / PST is wrong, then this driver will program the
143 * wrong values into hardware, which is very likely to lead to a crash.
146 #define PSB_ID_STRING "AMDK7PNOW!"
147 #define PSB_ID_STRING_LEN 10
149 #define PSB_VERSION_1_4 0x14
155 u16 voltagestabilizationtime;
165 /* Pairs of fid/vid values are appended to the version 1.4 PSB table. */
171 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "powernow-k8", msg)
173 static int core_voltage_pre_transition(struct powernow_k8_data *data, u32 reqvid);
174 static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid);
175 static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid);
177 static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index);