2 * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
3 * M (part of the Centrino chipset).
5 * Despite the "SpeedStep" in the name, this is almost entirely unlike
6 * traditional SpeedStep.
8 * Modelled on speedstep.c
10 * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
12 * WARNING WARNING WARNING
14 * This driver manipulates the PERF_CTL MSR, which is only somewhat
15 * documented. While it seems to work on my laptop, it has not been
16 * tested anywhere else, and it may not work for you, do strange
17 * things or simply crash.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/cpufreq.h>
24 #include <linux/config.h>
26 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
27 #include <linux/acpi.h>
28 #include <acpi/processor.h>
32 #include <asm/processor.h>
33 #include <asm/cpufeature.h>
35 #define PFX "speedstep-centrino: "
36 #define MAINTAINER "Jeremy Fitzhardinge <jeremy@goop.org>"
38 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
43 __u8 x86; /* CPU family */
44 __u8 x86_model; /* model */
45 __u8 x86_mask; /* stepping */
55 static const struct cpu_id cpu_ids[] = {
56 [CPU_BANIAS] = { 6, 9, 5 },
57 [CPU_DOTHAN_A1] = { 6, 13, 1 },
58 [CPU_DOTHAN_A2] = { 6, 13, 2 },
59 [CPU_DOTHAN_B0] = { 6, 13, 6 },
61 #define N_IDS (sizeof(cpu_ids)/sizeof(cpu_ids[0]))
65 const struct cpu_id *cpu_id;
66 const char *model_name;
67 unsigned max_freq; /* max clock in kHz */
69 struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
71 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x);
73 /* Operating points for current CPU */
74 static struct cpu_model *centrino_model;
75 static const struct cpu_id *centrino_cpu;
77 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
79 /* Computes the correct form for IA32_PERF_CTL MSR for a particular
80 frequency/voltage operating point; frequency in MHz, volts in mV.
81 This is stored as "index" in the structure. */
84 .frequency = (mhz) * 1000, \
85 .index = (((mhz)/100) << 8) | ((mv - 700) / 16) \
89 * These voltage tables were derived from the Intel Pentium M
90 * datasheet, document 25261202.pdf, Table 5. I have verified they
91 * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
95 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
96 static struct cpufreq_frequency_table banias_900[] =
101 { .frequency = CPUFREQ_TABLE_END }
104 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
105 static struct cpufreq_frequency_table banias_1000[] =
111 { .frequency = CPUFREQ_TABLE_END }
114 /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
115 static struct cpufreq_frequency_table banias_1100[] =
122 { .frequency = CPUFREQ_TABLE_END }
126 /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
127 static struct cpufreq_frequency_table banias_1200[] =
135 { .frequency = CPUFREQ_TABLE_END }
138 /* Intel Pentium M processor 1.30GHz (Banias) */
139 static struct cpufreq_frequency_table banias_1300[] =
146 { .frequency = CPUFREQ_TABLE_END }
149 /* Intel Pentium M processor 1.40GHz (Banias) */
150 static struct cpufreq_frequency_table banias_1400[] =
157 { .frequency = CPUFREQ_TABLE_END }
160 /* Intel Pentium M processor 1.50GHz (Banias) */
161 static struct cpufreq_frequency_table banias_1500[] =
169 { .frequency = CPUFREQ_TABLE_END }
172 /* Intel Pentium M processor 1.60GHz (Banias) */
173 static struct cpufreq_frequency_table banias_1600[] =
181 { .frequency = CPUFREQ_TABLE_END }
184 /* Intel Pentium M processor 1.70GHz (Banias) */
185 static struct cpufreq_frequency_table banias_1700[] =
193 { .frequency = CPUFREQ_TABLE_END }
197 #define _BANIAS(cpuid, max, name) \
199 .model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
200 .max_freq = (max)*1000, \
201 .op_points = banias_##max, \
203 #define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
205 /* CPU models, their operating frequency range, and freq/voltage
207 static struct cpu_model models[] =
209 _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
219 /* NULL model_name is a wildcard */
220 { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
221 { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
222 { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
229 static int centrino_cpu_init_table(struct cpufreq_policy *policy)
231 struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
232 struct cpu_model *model;
234 for(model = models; model->cpu_id != NULL; model++)
235 if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
236 (model->model_name == NULL ||
237 strcmp(cpu->x86_model_id, model->model_name) == 0))
240 if (model->cpu_id == NULL) {
241 /* No match at all */
242 printk(KERN_INFO PFX "no support for CPU model \"%s\": "
243 "send /proc/cpuinfo to " MAINTAINER "\n",
248 if (model->op_points == NULL) {
249 /* Matched a non-match */
250 printk(KERN_INFO PFX "no table support for CPU model \"%s\": \n",
252 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
253 printk(KERN_INFO PFX "try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n");
258 centrino_model = model;
260 dprintk("found \"%s\": max frequency: %dkHz\n",
261 model->model_name, model->max_freq);
267 static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; }
268 #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
270 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x)
272 if ((c->x86 == x->x86) &&
273 (c->x86_model == x->x86_model) &&
274 (c->x86_mask == x->x86_mask))
279 /* To be called only after centrino_model is initialized */
280 static unsigned extract_clock(unsigned msr)
285 * Extract clock in kHz from PERF_CTL value
286 * for centrino, as some DSDTs are buggy.
287 * Ideally, this can be done using the acpi_data structure.
289 if ((centrino_cpu == &cpu_ids[CPU_BANIAS]) ||
290 (centrino_cpu == &cpu_ids[CPU_DOTHAN_A1]) ||
291 (centrino_cpu == &cpu_ids[CPU_DOTHAN_B0])) {
292 msr = (msr >> 8) & 0xff;
296 if ((!centrino_model) || (!centrino_model->op_points))
300 for (i=0;centrino_model->op_points[i].frequency != CPUFREQ_TABLE_END; i++) {
301 if (msr == centrino_model->op_points[i].index)
302 return centrino_model->op_points[i].frequency;
307 /* Return the current CPU frequency in kHz */
308 static unsigned int get_cur_freq(unsigned int cpu)
311 cpumask_t saved_mask;
313 saved_mask = current->cpus_allowed;
314 set_cpus_allowed(current, cpumask_of_cpu(cpu));
315 if (smp_processor_id() != cpu)
318 rdmsr(MSR_IA32_PERF_STATUS, l, h);
319 set_cpus_allowed(current, saved_mask);
320 return extract_clock(l);
324 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
326 static struct acpi_processor_performance p;
329 * centrino_cpu_init_acpi - register with ACPI P-States library
331 * Register with the ACPI P-States library (part of drivers/acpi/processor.c)
332 * in order to determine correct frequency and voltage pairings by reading
333 * the _PSS of the ACPI DSDT or SSDT tables.
335 static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
337 union acpi_object arg0 = {ACPI_TYPE_BUFFER};
339 struct acpi_object_list arg_list = {1, &arg0};
340 unsigned long cur_freq;
344 arg0.buffer.length = 12;
345 arg0.buffer.pointer = (u8 *) arg0_buf;
346 arg0_buf[0] = ACPI_PDC_REVISION_ID;
348 arg0_buf[2] = ACPI_PDC_EST_CAPABILITY_SMP | ACPI_PDC_EST_CAPABILITY_MSR;
352 /* register with ACPI core */
353 if (acpi_processor_register_performance(&p, policy->cpu)) {
354 printk(KERN_INFO PFX "obtaining ACPI data failed\n");
358 /* verify the acpi_data */
359 if (p.state_count <= 1) {
360 dprintk("No P-States\n");
365 if ((p.control_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) ||
366 (p.status_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) {
367 dprintk("Invalid control/status registers (%x - %x)\n",
368 p.control_register.space_id, p.status_register.space_id);
373 for (i=0; i<p.state_count; i++) {
374 if (p.states[i].control != p.states[i].status) {
375 dprintk("Different control (%x) and status values (%x)\n",
376 p.states[i].control, p.states[i].status);
381 if (!p.states[i].core_frequency) {
382 dprintk("Zero core frequency for state %u\n", i);
387 if (p.states[i].core_frequency > p.states[0].core_frequency) {
388 dprintk("P%u has larger frequency (%u) than P0 (%u), skipping\n", i,
389 p.states[i].core_frequency, p.states[0].core_frequency);
390 p.states[i].core_frequency = 0;
395 centrino_model = kmalloc(sizeof(struct cpu_model), GFP_KERNEL);
396 if (!centrino_model) {
400 memset(centrino_model, 0, sizeof(struct cpu_model));
402 centrino_model->model_name=NULL;
403 centrino_model->max_freq = p.states[0].core_frequency * 1000;
404 centrino_model->op_points = kmalloc(sizeof(struct cpufreq_frequency_table) *
405 (p.state_count + 1), GFP_KERNEL);
406 if (!centrino_model->op_points) {
411 for (i=0; i<p.state_count; i++) {
412 centrino_model->op_points[i].index = p.states[i].control;
413 centrino_model->op_points[i].frequency = p.states[i].core_frequency * 1000;
414 dprintk("adding state %i with frequency %u and control value %04x\n",
415 i, centrino_model->op_points[i].frequency, centrino_model->op_points[i].index);
417 centrino_model->op_points[p.state_count].frequency = CPUFREQ_TABLE_END;
419 cur_freq = get_cur_freq(policy->cpu);
421 for (i=0; i<p.state_count; i++) {
422 if (!p.states[i].core_frequency) {
423 dprintk("skipping state %u\n", i);
424 centrino_model->op_points[i].frequency = CPUFREQ_ENTRY_INVALID;
428 if (extract_clock(centrino_model->op_points[i].index) !=
429 (centrino_model->op_points[i].frequency)) {
430 dprintk("Invalid encoded frequency (%u vs. %u)\n",
431 extract_clock(centrino_model->op_points[i].index),
432 centrino_model->op_points[i].frequency);
437 if (cur_freq == centrino_model->op_points[i].frequency)
441 /* notify BIOS that we exist */
442 acpi_processor_notify_smm(THIS_MODULE);
447 kfree(centrino_model->op_points);
449 kfree(centrino_model);
451 acpi_processor_unregister_performance(&p, policy->cpu);
452 printk(KERN_INFO PFX "invalid ACPI data\n");
456 static inline int centrino_cpu_init_acpi(struct cpufreq_policy *policy) { return -ENODEV; }
459 static int centrino_cpu_init(struct cpufreq_policy *policy)
461 struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
467 /* Only Intel makes Enhanced Speedstep-capable CPUs */
468 if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST))
471 for (i = 0; i < N_IDS; i++)
472 if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
476 centrino_cpu = &cpu_ids[i];
478 if (centrino_cpu_init_acpi(policy)) {
479 if (policy->cpu != 0)
483 printk(KERN_INFO PFX "found unsupported CPU with "
484 "Enhanced SpeedStep: send /proc/cpuinfo to "
489 if (centrino_cpu_init_table(policy)) {
494 /* Check to see if Enhanced SpeedStep is enabled, and try to
496 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
498 if (!(l & (1<<16))) {
500 dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
501 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
503 /* check to see if it stuck */
504 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
505 if (!(l & (1<<16))) {
506 printk(KERN_INFO PFX "couldn't enable Enhanced SpeedStep\n");
511 freq = get_cur_freq(policy->cpu);
513 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
514 policy->cpuinfo.transition_latency = 10000; /* 10uS transition latency */
517 dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);
519 ret = cpufreq_frequency_table_cpuinfo(policy, centrino_model->op_points);
523 cpufreq_frequency_table_get_attr(centrino_model->op_points, policy->cpu);
528 static int centrino_cpu_exit(struct cpufreq_policy *policy)
533 cpufreq_frequency_table_put_attr(policy->cpu);
535 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
536 if (!centrino_model->model_name) {
537 dprintk("unregistering and freeing ACPI data\n");
538 acpi_processor_unregister_performance(&p, policy->cpu);
539 kfree(centrino_model->op_points);
540 kfree(centrino_model);
544 centrino_model = NULL;
550 * centrino_verify - verifies a new CPUFreq policy
551 * @policy: new policy
553 * Limit must be within this model's frequency range at least one
556 static int centrino_verify (struct cpufreq_policy *policy)
558 return cpufreq_frequency_table_verify(policy, centrino_model->op_points);
562 * centrino_setpolicy - set a new CPUFreq policy
563 * @policy: new policy
564 * @target_freq: the target frequency
565 * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
567 * Sets a new CPUFreq policy.
569 static int centrino_target (struct cpufreq_policy *policy,
570 unsigned int target_freq,
571 unsigned int relation)
573 unsigned int newstate = 0;
574 unsigned int msr, oldmsr, h;
575 struct cpufreq_freqs freqs;
576 cpumask_t saved_mask;
579 if (centrino_model == NULL)
583 * Support for SMP systems.
584 * Make sure we are running on the CPU that wants to change frequency
586 saved_mask = current->cpus_allowed;
587 set_cpus_allowed(current, policy->cpus);
588 if (smp_processor_id() != policy->cpu) {
589 dprintk("couldn't limit to CPUs in this domain\n");
593 if (cpufreq_frequency_table_target(policy, centrino_model->op_points, target_freq,
594 relation, &newstate)) {
599 msr = centrino_model->op_points[newstate].index;
600 rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
602 if (msr == (oldmsr & 0xffff)) {
604 dprintk("no change needed - msr was and needs to be %x\n", oldmsr);
608 freqs.cpu = policy->cpu;
609 freqs.old = extract_clock(oldmsr);
610 freqs.new = extract_clock(msr);
612 dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
613 target_freq, freqs.old, freqs.new, msr);
615 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
617 /* all but 16 LSB are "reserved", so treat them with
623 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
625 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
629 set_cpus_allowed(current, saved_mask);
633 static struct freq_attr* centrino_attr[] = {
634 &cpufreq_freq_attr_scaling_available_freqs,
638 static struct cpufreq_driver centrino_driver = {
639 .name = "centrino", /* should be speedstep-centrino,
640 but there's a 16 char limit */
641 .init = centrino_cpu_init,
642 .exit = centrino_cpu_exit,
643 .verify = centrino_verify,
644 .target = centrino_target,
646 .attr = centrino_attr,
647 .owner = THIS_MODULE,
652 * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
654 * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
655 * unsupported devices, -ENOENT if there's no voltage table for this
656 * particular CPU model, -EINVAL on problems during initiatization,
657 * and zero on success.
659 * This is quite picky. Not only does the CPU have to advertise the
660 * "est" flag in the cpuid capability flags, we look for a specific
661 * CPU model and stepping, and we need to have the exact model name in
662 * our voltage tables. That is, be paranoid about not releasing
663 * someone's valuable magic smoke.
665 static int __init centrino_init(void)
667 struct cpuinfo_x86 *cpu = cpu_data;
669 if (!cpu_has(cpu, X86_FEATURE_EST))
672 return cpufreq_register_driver(¢rino_driver);
675 static void __exit centrino_exit(void)
677 cpufreq_unregister_driver(¢rino_driver);
680 MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
681 MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
682 MODULE_LICENSE ("GPL");
684 late_initcall(centrino_init);
685 module_exit(centrino_exit);