2 * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
3 * M (part of the Centrino chipset).
5 * Despite the "SpeedStep" in the name, this is almost entirely unlike
6 * traditional SpeedStep.
8 * Modelled on speedstep.c
10 * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
12 * WARNING WARNING WARNING
14 * This driver manipulates the PERF_CTL MSR, which is only somewhat
15 * documented. While it seems to work on my laptop, it has not been
16 * tested anywhere else, and it may not work for you, do strange
17 * things or simply crash.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/cpufreq.h>
24 #include <linux/config.h>
26 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
27 #include <linux/acpi.h>
28 #include <acpi/processor.h>
32 #include <asm/processor.h>
33 #include <asm/cpufeature.h>
35 #define PFX "speedstep-centrino: "
36 #define MAINTAINER "Jeremy Fitzhardinge <jeremy@goop.org>"
38 /*#define CENTRINO_DEBUG*/
41 #define dprintk(msg...) printk(msg)
43 #define dprintk(msg...) do { } while(0)
48 __u8 x86; /* CPU family */
49 __u8 x86_model; /* model */
50 __u8 x86_mask; /* stepping */
60 static const struct cpu_id cpu_ids[] = {
61 [CPU_BANIAS] = { 6, 9, 5 },
62 [CPU_DOTHAN_A1] = { 6, 13, 1 },
63 [CPU_DOTHAN_A2] = { 6, 13, 2 },
64 [CPU_DOTHAN_B0] = { 6, 13, 6 },
66 #define N_IDS (sizeof(cpu_ids)/sizeof(cpu_ids[0]))
70 const struct cpu_id *cpu_id;
71 const char *model_name;
72 unsigned max_freq; /* max clock in kHz */
74 struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
76 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x);
78 /* Operating points for current CPU */
79 static struct cpu_model *centrino_model;
80 static int centrino_cpu;
82 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
84 /* Computes the correct form for IA32_PERF_CTL MSR for a particular
85 frequency/voltage operating point; frequency in MHz, volts in mV.
86 This is stored as "index" in the structure. */
89 .frequency = (mhz) * 1000, \
90 .index = (((mhz)/100) << 8) | ((mv - 700) / 16) \
94 * These voltage tables were derived from the Intel Pentium M
95 * datasheet, document 25261202.pdf, Table 5. I have verified they
96 * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
100 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
101 static struct cpufreq_frequency_table banias_900[] =
106 { .frequency = CPUFREQ_TABLE_END }
109 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
110 static struct cpufreq_frequency_table banias_1000[] =
116 { .frequency = CPUFREQ_TABLE_END }
119 /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
120 static struct cpufreq_frequency_table banias_1100[] =
127 { .frequency = CPUFREQ_TABLE_END }
131 /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
132 static struct cpufreq_frequency_table banias_1200[] =
140 { .frequency = CPUFREQ_TABLE_END }
143 /* Intel Pentium M processor 1.30GHz (Banias) */
144 static struct cpufreq_frequency_table banias_1300[] =
151 { .frequency = CPUFREQ_TABLE_END }
154 /* Intel Pentium M processor 1.40GHz (Banias) */
155 static struct cpufreq_frequency_table banias_1400[] =
162 { .frequency = CPUFREQ_TABLE_END }
165 /* Intel Pentium M processor 1.50GHz (Banias) */
166 static struct cpufreq_frequency_table banias_1500[] =
174 { .frequency = CPUFREQ_TABLE_END }
177 /* Intel Pentium M processor 1.60GHz (Banias) */
178 static struct cpufreq_frequency_table banias_1600[] =
186 { .frequency = CPUFREQ_TABLE_END }
189 /* Intel Pentium M processor 1.70GHz (Banias) */
190 static struct cpufreq_frequency_table banias_1700[] =
198 { .frequency = CPUFREQ_TABLE_END }
202 #define _BANIAS(cpuid, max, name) \
204 .model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
205 .max_freq = (max)*1000, \
206 .op_points = banias_##max, \
208 #define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
210 /* CPU models, their operating frequency range, and freq/voltage
212 static struct cpu_model models[] =
214 _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
224 /* NULL model_name is a wildcard */
225 { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
226 { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
227 { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
234 static int centrino_cpu_init_table(struct cpufreq_policy *policy)
236 struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
237 struct cpu_model *model;
239 for(model = models; model->cpu_id != NULL; model++)
240 if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
241 (model->model_name == NULL ||
242 strcmp(cpu->x86_model_id, model->model_name) == 0))
245 if (model->cpu_id == NULL) {
246 /* No match at all */
247 printk(KERN_INFO PFX "no support for CPU model \"%s\": "
248 "send /proc/cpuinfo to " MAINTAINER "\n",
253 if (model->op_points == NULL) {
254 /* Matched a non-match */
255 printk(KERN_INFO PFX "no table support for CPU model \"%s\": \n",
257 printk(KERN_INFO PFX "try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n");
261 centrino_model = model;
263 printk(KERN_INFO PFX "found \"%s\": max frequency: %dkHz\n",
264 model->model_name, model->max_freq);
270 static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; }
271 #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
273 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x)
275 if ((c->x86 == x->x86) &&
276 (c->x86_model == x->x86_model) &&
277 (c->x86_mask == x->x86_mask))
282 /* To be called only after centrino_model is initialized */
283 static unsigned extract_clock(unsigned msr)
288 * Extract clock in kHz from PERF_CTL value
289 * for centrino, as some DSDTs are buggy.
290 * Ideally, this can be done using the acpi_data structure.
293 msr = (msr >> 8) & 0xff;
297 if ((!centrino_model) || (!centrino_model->op_points))
301 for (i=0;centrino_model->op_points[i].frequency != CPUFREQ_TABLE_END; i++) {
302 if (msr == centrino_model->op_points[i].index)
303 return centrino_model->op_points[i].frequency;
308 /* Return the current CPU frequency in kHz */
309 static unsigned int get_cur_freq(unsigned int cpu)
312 cpumask_t saved_mask;
314 saved_mask = current->cpus_allowed;
315 set_cpus_allowed(current, cpumask_of_cpu(cpu));
316 if (smp_processor_id() != cpu)
319 rdmsr(MSR_IA32_PERF_STATUS, l, h);
320 set_cpus_allowed(current, saved_mask);
321 return extract_clock(l);
325 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
327 static struct acpi_processor_performance p;
330 * centrino_cpu_init_acpi - register with ACPI P-States library
332 * Register with the ACPI P-States library (part of drivers/acpi/processor.c)
333 * in order to determine correct frequency and voltage pairings by reading
334 * the _PSS of the ACPI DSDT or SSDT tables.
336 static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
338 union acpi_object arg0 = {ACPI_TYPE_BUFFER};
340 struct acpi_object_list arg_list = {1, &arg0};
341 unsigned long cur_freq;
345 arg0.buffer.length = 12;
346 arg0.buffer.pointer = (u8 *) arg0_buf;
347 arg0_buf[0] = ACPI_PDC_REVISION_ID;
349 arg0_buf[2] = ACPI_PDC_EST_CAPABILITY_SMP | ACPI_PDC_EST_CAPABILITY_MSR;
353 /* register with ACPI core */
354 if (acpi_processor_register_performance(&p, policy->cpu))
357 /* verify the acpi_data */
358 if (p.state_count <= 1) {
359 printk(KERN_DEBUG "No P-States\n");
364 if ((p.control_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) ||
365 (p.status_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) {
366 printk(KERN_DEBUG "Invalid control/status registers\n");
371 for (i=0; i<p.state_count; i++) {
372 if (p.states[i].control != p.states[i].status) {
373 printk(KERN_DEBUG "Different control and status values\n");
378 if (!p.states[i].core_frequency) {
379 printk(KERN_DEBUG "Zero core frequency\n");
384 if (p.states[i].core_frequency > p.states[0].core_frequency) {
385 printk(KERN_DEBUG "P%u has larger frequency than P0, skipping\n", i);
386 p.states[i].core_frequency = 0;
391 centrino_model = kmalloc(sizeof(struct cpu_model), GFP_KERNEL);
392 if (!centrino_model) {
396 memset(centrino_model, 0, sizeof(struct cpu_model));
398 centrino_model->model_name=NULL;
399 centrino_model->max_freq = p.states[0].core_frequency * 1000;
400 centrino_model->op_points = kmalloc(sizeof(struct cpufreq_frequency_table) *
401 (p.state_count + 1), GFP_KERNEL);
402 if (!centrino_model->op_points) {
407 for (i=0; i<p.state_count; i++) {
408 centrino_model->op_points[i].index = p.states[i].control;
409 centrino_model->op_points[i].frequency = p.states[i].core_frequency * 1000;
411 centrino_model->op_points[p.state_count].frequency = CPUFREQ_TABLE_END;
413 cur_freq = get_cur_freq(policy->cpu);
415 for (i=0; i<p.state_count; i++) {
416 if (extract_clock(centrino_model->op_points[i].index) !=
417 (centrino_model->op_points[i].frequency)) {
418 printk(KERN_DEBUG "Invalid encoded frequency\n");
423 if (cur_freq == centrino_model->op_points[i].frequency)
425 if (!p.states[i].core_frequency)
426 centrino_model->op_points[i].frequency = CPUFREQ_ENTRY_INVALID;
432 kfree(centrino_model->op_points);
434 kfree(centrino_model);
436 acpi_processor_unregister_performance(&p, policy->cpu);
440 static inline int centrino_cpu_init_acpi(struct cpufreq_policy *policy) { return -ENODEV; }
443 static int centrino_cpu_init(struct cpufreq_policy *policy)
445 struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
451 /* Only Intel makes Enhanced Speedstep-capable CPUs */
452 if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST))
455 for (i = 0; i < N_IDS; i++)
456 if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
462 if (centrino_cpu_init_acpi(policy)) {
463 if (policy->cpu != 0)
467 printk(KERN_INFO PFX "found unsupported CPU with "
468 "Enhanced SpeedStep: send /proc/cpuinfo to "
473 if (centrino_cpu_init_table(policy)) {
478 /* Check to see if Enhanced SpeedStep is enabled, and try to
480 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
482 if (!(l & (1<<16))) {
484 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
486 /* check to see if it stuck */
487 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
488 if (!(l & (1<<16))) {
489 printk(KERN_INFO PFX "couldn't enable Enhanced SpeedStep\n");
494 freq = get_cur_freq(policy->cpu);
496 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
497 policy->cpuinfo.transition_latency = 10000; /* 10uS transition latency */
500 dprintk(KERN_INFO PFX "centrino_cpu_init: policy=%d cur=%dkHz\n",
501 policy->policy, policy->cur);
503 ret = cpufreq_frequency_table_cpuinfo(policy, centrino_model->op_points);
507 cpufreq_frequency_table_get_attr(centrino_model->op_points, policy->cpu);
512 static int centrino_cpu_exit(struct cpufreq_policy *policy)
517 cpufreq_frequency_table_put_attr(policy->cpu);
519 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
520 if (!centrino_model->model_name) {
521 acpi_processor_unregister_performance(&p, policy->cpu);
522 kfree(centrino_model->op_points);
523 kfree(centrino_model);
527 centrino_model = NULL;
533 * centrino_verify - verifies a new CPUFreq policy
534 * @policy: new policy
536 * Limit must be within this model's frequency range at least one
539 static int centrino_verify (struct cpufreq_policy *policy)
541 return cpufreq_frequency_table_verify(policy, centrino_model->op_points);
545 * centrino_setpolicy - set a new CPUFreq policy
546 * @policy: new policy
547 * @target_freq: the target frequency
548 * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
550 * Sets a new CPUFreq policy.
552 static int centrino_target (struct cpufreq_policy *policy,
553 unsigned int target_freq,
554 unsigned int relation)
556 unsigned int newstate = 0;
557 unsigned int msr, oldmsr, h;
558 struct cpufreq_freqs freqs;
559 cpumask_t saved_mask;
562 if (centrino_model == NULL)
566 * Support for SMP systems.
567 * Make sure we are running on the CPU that wants to change frequency
569 saved_mask = current->cpus_allowed;
570 set_cpus_allowed(current, cpumask_of_cpu(policy->cpu));
571 if (smp_processor_id() != policy->cpu) {
575 if (cpufreq_frequency_table_target(policy, centrino_model->op_points, target_freq,
576 relation, &newstate)) {
581 msr = centrino_model->op_points[newstate].index;
582 rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
584 if (msr == (oldmsr & 0xffff)) {
589 /* Hm, old frequency can either be the last value we put in
590 PERF_CTL, or whatever it is now. The trouble is that TM2
591 can change it behind our back, which means we never get to
592 see the speed change. Reading back the current speed would
593 tell us something happened, but it may leave the things on
594 the notifier chain confused; we therefore stick to using
595 the last programmed speed rather than the current speed for
598 TODO: work out how the TCC interrupts work, and try to
599 catch the CPU changing things under us.
601 freqs.cpu = policy->cpu;
602 freqs.old = extract_clock(oldmsr);
603 freqs.new = extract_clock(msr);
605 dprintk(KERN_INFO PFX "target=%dkHz old=%d new=%d msr=%04x\n",
606 target_freq, freqs.old, freqs.new, msr);
608 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
610 /* all but 16 LSB are "reserved", so treat them with
616 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
618 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
622 set_cpus_allowed(current, saved_mask);
626 static struct freq_attr* centrino_attr[] = {
627 &cpufreq_freq_attr_scaling_available_freqs,
631 static struct cpufreq_driver centrino_driver = {
632 .name = "centrino", /* should be speedstep-centrino,
633 but there's a 16 char limit */
634 .init = centrino_cpu_init,
635 .exit = centrino_cpu_exit,
636 .verify = centrino_verify,
637 .target = centrino_target,
639 .attr = centrino_attr,
640 .owner = THIS_MODULE,
645 * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
647 * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
648 * unsupported devices, -ENOENT if there's no voltage table for this
649 * particular CPU model, -EINVAL on problems during initiatization,
650 * and zero on success.
652 * This is quite picky. Not only does the CPU have to advertise the
653 * "est" flag in the cpuid capability flags, we look for a specific
654 * CPU model and stepping, and we need to have the exact model name in
655 * our voltage tables. That is, be paranoid about not releasing
656 * someone's valuable magic smoke.
658 static int __init centrino_init(void)
660 struct cpuinfo_x86 *cpu = cpu_data;
662 if (!cpu_has(cpu, X86_FEATURE_EST))
665 return cpufreq_register_driver(¢rino_driver);
668 static void __exit centrino_exit(void)
670 cpufreq_unregister_driver(¢rino_driver);
673 MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
674 MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
675 MODULE_LICENSE ("GPL");
677 late_initcall(centrino_init);
678 module_exit(centrino_exit);