1 #include <linux/config.h>
2 #include <linux/init.h>
3 #include <linux/kernel.h>
5 #include <linux/string.h>
6 #include <linux/bitops.h>
8 #include <linux/thread_info.h>
10 #include <asm/processor.h>
12 #include <asm/uaccess.h>
17 #ifdef CONFIG_X86_LOCAL_APIC
18 #include <asm/mpspec.h>
20 #include <mach_apic.h>
23 #ifdef CONFIG_X86_INTEL_USERCOPY
25 * Alignment at which movsl is preferred for bulk memory copies.
27 struct movsl_mask movsl_mask;
30 void __init early_intel_workaround(struct cpuinfo_x86 *c)
32 if (c->x86_vendor != X86_VENDOR_INTEL)
34 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
35 if (c->x86 == 15 && c->x86_cache_alignment == 64)
36 c->x86_cache_alignment = 128;
40 * Early probe support logic for ppro memory erratum #50
42 * This is called before we do cpu ident work
45 int __init ppro_with_ram_bug(void)
47 /* Uses data from early_cpu_detect now */
48 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
49 boot_cpu_data.x86 == 6 &&
50 boot_cpu_data.x86_model == 1 &&
51 boot_cpu_data.x86_mask < 8) {
52 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
66 unsigned char descriptor;
71 /* all the cache descriptor types we care about (no TLB or trace cache entries) */
72 static struct _cache_table cache_table[] __initdata =
74 { 0x06, LVL_1_INST, 8 },
75 { 0x08, LVL_1_INST, 16 },
76 { 0x0a, LVL_1_DATA, 8 },
77 { 0x0c, LVL_1_DATA, 16 },
79 { 0x23, LVL_3, 1024 },
80 { 0x25, LVL_3, 2048 },
81 { 0x29, LVL_3, 4096 },
82 { 0x2c, LVL_1_DATA, 32 },
83 { 0x30, LVL_1_INST, 32 },
90 { 0x44, LVL_2, 1024 },
91 { 0x45, LVL_2, 2048 },
92 { 0x60, LVL_1_DATA, 16 },
93 { 0x66, LVL_1_DATA, 8 },
94 { 0x67, LVL_1_DATA, 16 },
95 { 0x68, LVL_1_DATA, 32 },
96 { 0x70, LVL_TRACE, 12 },
97 { 0x71, LVL_TRACE, 16 },
98 { 0x72, LVL_TRACE, 32 },
100 { 0x7a, LVL_2, 256 },
101 { 0x7b, LVL_2, 512 },
102 { 0x7c, LVL_2, 1024 },
103 { 0x82, LVL_2, 256 },
104 { 0x83, LVL_2, 512 },
105 { 0x84, LVL_2, 1024 },
106 { 0x85, LVL_2, 2048 },
107 { 0x86, LVL_2, 512 },
108 { 0x87, LVL_2, 1024 },
113 * P4 Xeon errata 037 workaround.
114 * Hardware prefetcher may cause stale data to be loaded into the cache.
116 static void __init Intel_errata_workarounds(struct cpuinfo_x86 *c)
118 unsigned long lo, hi;
120 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
121 rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
122 if ((lo & (1<<9)) == 0) {
123 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
124 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
125 lo |= (1<<9); /* Disable hw prefetching */
126 wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
132 static void __init init_intel(struct cpuinfo_x86 *c)
135 unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0; /* Cache sizes */
137 #ifdef CONFIG_X86_F00F_BUG
139 * All current models of Pentium and Pentium with MMX technology CPUs
140 * have the F0 0F bug, which lets nonprivileged users lock up the system.
141 * Note that the workaround only should be initialized once...
145 static int f00f_workaround_enabled = 0;
148 if ( !f00f_workaround_enabled ) {
149 trap_init_virtual_IDT();
150 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
151 f00f_workaround_enabled = 1;
156 select_idle_routine(c);
157 if (c->cpuid_level > 1) {
158 /* supports eax=2 call */
161 unsigned char *dp = (unsigned char *)regs;
163 /* Number of times to iterate */
164 n = cpuid_eax(2) & 0xFF;
166 for ( i = 0 ; i < n ; i++ ) {
167 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
169 /* If bit 31 is set, this is an unknown format */
170 for ( j = 0 ; j < 3 ; j++ ) {
171 if ( regs[j] < 0 ) regs[j] = 0;
174 /* Byte 0 is level count, not a descriptor */
175 for ( j = 1 ; j < 16 ; j++ ) {
176 unsigned char des = dp[j];
179 /* look up this descriptor in the table */
180 while (cache_table[k].descriptor != 0)
182 if (cache_table[k].descriptor == des) {
183 switch (cache_table[k].cache_type) {
185 l1i += cache_table[k].size;
188 l1d += cache_table[k].size;
191 l2 += cache_table[k].size;
194 l3 += cache_table[k].size;
197 trace += cache_table[k].size;
210 printk (KERN_INFO "CPU: Trace cache: %dK uops", trace);
212 printk (KERN_INFO "CPU: L1 I cache: %dK", l1i);
214 printk(", L1 D cache: %dK\n", l1d);
218 printk(KERN_INFO "CPU: L2 cache: %dK\n", l2);
220 printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
223 * This assumes the L3 cache is shared; it typically lives in
224 * the northbridge. The L1 caches are included by the L2
225 * cache, and so should not be included for the purpose of
226 * SMP switching weights.
228 c->x86_cache_size = l2 ? l2 : (l1i+l1d);
231 /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
232 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
233 clear_bit(X86_FEATURE_SEP, c->x86_capability);
235 /* Names for the Pentium II/Celeron processors
236 detectable only by also checking the cache size.
237 Dixon is NOT a Celeron. */
239 switch (c->x86_model) {
241 if (c->x86_mask == 0) {
243 p = "Celeron (Covington)";
245 p = "Mobile Pentium II (Dixon)";
251 p = "Celeron (Mendocino)";
252 else if (c->x86_mask == 0 || c->x86_mask == 5)
258 p = "Celeron (Coppermine)";
264 strcpy(c->x86_model_id, p);
267 if (cpu_has(c, X86_FEATURE_HT)) {
268 extern int phys_proc_id[NR_CPUS];
270 u32 eax, ebx, ecx, edx;
271 int index_lsb, index_msb, tmp;
272 int cpu = smp_processor_id();
274 cpuid(1, &eax, &ebx, &ecx, &edx);
275 smp_num_siblings = (ebx & 0xff0000) >> 16;
277 if (smp_num_siblings == 1) {
278 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
279 } else if (smp_num_siblings > 1 ) {
283 if (smp_num_siblings > NR_CPUS) {
284 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
285 smp_num_siblings = 1;
286 goto too_many_siblings;
288 tmp = smp_num_siblings;
289 while ((tmp & 1) == 0) {
293 tmp = smp_num_siblings;
294 while ((tmp & 0x80000000 ) == 0) {
298 if (index_lsb != index_msb )
300 phys_proc_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
302 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
311 /* Work around errata */
312 Intel_errata_workarounds(c);
314 #ifdef CONFIG_X86_INTEL_USERCOPY
316 * Set up the preferred alignment for movsl bulk memory moves
319 case 4: /* 486: untested */
321 case 5: /* Old Pentia: untested */
323 case 6: /* PII/PIII only like movsl with 8-byte alignment */
326 case 15: /* P4 is OK down to 8-byte alignment */
333 set_bit(X86_FEATURE_P4, c->x86_capability);
335 set_bit(X86_FEATURE_P3, c->x86_capability);
339 static unsigned int intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
341 /* Intel PIII Tualatin. This comes in two flavours.
342 * One has 256kb of cache, the other 512. We have no way
343 * to determine which, so we use a boottime override
344 * for the 512kb model, and assume 256 otherwise.
346 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
351 static struct cpu_dev intel_cpu_dev __initdata = {
353 .c_ident = { "GenuineIntel" },
355 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
357 [0] = "486 DX-25/33",
368 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
370 [0] = "Pentium 60/66 A-step",
371 [1] = "Pentium 60/66",
372 [2] = "Pentium 75 - 200",
373 [3] = "OverDrive PODP5V83",
375 [7] = "Mobile Pentium 75 - 200",
376 [8] = "Mobile Pentium MMX"
379 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
381 [0] = "Pentium Pro A-step",
383 [3] = "Pentium II (Klamath)",
384 [4] = "Pentium II (Deschutes)",
385 [5] = "Pentium II (Deschutes)",
386 [6] = "Mobile Pentium II",
387 [7] = "Pentium III (Katmai)",
388 [8] = "Pentium III (Coppermine)",
389 [10] = "Pentium III (Cascades)",
390 [11] = "Pentium III (Tualatin)",
393 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
395 [0] = "Pentium 4 (Unknown)",
396 [1] = "Pentium 4 (Willamette)",
397 [2] = "Pentium 4 (Northwood)",
398 [4] = "Pentium 4 (Foster)",
399 [5] = "Pentium 4 (Foster)",
403 .c_init = init_intel,
404 .c_identify = generic_identify,
405 .c_size_cache = intel_size_cache,
408 __init int intel_cpu_init(void)
410 cpu_devs[X86_VENDOR_INTEL] = &intel_cpu_dev;
414 // arch_initcall(intel_cpu_init);