1 #include <linux/config.h>
2 #include <linux/init.h>
3 #include <linux/kernel.h>
5 #include <linux/string.h>
6 #include <linux/bitops.h>
8 #include <linux/thread_info.h>
10 #include <asm/processor.h>
12 #include <asm/uaccess.h>
16 #ifdef CONFIG_X86_LOCAL_APIC
17 #include <asm/mpspec.h>
19 #include <mach_apic.h>
22 extern int trap_init_f00f_bug(void);
24 #ifdef CONFIG_X86_INTEL_USERCOPY
26 * Alignment at which movsl is preferred for bulk memory copies.
28 struct movsl_mask movsl_mask;
31 void __init early_intel_workaround(struct cpuinfo_x86 *c)
33 if (c->x86_vendor != X86_VENDOR_INTEL)
35 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
36 if (c->x86 == 15 && c->x86_cache_alignment == 64)
37 c->x86_cache_alignment = 128;
41 * Early probe support logic for ppro memory erratum #50
43 * This is called before we do cpu ident work
46 int __init ppro_with_ram_bug(void)
48 /* Uses data from early_cpu_detect now */
49 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
50 boot_cpu_data.x86 == 6 &&
51 boot_cpu_data.x86_model == 1 &&
52 boot_cpu_data.x86_mask < 8) {
53 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
61 * P4 Xeon errata 037 workaround.
62 * Hardware prefetcher may cause stale data to be loaded into the cache.
64 static void __init Intel_errata_workarounds(struct cpuinfo_x86 *c)
68 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
69 rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
70 if ((lo & (1<<9)) == 0) {
71 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
72 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
73 lo |= (1<<9); /* Disable hw prefetching */
74 wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
80 static void __init init_intel(struct cpuinfo_x86 *c)
85 #ifdef CONFIG_X86_F00F_BUG
87 * All current models of Pentium and Pentium with MMX technology CPUs
88 * have the F0 0F bug, which lets nonprivileged users lock up the system.
89 * Note that the workaround only should be initialized once...
93 static int f00f_workaround_enabled = 0;
96 if ( !f00f_workaround_enabled ) {
98 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
99 f00f_workaround_enabled = 1;
104 select_idle_routine(c);
105 l2 = init_intel_cacheinfo(c);
107 /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
108 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
109 clear_bit(X86_FEATURE_SEP, c->x86_capability);
111 /* Names for the Pentium II/Celeron processors
112 detectable only by also checking the cache size.
113 Dixon is NOT a Celeron. */
115 switch (c->x86_model) {
117 if (c->x86_mask == 0) {
119 p = "Celeron (Covington)";
121 p = "Mobile Pentium II (Dixon)";
127 p = "Celeron (Mendocino)";
128 else if (c->x86_mask == 0 || c->x86_mask == 5)
134 p = "Celeron (Coppermine)";
140 strcpy(c->x86_model_id, p);
143 if (cpu_has(c, X86_FEATURE_HT)) {
144 extern int phys_proc_id[NR_CPUS];
146 u32 eax, ebx, ecx, edx;
147 int index_lsb, index_msb, tmp;
148 int cpu = smp_processor_id();
150 cpuid(1, &eax, &ebx, &ecx, &edx);
151 smp_num_siblings = (ebx & 0xff0000) >> 16;
153 if (smp_num_siblings == 1) {
154 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
155 } else if (smp_num_siblings > 1 ) {
159 if (smp_num_siblings > NR_CPUS) {
160 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
161 smp_num_siblings = 1;
162 goto too_many_siblings;
164 tmp = smp_num_siblings;
165 while ((tmp & 1) == 0) {
169 tmp = smp_num_siblings;
170 while ((tmp & 0x80000000 ) == 0) {
174 if (index_lsb != index_msb )
176 phys_proc_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
178 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
187 /* Work around errata */
188 Intel_errata_workarounds(c);
190 #ifdef CONFIG_X86_INTEL_USERCOPY
192 * Set up the preferred alignment for movsl bulk memory moves
195 case 4: /* 486: untested */
197 case 5: /* Old Pentia: untested */
199 case 6: /* PII/PIII only like movsl with 8-byte alignment */
202 case 15: /* P4 is OK down to 8-byte alignment */
209 set_bit(X86_FEATURE_P4, c->x86_capability);
211 set_bit(X86_FEATURE_P3, c->x86_capability);
215 static unsigned int intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
217 /* Intel PIII Tualatin. This comes in two flavours.
218 * One has 256kb of cache, the other 512. We have no way
219 * to determine which, so we use a boottime override
220 * for the 512kb model, and assume 256 otherwise.
222 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
227 static struct cpu_dev intel_cpu_dev __initdata = {
229 .c_ident = { "GenuineIntel" },
231 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
233 [0] = "486 DX-25/33",
244 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
246 [0] = "Pentium 60/66 A-step",
247 [1] = "Pentium 60/66",
248 [2] = "Pentium 75 - 200",
249 [3] = "OverDrive PODP5V83",
251 [7] = "Mobile Pentium 75 - 200",
252 [8] = "Mobile Pentium MMX"
255 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
257 [0] = "Pentium Pro A-step",
259 [3] = "Pentium II (Klamath)",
260 [4] = "Pentium II (Deschutes)",
261 [5] = "Pentium II (Deschutes)",
262 [6] = "Mobile Pentium II",
263 [7] = "Pentium III (Katmai)",
264 [8] = "Pentium III (Coppermine)",
265 [10] = "Pentium III (Cascades)",
266 [11] = "Pentium III (Tualatin)",
269 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
271 [0] = "Pentium 4 (Unknown)",
272 [1] = "Pentium 4 (Willamette)",
273 [2] = "Pentium 4 (Northwood)",
274 [4] = "Pentium 4 (Foster)",
275 [5] = "Pentium 4 (Foster)",
279 .c_init = init_intel,
280 .c_identify = generic_identify,
281 .c_size_cache = intel_size_cache,
284 __init int intel_cpu_init(void)
286 cpu_devs[X86_VENDOR_INTEL] = &intel_cpu_dev;
290 // arch_initcall(intel_cpu_init);