2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/config.h>
29 #include <linux/smp_lock.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/compiler.h>
32 #include <linux/acpi.h>
33 #include <linux/module.h>
34 #include <linux/sysdev.h>
39 #include <asm/timer.h>
40 #include <asm/i8259.h>
42 #include <mach_apic.h>
48 #include <xen/interface/xen.h>
49 #include <xen/interface/physdev.h>
52 #define make_8259A_irq(_irq) (io_apic_irqs &= ~(1UL<<(_irq)))
53 #define disable_8259A_irq(_irq) ((void)0)
54 #define i8259A_irq_pending(_irq) (0)
56 unsigned long io_apic_irqs;
58 static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg)
60 struct physdev_apic apic_op;
63 apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
65 ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
71 static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
73 struct physdev_apic apic_op;
75 apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
77 apic_op.value = value;
78 HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op);
81 #define io_apic_read(a,r) xen_io_apic_read(a,r)
82 #define io_apic_write(a,r,v) xen_io_apic_write(a,r,v)
84 #endif /* CONFIG_XEN */
86 int (*ioapic_renumber_irq)(int ioapic, int irq);
87 atomic_t irq_mis_count;
89 /* Where if anywhere is the i8259 connect in external int mode */
90 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
92 static DEFINE_SPINLOCK(ioapic_lock);
94 int timer_over_8254 __initdata = 1;
97 * Is the SiS APIC rmw bug present ?
98 * -1 = don't know, 0 = no, 1 = yes
100 int sis_apic_bug = -1;
103 * # of IRQ routing registers
105 int nr_ioapic_registers[MAX_IO_APICS];
107 int disable_timer_pin_1 __initdata;
110 * Rough estimation of how many shared IRQs there are, can
111 * be changed anytime.
113 #define MAX_PLUS_SHARED_IRQS NR_IRQS
114 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
117 * This is performance-critical, we want to do it O(1)
119 * the indexing order of this array favors 1:1 mappings
120 * between pins and IRQs.
123 static struct irq_pin_list {
125 } irq_2_pin[PIN_MAP_SIZE];
127 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
128 #ifdef CONFIG_PCI_MSI
129 #define vector_to_irq(vector) \
130 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
132 #define vector_to_irq(vector) (vector)
136 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
137 * shared ISA-space IRQs, so we have to support them. We are super
138 * fast in the common case, and fast for shared ISA-space IRQs.
140 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
142 static int first_free_entry = NR_IRQS;
143 struct irq_pin_list *entry = irq_2_pin + irq;
146 entry = irq_2_pin + entry->next;
148 if (entry->pin != -1) {
149 entry->next = first_free_entry;
150 entry = irq_2_pin + entry->next;
151 if (++first_free_entry >= PIN_MAP_SIZE)
152 panic("io_apic.c: whoops");
159 #define clear_IO_APIC() ((void)0)
162 * Reroute an IRQ to a different pin.
164 static void __init replace_pin_at_irq(unsigned int irq,
165 int oldapic, int oldpin,
166 int newapic, int newpin)
168 struct irq_pin_list *entry = irq_2_pin + irq;
171 if (entry->apic == oldapic && entry->pin == oldpin) {
172 entry->apic = newapic;
177 entry = irq_2_pin + entry->next;
181 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
183 struct irq_pin_list *entry = irq_2_pin + irq;
184 unsigned int pin, reg;
190 reg = io_apic_read(entry->apic, 0x10 + pin*2);
193 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
196 entry = irq_2_pin + entry->next;
201 static void __mask_IO_APIC_irq (unsigned int irq)
203 __modify_IO_APIC_irq(irq, 0x00010000, 0);
207 static void __unmask_IO_APIC_irq (unsigned int irq)
209 __modify_IO_APIC_irq(irq, 0, 0x00010000);
212 /* mask = 1, trigger = 0 */
213 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
215 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
218 /* mask = 0, trigger = 1 */
219 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
221 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
224 static void mask_IO_APIC_irq (unsigned int irq)
228 spin_lock_irqsave(&ioapic_lock, flags);
229 __mask_IO_APIC_irq(irq);
230 spin_unlock_irqrestore(&ioapic_lock, flags);
233 static void unmask_IO_APIC_irq (unsigned int irq)
237 spin_lock_irqsave(&ioapic_lock, flags);
238 __unmask_IO_APIC_irq(irq);
239 spin_unlock_irqrestore(&ioapic_lock, flags);
242 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
244 struct IO_APIC_route_entry entry;
247 /* Check delivery_mode to be sure we're not clearing an SMI pin */
248 spin_lock_irqsave(&ioapic_lock, flags);
249 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
250 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
251 spin_unlock_irqrestore(&ioapic_lock, flags);
252 if (entry.delivery_mode == dest_SMI)
256 * Disable it in the IO-APIC irq-routing table:
258 memset(&entry, 0, sizeof(entry));
260 spin_lock_irqsave(&ioapic_lock, flags);
261 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
262 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
263 spin_unlock_irqrestore(&ioapic_lock, flags);
266 static void clear_IO_APIC (void)
270 for (apic = 0; apic < nr_ioapics; apic++)
271 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
272 clear_IO_APIC_pin(apic, pin);
276 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
280 struct irq_pin_list *entry = irq_2_pin + irq;
281 unsigned int apicid_value;
284 cpus_and(tmp, cpumask, cpu_online_map);
288 cpus_and(cpumask, tmp, CPU_MASK_ALL);
290 apicid_value = cpu_mask_to_apicid(cpumask);
291 /* Prepare to do the io_apic_write */
292 apicid_value = apicid_value << 24;
293 spin_lock_irqsave(&ioapic_lock, flags);
298 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
301 entry = irq_2_pin + entry->next;
303 set_irq_info(irq, cpumask);
304 spin_unlock_irqrestore(&ioapic_lock, flags);
307 #if defined(CONFIG_IRQBALANCE)
308 # include <asm/processor.h> /* kernel_thread() */
309 # include <linux/kernel_stat.h> /* kstat */
310 # include <linux/slab.h> /* kmalloc() */
311 # include <linux/timer.h> /* time_after() */
313 # ifdef CONFIG_BALANCED_IRQ_DEBUG
314 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
315 # define Dprintk(x...) do { TDprintk(x); } while (0)
317 # define TDprintk(x...)
318 # define Dprintk(x...)
322 #define IRQBALANCE_CHECK_ARCH -999
323 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
324 static int physical_balance = 0;
326 static struct irq_cpu_info {
327 unsigned long * last_irq;
328 unsigned long * irq_delta;
330 } irq_cpu_data[NR_CPUS];
332 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
333 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
334 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
336 #define IDLE_ENOUGH(cpu,now) \
337 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
339 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
341 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
343 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
344 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
345 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
346 #define BALANCED_IRQ_LESS_DELTA (HZ)
348 static long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
350 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
351 unsigned long now, int direction)
359 if (unlikely(cpu == curr_cpu))
362 if (direction == 1) {
371 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
372 (search_idle && !IDLE_ENOUGH(cpu,now)));
377 static inline void balance_irq(int cpu, int irq)
379 unsigned long now = jiffies;
380 cpumask_t allowed_mask;
381 unsigned int new_cpu;
383 if (irqbalance_disabled)
386 cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
387 new_cpu = move(cpu, allowed_mask, now, 1);
388 if (cpu != new_cpu) {
389 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
393 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
396 Dprintk("Rotating IRQs among CPUs.\n");
397 for_each_online_cpu(i) {
398 for (j = 0; j < NR_IRQS; j++) {
399 if (!irq_desc[j].action)
401 /* Is it a significant load ? */
402 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
403 useful_load_threshold)
408 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
409 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
413 static void do_irq_balance(void)
416 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
417 unsigned long move_this_load = 0;
418 int max_loaded = 0, min_loaded = 0;
420 unsigned long useful_load_threshold = balanced_irq_interval + 10;
422 int tmp_loaded, first_attempt = 1;
423 unsigned long tmp_cpu_irq;
424 unsigned long imbalance = 0;
425 cpumask_t allowed_mask, target_cpu_mask, tmp;
427 for_each_possible_cpu(i) {
432 package_index = CPU_TO_PACKAGEINDEX(i);
433 for (j = 0; j < NR_IRQS; j++) {
434 unsigned long value_now, delta;
435 /* Is this an active IRQ? */
436 if (!irq_desc[j].action)
438 if ( package_index == i )
439 IRQ_DELTA(package_index,j) = 0;
440 /* Determine the total count per processor per IRQ */
441 value_now = (unsigned long) kstat_cpu(i).irqs[j];
443 /* Determine the activity per processor per IRQ */
444 delta = value_now - LAST_CPU_IRQ(i,j);
446 /* Update last_cpu_irq[][] for the next time */
447 LAST_CPU_IRQ(i,j) = value_now;
449 /* Ignore IRQs whose rate is less than the clock */
450 if (delta < useful_load_threshold)
452 /* update the load for the processor or package total */
453 IRQ_DELTA(package_index,j) += delta;
455 /* Keep track of the higher numbered sibling as well */
456 if (i != package_index)
459 * We have sibling A and sibling B in the package
461 * cpu_irq[A] = load for cpu A + load for cpu B
462 * cpu_irq[B] = load for cpu B
464 CPU_IRQ(package_index) += delta;
467 /* Find the least loaded processor package */
468 for_each_online_cpu(i) {
469 if (i != CPU_TO_PACKAGEINDEX(i))
471 if (min_cpu_irq > CPU_IRQ(i)) {
472 min_cpu_irq = CPU_IRQ(i);
476 max_cpu_irq = ULONG_MAX;
479 /* Look for heaviest loaded processor.
480 * We may come back to get the next heaviest loaded processor.
481 * Skip processors with trivial loads.
485 for_each_online_cpu(i) {
486 if (i != CPU_TO_PACKAGEINDEX(i))
488 if (max_cpu_irq <= CPU_IRQ(i))
490 if (tmp_cpu_irq < CPU_IRQ(i)) {
491 tmp_cpu_irq = CPU_IRQ(i);
496 if (tmp_loaded == -1) {
497 /* In the case of small number of heavy interrupt sources,
498 * loading some of the cpus too much. We use Ingo's original
499 * approach to rotate them around.
501 if (!first_attempt && imbalance >= useful_load_threshold) {
502 rotate_irqs_among_cpus(useful_load_threshold);
505 goto not_worth_the_effort;
508 first_attempt = 0; /* heaviest search */
509 max_cpu_irq = tmp_cpu_irq; /* load */
510 max_loaded = tmp_loaded; /* processor */
511 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
513 Dprintk("max_loaded cpu = %d\n", max_loaded);
514 Dprintk("min_loaded cpu = %d\n", min_loaded);
515 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
516 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
517 Dprintk("load imbalance = %lu\n", imbalance);
519 /* if imbalance is less than approx 10% of max load, then
520 * observe diminishing returns action. - quit
522 if (imbalance < (max_cpu_irq >> 3)) {
523 Dprintk("Imbalance too trivial\n");
524 goto not_worth_the_effort;
528 /* if we select an IRQ to move that can't go where we want, then
529 * see if there is another one to try.
533 for (j = 0; j < NR_IRQS; j++) {
534 /* Is this an active IRQ? */
535 if (!irq_desc[j].action)
537 if (imbalance <= IRQ_DELTA(max_loaded,j))
539 /* Try to find the IRQ that is closest to the imbalance
540 * without going over.
542 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
543 move_this_load = IRQ_DELTA(max_loaded,j);
547 if (selected_irq == -1) {
551 imbalance = move_this_load;
553 /* For physical_balance case, we accumlated both load
554 * values in the one of the siblings cpu_irq[],
555 * to use the same code for physical and logical processors
556 * as much as possible.
558 * NOTE: the cpu_irq[] array holds the sum of the load for
559 * sibling A and sibling B in the slot for the lowest numbered
560 * sibling (A), _AND_ the load for sibling B in the slot for
561 * the higher numbered sibling.
563 * We seek the least loaded sibling by making the comparison
566 load = CPU_IRQ(min_loaded) >> 1;
567 for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
568 if (load > CPU_IRQ(j)) {
569 /* This won't change cpu_sibling_map[min_loaded] */
575 cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
576 target_cpu_mask = cpumask_of_cpu(min_loaded);
577 cpus_and(tmp, target_cpu_mask, allowed_mask);
579 if (!cpus_empty(tmp)) {
581 Dprintk("irq = %d moved to cpu = %d\n",
582 selected_irq, min_loaded);
583 /* mark for change destination */
584 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
586 /* Since we made a change, come back sooner to
587 * check for more variation.
589 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
590 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
595 not_worth_the_effort:
597 * if we did not find an IRQ to move, then adjust the time interval
600 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
601 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
602 Dprintk("IRQ worth rotating not found\n");
606 static int balanced_irq(void *unused)
609 unsigned long prev_balance_time = jiffies;
610 long time_remaining = balanced_irq_interval;
614 /* push everything to CPU 0 to give us a starting point. */
615 for (i = 0 ; i < NR_IRQS ; i++) {
616 pending_irq_cpumask[i] = cpumask_of_cpu(0);
617 set_pending_irq(i, cpumask_of_cpu(0));
621 time_remaining = schedule_timeout_interruptible(time_remaining);
623 if (time_after(jiffies,
624 prev_balance_time+balanced_irq_interval)) {
627 prev_balance_time = jiffies;
628 time_remaining = balanced_irq_interval;
635 static int __init balanced_irq_init(void)
638 struct cpuinfo_x86 *c;
641 cpus_shift_right(tmp, cpu_online_map, 2);
643 /* When not overwritten by the command line ask subarchitecture. */
644 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
645 irqbalance_disabled = NO_BALANCE_IRQ;
646 if (irqbalance_disabled)
649 /* disable irqbalance completely if there is only one processor online */
650 if (num_online_cpus() < 2) {
651 irqbalance_disabled = 1;
655 * Enable physical balance only if more than 1 physical processor
658 if (smp_num_siblings > 1 && !cpus_empty(tmp))
659 physical_balance = 1;
661 for_each_online_cpu(i) {
662 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
663 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
664 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
665 printk(KERN_ERR "balanced_irq_init: out of memory");
668 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
669 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
672 printk(KERN_INFO "Starting balanced_irq\n");
673 if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
676 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
678 for_each_possible_cpu(i) {
679 kfree(irq_cpu_data[i].irq_delta);
680 irq_cpu_data[i].irq_delta = NULL;
681 kfree(irq_cpu_data[i].last_irq);
682 irq_cpu_data[i].last_irq = NULL;
687 int __init irqbalance_disable(char *str)
689 irqbalance_disabled = 1;
693 __setup("noirqbalance", irqbalance_disable);
695 late_initcall(balanced_irq_init);
696 #endif /* CONFIG_IRQBALANCE */
697 #endif /* CONFIG_SMP */
701 void fastcall send_IPI_self(int vector)
709 apic_wait_icr_idle();
710 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
712 * Send the IPI. The write to APIC_ICR fires this off.
714 apic_write_around(APIC_ICR, cfg);
717 #endif /* !CONFIG_SMP */
721 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
722 * specific CPU-side IRQs.
726 static int pirq_entries [MAX_PIRQS];
727 static int pirqs_enabled;
728 int skip_ioapic_setup;
730 static int __init ioapic_setup(char *str)
732 skip_ioapic_setup = 1;
736 __setup("noapic", ioapic_setup);
738 static int __init ioapic_pirq_setup(char *str)
741 int ints[MAX_PIRQS+1];
743 get_options(str, ARRAY_SIZE(ints), ints);
745 for (i = 0; i < MAX_PIRQS; i++)
746 pirq_entries[i] = -1;
749 apic_printk(APIC_VERBOSE, KERN_INFO
750 "PIRQ redirection, working around broken MP-BIOS.\n");
752 if (ints[0] < MAX_PIRQS)
755 for (i = 0; i < max; i++) {
756 apic_printk(APIC_VERBOSE, KERN_DEBUG
757 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
759 * PIRQs are mapped upside down, usually.
761 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
766 __setup("pirq=", ioapic_pirq_setup);
769 * Find the IRQ entry number of a certain pin.
771 static int find_irq_entry(int apic, int pin, int type)
775 for (i = 0; i < mp_irq_entries; i++)
776 if (mp_irqs[i].mpc_irqtype == type &&
777 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
778 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
779 mp_irqs[i].mpc_dstirq == pin)
786 * Find the pin to which IRQ[irq] (ISA) is connected
788 static int __init find_isa_irq_pin(int irq, int type)
792 for (i = 0; i < mp_irq_entries; i++) {
793 int lbus = mp_irqs[i].mpc_srcbus;
795 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
796 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
797 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
798 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
800 (mp_irqs[i].mpc_irqtype == type) &&
801 (mp_irqs[i].mpc_srcbusirq == irq))
803 return mp_irqs[i].mpc_dstirq;
808 static int __init find_isa_irq_apic(int irq, int type)
812 for (i = 0; i < mp_irq_entries; i++) {
813 int lbus = mp_irqs[i].mpc_srcbus;
815 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
816 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
817 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
818 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
820 (mp_irqs[i].mpc_irqtype == type) &&
821 (mp_irqs[i].mpc_srcbusirq == irq))
824 if (i < mp_irq_entries) {
826 for(apic = 0; apic < nr_ioapics; apic++) {
827 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
836 * Find a specific PCI IRQ entry.
837 * Not an __init, possibly needed by modules
839 static int pin_2_irq(int idx, int apic, int pin);
841 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
843 int apic, i, best_guess = -1;
845 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
846 "slot:%d, pin:%d.\n", bus, slot, pin);
847 if (mp_bus_id_to_pci_bus[bus] == -1) {
848 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
851 for (i = 0; i < mp_irq_entries; i++) {
852 int lbus = mp_irqs[i].mpc_srcbus;
854 for (apic = 0; apic < nr_ioapics; apic++)
855 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
856 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
859 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
860 !mp_irqs[i].mpc_irqtype &&
862 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
863 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
865 if (!(apic || IO_APIC_IRQ(irq)))
868 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
871 * Use the first all-but-pin matching entry as a
872 * best-guess fuzzy result for broken mptables.
880 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
883 * This function currently is only a helper for the i386 smp boot process where
884 * we need to reprogram the ioredtbls to cater for the cpus which have come online
885 * so mask in all cases should simply be TARGET_CPUS
889 void __init setup_ioapic_dest(void)
891 int pin, ioapic, irq, irq_entry;
893 if (skip_ioapic_setup == 1)
896 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
897 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
898 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
901 irq = pin_2_irq(irq_entry, ioapic, pin);
902 set_ioapic_affinity_irq(irq, TARGET_CPUS);
907 #endif /* !CONFIG_XEN */
911 * EISA Edge/Level control register, ELCR
913 static int EISA_ELCR(unsigned int irq)
916 unsigned int port = 0x4d0 + (irq >> 3);
917 return (inb(port) >> (irq & 7)) & 1;
919 apic_printk(APIC_VERBOSE, KERN_INFO
920 "Broken MPtable reports ISA irq %d\n", irq);
924 /* EISA interrupts are always polarity zero and can be edge or level
925 * trigger depending on the ELCR value. If an interrupt is listed as
926 * EISA conforming in the MP table, that means its trigger type must
927 * be read in from the ELCR */
929 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
930 #define default_EISA_polarity(idx) (0)
932 /* ISA interrupts are always polarity zero edge triggered,
933 * when listed as conforming in the MP table. */
935 #define default_ISA_trigger(idx) (0)
936 #define default_ISA_polarity(idx) (0)
938 /* PCI interrupts are always polarity one level triggered,
939 * when listed as conforming in the MP table. */
941 #define default_PCI_trigger(idx) (1)
942 #define default_PCI_polarity(idx) (1)
944 /* MCA interrupts are always polarity zero level triggered,
945 * when listed as conforming in the MP table. */
947 #define default_MCA_trigger(idx) (1)
948 #define default_MCA_polarity(idx) (0)
950 /* NEC98 interrupts are always polarity zero edge triggered,
951 * when listed as conforming in the MP table. */
953 #define default_NEC98_trigger(idx) (0)
954 #define default_NEC98_polarity(idx) (0)
956 static int __init MPBIOS_polarity(int idx)
958 int bus = mp_irqs[idx].mpc_srcbus;
962 * Determine IRQ line polarity (high active or low active):
964 switch (mp_irqs[idx].mpc_irqflag & 3)
966 case 0: /* conforms, ie. bus-type dependent polarity */
968 switch (mp_bus_id_to_type[bus])
970 case MP_BUS_ISA: /* ISA pin */
972 polarity = default_ISA_polarity(idx);
975 case MP_BUS_EISA: /* EISA pin */
977 polarity = default_EISA_polarity(idx);
980 case MP_BUS_PCI: /* PCI pin */
982 polarity = default_PCI_polarity(idx);
985 case MP_BUS_MCA: /* MCA pin */
987 polarity = default_MCA_polarity(idx);
990 case MP_BUS_NEC98: /* NEC 98 pin */
992 polarity = default_NEC98_polarity(idx);
997 printk(KERN_WARNING "broken BIOS!!\n");
1004 case 1: /* high active */
1009 case 2: /* reserved */
1011 printk(KERN_WARNING "broken BIOS!!\n");
1015 case 3: /* low active */
1020 default: /* invalid */
1022 printk(KERN_WARNING "broken BIOS!!\n");
1030 static int MPBIOS_trigger(int idx)
1032 int bus = mp_irqs[idx].mpc_srcbus;
1036 * Determine IRQ trigger mode (edge or level sensitive):
1038 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1040 case 0: /* conforms, ie. bus-type dependent */
1042 switch (mp_bus_id_to_type[bus])
1044 case MP_BUS_ISA: /* ISA pin */
1046 trigger = default_ISA_trigger(idx);
1049 case MP_BUS_EISA: /* EISA pin */
1051 trigger = default_EISA_trigger(idx);
1054 case MP_BUS_PCI: /* PCI pin */
1056 trigger = default_PCI_trigger(idx);
1059 case MP_BUS_MCA: /* MCA pin */
1061 trigger = default_MCA_trigger(idx);
1064 case MP_BUS_NEC98: /* NEC 98 pin */
1066 trigger = default_NEC98_trigger(idx);
1071 printk(KERN_WARNING "broken BIOS!!\n");
1083 case 2: /* reserved */
1085 printk(KERN_WARNING "broken BIOS!!\n");
1094 default: /* invalid */
1096 printk(KERN_WARNING "broken BIOS!!\n");
1104 static inline int irq_polarity(int idx)
1106 return MPBIOS_polarity(idx);
1109 static inline int irq_trigger(int idx)
1111 return MPBIOS_trigger(idx);
1114 static int pin_2_irq(int idx, int apic, int pin)
1117 int bus = mp_irqs[idx].mpc_srcbus;
1120 * Debugging check, we are in big trouble if this message pops up!
1122 if (mp_irqs[idx].mpc_dstirq != pin)
1123 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1125 switch (mp_bus_id_to_type[bus])
1127 case MP_BUS_ISA: /* ISA pin */
1132 irq = mp_irqs[idx].mpc_srcbusirq;
1135 case MP_BUS_PCI: /* PCI pin */
1138 * PCI IRQs are mapped in order
1142 irq += nr_ioapic_registers[i++];
1146 * For MPS mode, so far only needed by ES7000 platform
1148 if (ioapic_renumber_irq)
1149 irq = ioapic_renumber_irq(apic, irq);
1155 printk(KERN_ERR "unknown bus type %d.\n",bus);
1162 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1164 if ((pin >= 16) && (pin <= 23)) {
1165 if (pirq_entries[pin-16] != -1) {
1166 if (!pirq_entries[pin-16]) {
1167 apic_printk(APIC_VERBOSE, KERN_DEBUG
1168 "disabling PIRQ%d\n", pin-16);
1170 irq = pirq_entries[pin-16];
1171 apic_printk(APIC_VERBOSE, KERN_DEBUG
1172 "using PIRQ%d -> IRQ %d\n",
1180 static inline int IO_APIC_irq_trigger(int irq)
1184 for (apic = 0; apic < nr_ioapics; apic++) {
1185 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1186 idx = find_irq_entry(apic,pin,mp_INT);
1187 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1188 return irq_trigger(idx);
1192 * nonexistent IRQs are edge default
1197 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1198 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly; /* = { FIRST_DEVICE_VECTOR , 0 }; */
1200 int assign_irq_vector(int irq)
1202 struct physdev_irq irq_op;
1204 BUG_ON(irq >= NR_IRQ_VECTORS);
1205 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1206 return IO_APIC_VECTOR(irq);
1209 if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op))
1212 vector_irq[irq_op.vector] = irq;
1213 if (irq != AUTO_ASSIGN)
1214 IO_APIC_VECTOR(irq) = irq_op.vector;
1216 return irq_op.vector;
1220 static struct hw_interrupt_type ioapic_level_type;
1221 static struct hw_interrupt_type ioapic_edge_type;
1223 #define IOAPIC_AUTO -1
1224 #define IOAPIC_EDGE 0
1225 #define IOAPIC_LEVEL 1
1227 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1229 if (use_pci_vector() && !platform_legacy_irq(irq)) {
1230 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1231 trigger == IOAPIC_LEVEL)
1232 irq_desc[vector].handler = &ioapic_level_type;
1234 irq_desc[vector].handler = &ioapic_edge_type;
1235 set_intr_gate(vector, interrupt[vector]);
1237 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1238 trigger == IOAPIC_LEVEL)
1239 irq_desc[irq].handler = &ioapic_level_type;
1241 irq_desc[irq].handler = &ioapic_edge_type;
1242 set_intr_gate(vector, interrupt[irq]);
1246 #define ioapic_register_intr(_irq,_vector,_trigger) ((void)0)
1249 static void __init setup_IO_APIC_irqs(void)
1251 struct IO_APIC_route_entry entry;
1252 int apic, pin, idx, irq, first_notcon = 1, vector;
1253 unsigned long flags;
1255 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1257 for (apic = 0; apic < nr_ioapics; apic++) {
1258 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1261 * add it to the IO-APIC irq-routing table:
1263 memset(&entry,0,sizeof(entry));
1265 entry.delivery_mode = INT_DELIVERY_MODE;
1266 entry.dest_mode = INT_DEST_MODE;
1267 entry.mask = 0; /* enable IRQ */
1268 entry.dest.logical.logical_dest =
1269 cpu_mask_to_apicid(TARGET_CPUS);
1271 idx = find_irq_entry(apic,pin,mp_INT);
1274 apic_printk(APIC_VERBOSE, KERN_DEBUG
1275 " IO-APIC (apicid-pin) %d-%d",
1276 mp_ioapics[apic].mpc_apicid,
1280 apic_printk(APIC_VERBOSE, ", %d-%d",
1281 mp_ioapics[apic].mpc_apicid, pin);
1285 entry.trigger = irq_trigger(idx);
1286 entry.polarity = irq_polarity(idx);
1288 if (irq_trigger(idx)) {
1293 irq = pin_2_irq(idx, apic, pin);
1295 * skip adding the timer int on secondary nodes, which causes
1296 * a small but painful rift in the time-space continuum
1298 if (multi_timer_check(apic, irq))
1301 add_pin_to_irq(irq, apic, pin);
1303 if (/*!apic &&*/ !IO_APIC_IRQ(irq))
1306 if (IO_APIC_IRQ(irq)) {
1307 vector = assign_irq_vector(irq);
1308 entry.vector = vector;
1309 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1311 if (!apic && (irq < 16))
1312 disable_8259A_irq(irq);
1314 spin_lock_irqsave(&ioapic_lock, flags);
1315 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1316 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1317 set_native_irq_info(irq, TARGET_CPUS);
1318 spin_unlock_irqrestore(&ioapic_lock, flags);
1323 apic_printk(APIC_VERBOSE, " not connected.\n");
1327 * Set up the 8259A-master output pin:
1330 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1332 struct IO_APIC_route_entry entry;
1333 unsigned long flags;
1335 memset(&entry,0,sizeof(entry));
1337 disable_8259A_irq(0);
1340 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1343 * We use logical delivery to get the timer IRQ
1346 entry.dest_mode = INT_DEST_MODE;
1347 entry.mask = 0; /* unmask IRQ now */
1348 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1349 entry.delivery_mode = INT_DELIVERY_MODE;
1352 entry.vector = vector;
1355 * The timer IRQ doesn't have to know that behind the
1356 * scene we have a 8259A-master in AEOI mode ...
1358 irq_desc[0].handler = &ioapic_edge_type;
1361 * Add it to the IO-APIC irq-routing table:
1363 spin_lock_irqsave(&ioapic_lock, flags);
1364 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1365 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1366 spin_unlock_irqrestore(&ioapic_lock, flags);
1368 enable_8259A_irq(0);
1371 static inline void UNEXPECTED_IO_APIC(void)
1375 void __init print_IO_APIC(void)
1378 union IO_APIC_reg_00 reg_00;
1379 union IO_APIC_reg_01 reg_01;
1380 union IO_APIC_reg_02 reg_02;
1381 union IO_APIC_reg_03 reg_03;
1382 unsigned long flags;
1384 if (apic_verbosity == APIC_QUIET)
1387 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1388 for (i = 0; i < nr_ioapics; i++)
1389 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1390 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1393 * We are a bit conservative about what we expect. We have to
1394 * know about every hardware change ASAP.
1396 printk(KERN_INFO "testing the IO APIC.......................\n");
1398 for (apic = 0; apic < nr_ioapics; apic++) {
1400 spin_lock_irqsave(&ioapic_lock, flags);
1401 reg_00.raw = io_apic_read(apic, 0);
1402 reg_01.raw = io_apic_read(apic, 1);
1403 if (reg_01.bits.version >= 0x10)
1404 reg_02.raw = io_apic_read(apic, 2);
1405 if (reg_01.bits.version >= 0x20)
1406 reg_03.raw = io_apic_read(apic, 3);
1407 spin_unlock_irqrestore(&ioapic_lock, flags);
1409 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1410 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1411 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1412 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1413 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1414 if (reg_00.bits.ID >= get_physical_broadcast())
1415 UNEXPECTED_IO_APIC();
1416 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1417 UNEXPECTED_IO_APIC();
1419 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1420 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1421 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1422 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1423 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1424 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1425 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1426 (reg_01.bits.entries != 0x2E) &&
1427 (reg_01.bits.entries != 0x3F)
1429 UNEXPECTED_IO_APIC();
1431 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1432 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1433 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1434 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1435 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1436 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1437 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1439 UNEXPECTED_IO_APIC();
1440 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1441 UNEXPECTED_IO_APIC();
1444 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1445 * but the value of reg_02 is read as the previous read register
1446 * value, so ignore it if reg_02 == reg_01.
1448 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1449 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1450 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1451 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1452 UNEXPECTED_IO_APIC();
1456 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1457 * or reg_03, but the value of reg_0[23] is read as the previous read
1458 * register value, so ignore it if reg_03 == reg_0[12].
1460 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1461 reg_03.raw != reg_01.raw) {
1462 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1463 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1464 if (reg_03.bits.__reserved_1)
1465 UNEXPECTED_IO_APIC();
1468 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1470 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1471 " Stat Dest Deli Vect: \n");
1473 for (i = 0; i <= reg_01.bits.entries; i++) {
1474 struct IO_APIC_route_entry entry;
1476 spin_lock_irqsave(&ioapic_lock, flags);
1477 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1478 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1479 spin_unlock_irqrestore(&ioapic_lock, flags);
1481 printk(KERN_DEBUG " %02x %03X %02X ",
1483 entry.dest.logical.logical_dest,
1484 entry.dest.physical.physical_dest
1487 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1492 entry.delivery_status,
1494 entry.delivery_mode,
1499 if (use_pci_vector())
1500 printk(KERN_INFO "Using vector-based indexing\n");
1501 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1502 for (i = 0; i < NR_IRQS; i++) {
1503 struct irq_pin_list *entry = irq_2_pin + i;
1506 if (use_pci_vector() && !platform_legacy_irq(i))
1507 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1509 printk(KERN_DEBUG "IRQ%d ", i);
1511 printk("-> %d:%d", entry->apic, entry->pin);
1514 entry = irq_2_pin + entry->next;
1519 printk(KERN_INFO ".................................... done.\n");
1526 static void print_APIC_bitfield (int base)
1531 if (apic_verbosity == APIC_QUIET)
1534 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1535 for (i = 0; i < 8; i++) {
1536 v = apic_read(base + i*0x10);
1537 for (j = 0; j < 32; j++) {
1547 void /*__init*/ print_local_APIC(void * dummy)
1549 unsigned int v, ver, maxlvt;
1551 if (apic_verbosity == APIC_QUIET)
1554 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1555 smp_processor_id(), hard_smp_processor_id());
1556 v = apic_read(APIC_ID);
1557 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1558 v = apic_read(APIC_LVR);
1559 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1560 ver = GET_APIC_VERSION(v);
1561 maxlvt = get_maxlvt();
1563 v = apic_read(APIC_TASKPRI);
1564 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1566 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1567 v = apic_read(APIC_ARBPRI);
1568 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1569 v & APIC_ARBPRI_MASK);
1570 v = apic_read(APIC_PROCPRI);
1571 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1574 v = apic_read(APIC_EOI);
1575 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1576 v = apic_read(APIC_RRR);
1577 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1578 v = apic_read(APIC_LDR);
1579 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1580 v = apic_read(APIC_DFR);
1581 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1582 v = apic_read(APIC_SPIV);
1583 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1585 printk(KERN_DEBUG "... APIC ISR field:\n");
1586 print_APIC_bitfield(APIC_ISR);
1587 printk(KERN_DEBUG "... APIC TMR field:\n");
1588 print_APIC_bitfield(APIC_TMR);
1589 printk(KERN_DEBUG "... APIC IRR field:\n");
1590 print_APIC_bitfield(APIC_IRR);
1592 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1593 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1594 apic_write(APIC_ESR, 0);
1595 v = apic_read(APIC_ESR);
1596 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1599 v = apic_read(APIC_ICR);
1600 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1601 v = apic_read(APIC_ICR2);
1602 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1604 v = apic_read(APIC_LVTT);
1605 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1607 if (maxlvt > 3) { /* PC is LVT#4. */
1608 v = apic_read(APIC_LVTPC);
1609 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1611 v = apic_read(APIC_LVT0);
1612 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1613 v = apic_read(APIC_LVT1);
1614 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1616 if (maxlvt > 2) { /* ERR is LVT#3. */
1617 v = apic_read(APIC_LVTERR);
1618 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1621 v = apic_read(APIC_TMICT);
1622 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1623 v = apic_read(APIC_TMCCT);
1624 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1625 v = apic_read(APIC_TDCR);
1626 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1630 void print_all_local_APICs (void)
1632 on_each_cpu(print_local_APIC, NULL, 1, 1);
1635 void /*__init*/ print_PIC(void)
1638 unsigned long flags;
1640 if (apic_verbosity == APIC_QUIET)
1643 printk(KERN_DEBUG "\nprinting PIC contents\n");
1645 spin_lock_irqsave(&i8259A_lock, flags);
1647 v = inb(0xa1) << 8 | inb(0x21);
1648 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1650 v = inb(0xa0) << 8 | inb(0x20);
1651 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1655 v = inb(0xa0) << 8 | inb(0x20);
1659 spin_unlock_irqrestore(&i8259A_lock, flags);
1661 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1663 v = inb(0x4d1) << 8 | inb(0x4d0);
1664 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1670 void __init print_IO_APIC(void) { }
1671 #endif /* !CONFIG_XEN */
1673 static void __init enable_IO_APIC(void)
1675 union IO_APIC_reg_01 reg_01;
1676 int i8259_apic, i8259_pin;
1678 unsigned long flags;
1680 for (i = 0; i < PIN_MAP_SIZE; i++) {
1681 irq_2_pin[i].pin = -1;
1682 irq_2_pin[i].next = 0;
1685 for (i = 0; i < MAX_PIRQS; i++)
1686 pirq_entries[i] = -1;
1689 * The number of IO-APIC IRQ registers (== #pins):
1691 for (apic = 0; apic < nr_ioapics; apic++) {
1692 spin_lock_irqsave(&ioapic_lock, flags);
1693 reg_01.raw = io_apic_read(apic, 1);
1694 spin_unlock_irqrestore(&ioapic_lock, flags);
1695 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1697 for(apic = 0; apic < nr_ioapics; apic++) {
1699 /* See if any of the pins is in ExtINT mode */
1700 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1701 struct IO_APIC_route_entry entry;
1702 spin_lock_irqsave(&ioapic_lock, flags);
1703 *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1704 *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1705 spin_unlock_irqrestore(&ioapic_lock, flags);
1708 /* If the interrupt line is enabled and in ExtInt mode
1709 * I have found the pin where the i8259 is connected.
1711 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1712 ioapic_i8259.apic = apic;
1713 ioapic_i8259.pin = pin;
1719 /* Look to see what if the MP table has reported the ExtINT */
1720 /* If we could not find the appropriate pin by looking at the ioapic
1721 * the i8259 probably is not connected the ioapic but give the
1722 * mptable a chance anyway.
1724 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1725 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1726 /* Trust the MP table if nothing is setup in the hardware */
1727 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1728 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1729 ioapic_i8259.pin = i8259_pin;
1730 ioapic_i8259.apic = i8259_apic;
1732 /* Complain if the MP table and the hardware disagree */
1733 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1734 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1736 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1740 * Do not trust the IO-APIC being empty at bootup
1746 * Not an __init, needed by the reboot code
1748 void disable_IO_APIC(void)
1751 * Clear the IO-APIC before rebooting:
1757 * If the i8259 is routed through an IOAPIC
1758 * Put that IOAPIC in virtual wire mode
1759 * so legacy interrupts can be delivered.
1761 if (ioapic_i8259.pin != -1) {
1762 struct IO_APIC_route_entry entry;
1763 unsigned long flags;
1765 memset(&entry, 0, sizeof(entry));
1766 entry.mask = 0; /* Enabled */
1767 entry.trigger = 0; /* Edge */
1769 entry.polarity = 0; /* High */
1770 entry.delivery_status = 0;
1771 entry.dest_mode = 0; /* Physical */
1772 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1774 entry.dest.physical.physical_dest =
1775 GET_APIC_ID(apic_read(APIC_ID));
1778 * Add it to the IO-APIC irq-routing table:
1780 spin_lock_irqsave(&ioapic_lock, flags);
1781 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1782 *(((int *)&entry)+1));
1783 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1784 *(((int *)&entry)+0));
1785 spin_unlock_irqrestore(&ioapic_lock, flags);
1787 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1792 * function to set the IO-APIC physical IDs based on the
1793 * values stored in the MPC table.
1795 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1798 #if !defined(CONFIG_XEN) && !defined(CONFIG_X86_NUMAQ)
1799 static void __init setup_ioapic_ids_from_mpc(void)
1801 union IO_APIC_reg_00 reg_00;
1802 physid_mask_t phys_id_present_map;
1805 unsigned char old_id;
1806 unsigned long flags;
1809 * Don't check I/O APIC IDs for xAPIC systems. They have
1810 * no meaning without the serial APIC bus.
1812 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1813 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1816 * This is broken; anything with a real cpu count has to
1817 * circumvent this idiocy regardless.
1819 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1822 * Set the IOAPIC ID to the value stored in the MPC table.
1824 for (apic = 0; apic < nr_ioapics; apic++) {
1826 /* Read the register 0 value */
1827 spin_lock_irqsave(&ioapic_lock, flags);
1828 reg_00.raw = io_apic_read(apic, 0);
1829 spin_unlock_irqrestore(&ioapic_lock, flags);
1831 old_id = mp_ioapics[apic].mpc_apicid;
1833 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1834 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1835 apic, mp_ioapics[apic].mpc_apicid);
1836 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1838 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1842 * Sanity check, is the ID really free? Every APIC in a
1843 * system must have a unique ID or we get lots of nice
1844 * 'stuck on smp_invalidate_needed IPI wait' messages.
1846 if (check_apicid_used(phys_id_present_map,
1847 mp_ioapics[apic].mpc_apicid)) {
1848 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1849 apic, mp_ioapics[apic].mpc_apicid);
1850 for (i = 0; i < get_physical_broadcast(); i++)
1851 if (!physid_isset(i, phys_id_present_map))
1853 if (i >= get_physical_broadcast())
1854 panic("Max APIC ID exceeded!\n");
1855 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1857 physid_set(i, phys_id_present_map);
1858 mp_ioapics[apic].mpc_apicid = i;
1861 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1862 apic_printk(APIC_VERBOSE, "Setting %d in the "
1863 "phys_id_present_map\n",
1864 mp_ioapics[apic].mpc_apicid);
1865 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1870 * We need to adjust the IRQ routing table
1871 * if the ID changed.
1873 if (old_id != mp_ioapics[apic].mpc_apicid)
1874 for (i = 0; i < mp_irq_entries; i++)
1875 if (mp_irqs[i].mpc_dstapic == old_id)
1876 mp_irqs[i].mpc_dstapic
1877 = mp_ioapics[apic].mpc_apicid;
1880 * Read the right value from the MPC table and
1881 * write it into the ID register.
1883 apic_printk(APIC_VERBOSE, KERN_INFO
1884 "...changing IO-APIC physical APIC ID to %d ...",
1885 mp_ioapics[apic].mpc_apicid);
1887 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1888 spin_lock_irqsave(&ioapic_lock, flags);
1889 io_apic_write(apic, 0, reg_00.raw);
1890 spin_unlock_irqrestore(&ioapic_lock, flags);
1895 spin_lock_irqsave(&ioapic_lock, flags);
1896 reg_00.raw = io_apic_read(apic, 0);
1897 spin_unlock_irqrestore(&ioapic_lock, flags);
1898 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1899 printk("could not set ID!\n");
1901 apic_printk(APIC_VERBOSE, " ok.\n");
1905 static void __init setup_ioapic_ids_from_mpc(void) { }
1910 * There is a nasty bug in some older SMP boards, their mptable lies
1911 * about the timer IRQ. We do the following to work around the situation:
1913 * - timer IRQ defaults to IO-APIC IRQ
1914 * - if this function detects that timer IRQs are defunct, then we fall
1915 * back to ISA timer IRQs
1917 static int __init timer_irq_works(void)
1919 unsigned long t1 = jiffies;
1922 /* Let ten ticks pass... */
1923 mdelay((10 * 1000) / HZ);
1926 * Expect a few ticks at least, to be sure some possible
1927 * glue logic does not lock up after one or two first
1928 * ticks in a non-ExtINT mode. Also the local APIC
1929 * might have cached one ExtINT interrupt. Finally, at
1930 * least one tick may be lost due to delays.
1932 if (jiffies - t1 > 4)
1939 * In the SMP+IOAPIC case it might happen that there are an unspecified
1940 * number of pending IRQ events unhandled. These cases are very rare,
1941 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1942 * better to do it this way as thus we do not have to be aware of
1943 * 'pending' interrupts in the IRQ path, except at this point.
1946 * Edge triggered needs to resend any interrupt
1947 * that was delayed but this is now handled in the device
1952 * Starting up a edge-triggered IO-APIC interrupt is
1953 * nasty - we need to make sure that we get the edge.
1954 * If it is already asserted for some reason, we need
1955 * return 1 to indicate that is was pending.
1957 * This is not complete - we should be able to fake
1958 * an edge even if it isn't on the 8259A...
1960 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1962 int was_pending = 0;
1963 unsigned long flags;
1965 spin_lock_irqsave(&ioapic_lock, flags);
1967 disable_8259A_irq(irq);
1968 if (i8259A_irq_pending(irq))
1971 __unmask_IO_APIC_irq(irq);
1972 spin_unlock_irqrestore(&ioapic_lock, flags);
1978 * Once we have recorded IRQ_PENDING already, we can mask the
1979 * interrupt for real. This prevents IRQ storms from unhandled
1982 static void ack_edge_ioapic_irq(unsigned int irq)
1985 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1986 == (IRQ_PENDING | IRQ_DISABLED))
1987 mask_IO_APIC_irq(irq);
1992 * Level triggered interrupts can just be masked,
1993 * and shutting down and starting up the interrupt
1994 * is the same as enabling and disabling them -- except
1995 * with a startup need to return a "was pending" value.
1997 * Level triggered interrupts are special because we
1998 * do not touch any IO-APIC register while handling
1999 * them. We ack the APIC in the end-IRQ handler, not
2000 * in the start-IRQ-handler. Protection against reentrance
2001 * from the same interrupt is still provided, both by the
2002 * generic IRQ layer and by the fact that an unacked local
2003 * APIC does not accept IRQs.
2005 static unsigned int startup_level_ioapic_irq (unsigned int irq)
2007 unmask_IO_APIC_irq(irq);
2009 return 0; /* don't check for pending */
2012 static void end_level_ioapic_irq (unsigned int irq)
2019 * It appears there is an erratum which affects at least version 0x11
2020 * of I/O APIC (that's the 82093AA and cores integrated into various
2021 * chipsets). Under certain conditions a level-triggered interrupt is
2022 * erroneously delivered as edge-triggered one but the respective IRR
2023 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2024 * message but it will never arrive and further interrupts are blocked
2025 * from the source. The exact reason is so far unknown, but the
2026 * phenomenon was observed when two consecutive interrupt requests
2027 * from a given source get delivered to the same CPU and the source is
2028 * temporarily disabled in between.
2030 * A workaround is to simulate an EOI message manually. We achieve it
2031 * by setting the trigger mode to edge and then to level when the edge
2032 * trigger mode gets detected in the TMR of a local APIC for a
2033 * level-triggered interrupt. We mask the source for the time of the
2034 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2035 * The idea is from Manfred Spraul. --macro
2037 i = IO_APIC_VECTOR(irq);
2039 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2043 if (!(v & (1 << (i & 0x1f)))) {
2044 atomic_inc(&irq_mis_count);
2045 spin_lock(&ioapic_lock);
2046 __mask_and_edge_IO_APIC_irq(irq);
2047 __unmask_and_level_IO_APIC_irq(irq);
2048 spin_unlock(&ioapic_lock);
2052 #ifdef CONFIG_PCI_MSI
2053 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
2055 int irq = vector_to_irq(vector);
2057 return startup_edge_ioapic_irq(irq);
2060 static void ack_edge_ioapic_vector(unsigned int vector)
2062 int irq = vector_to_irq(vector);
2064 move_native_irq(vector);
2065 ack_edge_ioapic_irq(irq);
2068 static unsigned int startup_level_ioapic_vector (unsigned int vector)
2070 int irq = vector_to_irq(vector);
2072 return startup_level_ioapic_irq (irq);
2075 static void end_level_ioapic_vector (unsigned int vector)
2077 int irq = vector_to_irq(vector);
2079 move_native_irq(vector);
2080 end_level_ioapic_irq(irq);
2083 static void mask_IO_APIC_vector (unsigned int vector)
2085 int irq = vector_to_irq(vector);
2087 mask_IO_APIC_irq(irq);
2090 static void unmask_IO_APIC_vector (unsigned int vector)
2092 int irq = vector_to_irq(vector);
2094 unmask_IO_APIC_irq(irq);
2098 static void set_ioapic_affinity_vector (unsigned int vector,
2101 int irq = vector_to_irq(vector);
2103 set_native_irq_info(vector, cpu_mask);
2104 set_ioapic_affinity_irq(irq, cpu_mask);
2110 * Level and edge triggered IO-APIC interrupts need different handling,
2111 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2112 * handled with the level-triggered descriptor, but that one has slightly
2113 * more overhead. Level-triggered interrupts cannot be handled with the
2114 * edge-triggered handler, without risking IRQ storms and other ugly
2117 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
2118 .typename = "IO-APIC-edge",
2119 .startup = startup_edge_ioapic,
2120 .shutdown = shutdown_edge_ioapic,
2121 .enable = enable_edge_ioapic,
2122 .disable = disable_edge_ioapic,
2123 .ack = ack_edge_ioapic,
2124 .end = end_edge_ioapic,
2126 .set_affinity = set_ioapic_affinity,
2130 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
2131 .typename = "IO-APIC-level",
2132 .startup = startup_level_ioapic,
2133 .shutdown = shutdown_level_ioapic,
2134 .enable = enable_level_ioapic,
2135 .disable = disable_level_ioapic,
2136 .ack = mask_and_ack_level_ioapic,
2137 .end = end_level_ioapic,
2139 .set_affinity = set_ioapic_affinity,
2142 #endif /* !CONFIG_XEN */
2144 static inline void init_IO_APIC_traps(void)
2149 * NOTE! The local APIC isn't very good at handling
2150 * multiple interrupts at the same interrupt level.
2151 * As the interrupt level is determined by taking the
2152 * vector number and shifting that right by 4, we
2153 * want to spread these out a bit so that they don't
2154 * all fall in the same interrupt level.
2156 * Also, we've got to be careful not to trash gate
2157 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2159 for (irq = 0; irq < NR_IRQS ; irq++) {
2161 if (use_pci_vector()) {
2162 if (!platform_legacy_irq(tmp))
2163 if ((tmp = vector_to_irq(tmp)) == -1)
2166 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2168 * Hmm.. We don't have an entry for this,
2169 * so default to an old-fashioned 8259
2170 * interrupt if we can..
2173 make_8259A_irq(irq);
2176 /* Strange. Oh, well.. */
2177 irq_desc[irq].handler = &no_irq_type;
2184 static void enable_lapic_irq (unsigned int irq)
2188 v = apic_read(APIC_LVT0);
2189 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2192 static void disable_lapic_irq (unsigned int irq)
2196 v = apic_read(APIC_LVT0);
2197 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2200 static void ack_lapic_irq (unsigned int irq)
2205 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2207 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
2208 .typename = "local-APIC-edge",
2209 .startup = NULL, /* startup_irq() not used for IRQ0 */
2210 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
2211 .enable = enable_lapic_irq,
2212 .disable = disable_lapic_irq,
2213 .ack = ack_lapic_irq,
2214 .end = end_lapic_irq
2217 static void setup_nmi (void)
2220 * Dirty trick to enable the NMI watchdog ...
2221 * We put the 8259A master into AEOI mode and
2222 * unmask on all local APICs LVT0 as NMI.
2224 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2225 * is from Maciej W. Rozycki - so we do not have to EOI from
2226 * the NMI handler or the timer interrupt.
2228 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2230 on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2232 apic_printk(APIC_VERBOSE, " done.\n");
2236 * This looks a bit hackish but it's about the only one way of sending
2237 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2238 * not support the ExtINT mode, unfortunately. We need to send these
2239 * cycles as some i82489DX-based boards have glue logic that keeps the
2240 * 8259A interrupt line asserted until INTA. --macro
2242 static inline void unlock_ExtINT_logic(void)
2245 struct IO_APIC_route_entry entry0, entry1;
2246 unsigned char save_control, save_freq_select;
2247 unsigned long flags;
2249 pin = find_isa_irq_pin(8, mp_INT);
2250 apic = find_isa_irq_apic(8, mp_INT);
2254 spin_lock_irqsave(&ioapic_lock, flags);
2255 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
2256 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
2257 spin_unlock_irqrestore(&ioapic_lock, flags);
2258 clear_IO_APIC_pin(apic, pin);
2260 memset(&entry1, 0, sizeof(entry1));
2262 entry1.dest_mode = 0; /* physical delivery */
2263 entry1.mask = 0; /* unmask IRQ now */
2264 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2265 entry1.delivery_mode = dest_ExtINT;
2266 entry1.polarity = entry0.polarity;
2270 spin_lock_irqsave(&ioapic_lock, flags);
2271 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2272 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2273 spin_unlock_irqrestore(&ioapic_lock, flags);
2275 save_control = CMOS_READ(RTC_CONTROL);
2276 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2277 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2279 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2284 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2288 CMOS_WRITE(save_control, RTC_CONTROL);
2289 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2290 clear_IO_APIC_pin(apic, pin);
2292 spin_lock_irqsave(&ioapic_lock, flags);
2293 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2294 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2295 spin_unlock_irqrestore(&ioapic_lock, flags);
2298 int timer_uses_ioapic_pin_0;
2301 * This code may look a bit paranoid, but it's supposed to cooperate with
2302 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2303 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2304 * fanatically on his truly buggy board.
2306 static inline void check_timer(void)
2308 int apic1, pin1, apic2, pin2;
2312 * get/set the timer IRQ vector:
2314 disable_8259A_irq(0);
2315 vector = assign_irq_vector(0);
2316 set_intr_gate(vector, interrupt[0]);
2319 * Subtle, code in do_timer_interrupt() expects an AEOI
2320 * mode for the 8259A whenever interrupts are routed
2321 * through I/O APICs. Also IRQ0 has to be enabled in
2322 * the 8259A which implies the virtual wire has to be
2323 * disabled in the local APIC.
2325 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2328 if (timer_over_8254 > 0)
2329 enable_8259A_irq(0);
2331 pin1 = find_isa_irq_pin(0, mp_INT);
2332 apic1 = find_isa_irq_apic(0, mp_INT);
2333 pin2 = ioapic_i8259.pin;
2334 apic2 = ioapic_i8259.apic;
2337 timer_uses_ioapic_pin_0 = 1;
2339 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2340 vector, apic1, pin1, apic2, pin2);
2344 * Ok, does IRQ0 through the IOAPIC work?
2346 unmask_IO_APIC_irq(0);
2347 if (timer_irq_works()) {
2348 if (nmi_watchdog == NMI_IO_APIC) {
2349 disable_8259A_irq(0);
2351 enable_8259A_irq(0);
2353 if (disable_timer_pin_1 > 0)
2354 clear_IO_APIC_pin(0, pin1);
2357 clear_IO_APIC_pin(apic1, pin1);
2358 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2362 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2364 printk("\n..... (found pin %d) ...", pin2);
2366 * legacy devices should be connected to IO APIC #0
2368 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2369 if (timer_irq_works()) {
2372 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2374 add_pin_to_irq(0, apic2, pin2);
2375 if (nmi_watchdog == NMI_IO_APIC) {
2381 * Cleanup, just in case ...
2383 clear_IO_APIC_pin(apic2, pin2);
2385 printk(" failed.\n");
2387 if (nmi_watchdog == NMI_IO_APIC) {
2388 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2392 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2394 disable_8259A_irq(0);
2395 irq_desc[0].handler = &lapic_irq_type;
2396 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2397 enable_8259A_irq(0);
2399 if (timer_irq_works()) {
2400 printk(" works.\n");
2403 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2404 printk(" failed.\n");
2406 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2411 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2413 unlock_ExtINT_logic();
2415 if (timer_irq_works()) {
2416 printk(" works.\n");
2419 printk(" failed :(.\n");
2420 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2421 "report. Then try booting with the 'noapic' option");
2424 int timer_uses_ioapic_pin_0;
2425 #define check_timer() ((void)0)
2430 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2431 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2432 * Linux doesn't really care, as it's not actually used
2433 * for any interrupt handling anyway.
2435 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2437 void __init setup_IO_APIC(void)
2442 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2444 io_apic_irqs = ~PIC_IRQS;
2446 printk("ENABLING IO-APIC IRQs\n");
2449 * Set up IO-APIC IRQ routing.
2452 setup_ioapic_ids_from_mpc();
2456 setup_IO_APIC_irqs();
2457 init_IO_APIC_traps();
2463 static int __init setup_disable_8254_timer(char *s)
2465 timer_over_8254 = -1;
2468 static int __init setup_enable_8254_timer(char *s)
2470 timer_over_8254 = 2;
2474 __setup("disable_8254_timer", setup_disable_8254_timer);
2475 __setup("enable_8254_timer", setup_enable_8254_timer);
2478 * Called after all the initialization is done. If we didnt find any
2479 * APIC bugs then we can allow the modify fast path
2482 static int __init io_apic_bug_finalize(void)
2484 if(sis_apic_bug == -1)
2486 if (xen_start_info->flags & SIF_INITDOMAIN) {
2487 dom0_op_t op = { .cmd = DOM0_PLATFORM_QUIRK };
2488 op.u.platform_quirk.quirk_id = sis_apic_bug ?
2489 QUIRK_IOAPIC_BAD_REGSEL : QUIRK_IOAPIC_GOOD_REGSEL;
2490 HYPERVISOR_dom0_op(&op);
2495 late_initcall(io_apic_bug_finalize);
2497 struct sysfs_ioapic_data {
2498 struct sys_device dev;
2499 struct IO_APIC_route_entry entry[0];
2501 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2503 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2505 struct IO_APIC_route_entry *entry;
2506 struct sysfs_ioapic_data *data;
2507 unsigned long flags;
2510 data = container_of(dev, struct sysfs_ioapic_data, dev);
2511 entry = data->entry;
2512 spin_lock_irqsave(&ioapic_lock, flags);
2513 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2514 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2515 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2517 spin_unlock_irqrestore(&ioapic_lock, flags);
2522 static int ioapic_resume(struct sys_device *dev)
2524 struct IO_APIC_route_entry *entry;
2525 struct sysfs_ioapic_data *data;
2526 unsigned long flags;
2527 union IO_APIC_reg_00 reg_00;
2530 data = container_of(dev, struct sysfs_ioapic_data, dev);
2531 entry = data->entry;
2533 spin_lock_irqsave(&ioapic_lock, flags);
2534 reg_00.raw = io_apic_read(dev->id, 0);
2535 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2536 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2537 io_apic_write(dev->id, 0, reg_00.raw);
2539 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2540 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2541 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2543 spin_unlock_irqrestore(&ioapic_lock, flags);
2548 static struct sysdev_class ioapic_sysdev_class = {
2549 set_kset_name("ioapic"),
2550 .suspend = ioapic_suspend,
2551 .resume = ioapic_resume,
2554 static int __init ioapic_init_sysfs(void)
2556 struct sys_device * dev;
2557 int i, size, error = 0;
2559 error = sysdev_class_register(&ioapic_sysdev_class);
2563 for (i = 0; i < nr_ioapics; i++ ) {
2564 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2565 * sizeof(struct IO_APIC_route_entry);
2566 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2567 if (!mp_ioapic_data[i]) {
2568 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2571 memset(mp_ioapic_data[i], 0, size);
2572 dev = &mp_ioapic_data[i]->dev;
2574 dev->cls = &ioapic_sysdev_class;
2575 error = sysdev_register(dev);
2577 kfree(mp_ioapic_data[i]);
2578 mp_ioapic_data[i] = NULL;
2579 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2587 device_initcall(ioapic_init_sysfs);
2589 /* --------------------------------------------------------------------------
2590 ACPI-based IOAPIC Configuration
2591 -------------------------------------------------------------------------- */
2595 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2598 union IO_APIC_reg_00 reg_00;
2599 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2601 unsigned long flags;
2605 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2606 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2607 * supports up to 16 on one shared APIC bus.
2609 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2610 * advantage of new APIC bus architecture.
2613 if (physids_empty(apic_id_map))
2614 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2616 spin_lock_irqsave(&ioapic_lock, flags);
2617 reg_00.raw = io_apic_read(ioapic, 0);
2618 spin_unlock_irqrestore(&ioapic_lock, flags);
2620 if (apic_id >= get_physical_broadcast()) {
2621 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2622 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2623 apic_id = reg_00.bits.ID;
2627 * Every APIC in a system must have a unique ID or we get lots of nice
2628 * 'stuck on smp_invalidate_needed IPI wait' messages.
2630 if (check_apicid_used(apic_id_map, apic_id)) {
2632 for (i = 0; i < get_physical_broadcast(); i++) {
2633 if (!check_apicid_used(apic_id_map, i))
2637 if (i == get_physical_broadcast())
2638 panic("Max apic_id exceeded!\n");
2640 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2641 "trying %d\n", ioapic, apic_id, i);
2646 tmp = apicid_to_cpu_present(apic_id);
2647 physids_or(apic_id_map, apic_id_map, tmp);
2649 if (reg_00.bits.ID != apic_id) {
2650 reg_00.bits.ID = apic_id;
2652 spin_lock_irqsave(&ioapic_lock, flags);
2653 io_apic_write(ioapic, 0, reg_00.raw);
2654 reg_00.raw = io_apic_read(ioapic, 0);
2655 spin_unlock_irqrestore(&ioapic_lock, flags);
2658 if (reg_00.bits.ID != apic_id) {
2659 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2664 apic_printk(APIC_VERBOSE, KERN_INFO
2665 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2666 #endif /* !CONFIG_XEN */
2672 int __init io_apic_get_version (int ioapic)
2674 union IO_APIC_reg_01 reg_01;
2675 unsigned long flags;
2677 spin_lock_irqsave(&ioapic_lock, flags);
2678 reg_01.raw = io_apic_read(ioapic, 1);
2679 spin_unlock_irqrestore(&ioapic_lock, flags);
2681 return reg_01.bits.version;
2685 int __init io_apic_get_redir_entries (int ioapic)
2687 union IO_APIC_reg_01 reg_01;
2688 unsigned long flags;
2690 spin_lock_irqsave(&ioapic_lock, flags);
2691 reg_01.raw = io_apic_read(ioapic, 1);
2692 spin_unlock_irqrestore(&ioapic_lock, flags);
2694 return reg_01.bits.entries;
2698 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2700 struct IO_APIC_route_entry entry;
2701 unsigned long flags;
2703 if (!IO_APIC_IRQ(irq)) {
2704 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2710 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2711 * Note that we mask (disable) IRQs now -- these get enabled when the
2712 * corresponding device driver registers for this IRQ.
2715 memset(&entry,0,sizeof(entry));
2717 entry.delivery_mode = INT_DELIVERY_MODE;
2718 entry.dest_mode = INT_DEST_MODE;
2719 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2720 entry.trigger = edge_level;
2721 entry.polarity = active_high_low;
2725 * IRQs < 16 are already in the irq_2_pin[] map
2728 add_pin_to_irq(irq, ioapic, pin);
2730 entry.vector = assign_irq_vector(irq);
2732 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2733 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2734 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2735 edge_level, active_high_low);
2737 ioapic_register_intr(irq, entry.vector, edge_level);
2739 if (!ioapic && (irq < 16))
2740 disable_8259A_irq(irq);
2742 spin_lock_irqsave(&ioapic_lock, flags);
2743 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2744 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2745 set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2746 spin_unlock_irqrestore(&ioapic_lock, flags);
2751 #endif /* CONFIG_ACPI */