2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
42 #include <asm/timer.h>
43 #include <asm/i8259.h>
45 #include <asm/msidef.h>
46 #include <asm/hypertransport.h>
48 #include <mach_apic.h>
49 #include <mach_apicdef.h>
55 #include <xen/interface/xen.h>
56 #include <xen/interface/physdev.h>
59 #define make_8259A_irq(_irq) (io_apic_irqs &= ~(1UL<<(_irq)))
60 #define disable_8259A_irq(_irq) ((void)0)
61 #define i8259A_irq_pending(_irq) (0)
63 unsigned long io_apic_irqs;
65 static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg)
67 struct physdev_apic apic_op;
70 apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
72 ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
78 static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
80 struct physdev_apic apic_op;
82 apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
84 apic_op.value = value;
85 HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op);
88 #define io_apic_read(a,r) xen_io_apic_read(a,r)
89 #define io_apic_write(a,r,v) xen_io_apic_write(a,r,v)
91 #endif /* CONFIG_XEN */
93 int (*ioapic_renumber_irq)(int ioapic, int irq);
94 atomic_t irq_mis_count;
96 /* Where if anywhere is the i8259 connect in external int mode */
97 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
99 static DEFINE_SPINLOCK(ioapic_lock);
100 static DEFINE_SPINLOCK(vector_lock);
102 int timer_over_8254 __initdata = 1;
105 * Is the SiS APIC rmw bug present ?
106 * -1 = don't know, 0 = no, 1 = yes
108 int sis_apic_bug = -1;
111 * # of IRQ routing registers
113 int nr_ioapic_registers[MAX_IO_APICS];
115 static int disable_timer_pin_1 __initdata;
118 * Rough estimation of how many shared IRQs there are, can
119 * be changed anytime.
121 #define MAX_PLUS_SHARED_IRQS NR_IRQS
122 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
125 * This is performance-critical, we want to do it O(1)
127 * the indexing order of this array favors 1:1 mappings
128 * between pins and IRQs.
131 static struct irq_pin_list {
133 } irq_2_pin[PIN_MAP_SIZE];
138 unsigned int unused[3];
142 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
144 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
145 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
148 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
150 struct io_apic __iomem *io_apic = io_apic_base(apic);
151 writel(reg, &io_apic->index);
152 return readl(&io_apic->data);
155 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
157 struct io_apic __iomem *io_apic = io_apic_base(apic);
158 writel(reg, &io_apic->index);
159 writel(value, &io_apic->data);
163 * Re-write a value: to be used for read-modify-write
164 * cycles where the read already set up the index register.
166 * Older SiS APIC requires we rewrite the index register
168 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
170 volatile struct io_apic *io_apic = io_apic_base(apic);
172 writel(reg, &io_apic->index);
173 writel(value, &io_apic->data);
175 #endif /* !CONFIG_XEN */
178 struct { u32 w1, w2; };
179 struct IO_APIC_route_entry entry;
182 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
184 union entry_union eu;
186 spin_lock_irqsave(&ioapic_lock, flags);
187 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
188 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
189 spin_unlock_irqrestore(&ioapic_lock, flags);
194 * When we write a new IO APIC routing entry, we need to write the high
195 * word first! If the mask bit in the low word is clear, we will enable
196 * the interrupt, and we need to make sure the entry is fully populated
197 * before that happens.
200 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
202 union entry_union eu;
204 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
205 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
208 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
211 spin_lock_irqsave(&ioapic_lock, flags);
212 __ioapic_write_entry(apic, pin, e);
213 spin_unlock_irqrestore(&ioapic_lock, flags);
217 * When we mask an IO APIC routing entry, we need to write the low
218 * word first, in order to set the mask bit before we change the
223 static void ioapic_mask_entry(int apic, int pin)
226 union entry_union eu = { .entry.mask = 1 };
228 spin_lock_irqsave(&ioapic_lock, flags);
229 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
230 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
231 spin_unlock_irqrestore(&ioapic_lock, flags);
236 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
237 * shared ISA-space IRQs, so we have to support them. We are super
238 * fast in the common case, and fast for shared ISA-space IRQs.
240 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
242 static int first_free_entry = NR_IRQS;
243 struct irq_pin_list *entry = irq_2_pin + irq;
246 entry = irq_2_pin + entry->next;
248 if (entry->pin != -1) {
249 entry->next = first_free_entry;
250 entry = irq_2_pin + entry->next;
251 if (++first_free_entry >= PIN_MAP_SIZE)
252 panic("io_apic.c: whoops");
259 #define clear_IO_APIC() ((void)0)
262 * Reroute an IRQ to a different pin.
264 static void __init replace_pin_at_irq(unsigned int irq,
265 int oldapic, int oldpin,
266 int newapic, int newpin)
268 struct irq_pin_list *entry = irq_2_pin + irq;
271 if (entry->apic == oldapic && entry->pin == oldpin) {
272 entry->apic = newapic;
277 entry = irq_2_pin + entry->next;
281 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
283 struct irq_pin_list *entry = irq_2_pin + irq;
284 unsigned int pin, reg;
290 reg = io_apic_read(entry->apic, 0x10 + pin*2);
293 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
296 entry = irq_2_pin + entry->next;
301 static void __mask_IO_APIC_irq (unsigned int irq)
303 __modify_IO_APIC_irq(irq, 0x00010000, 0);
307 static void __unmask_IO_APIC_irq (unsigned int irq)
309 __modify_IO_APIC_irq(irq, 0, 0x00010000);
312 /* mask = 1, trigger = 0 */
313 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
315 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
318 /* mask = 0, trigger = 1 */
319 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
321 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
324 static void mask_IO_APIC_irq (unsigned int irq)
328 spin_lock_irqsave(&ioapic_lock, flags);
329 __mask_IO_APIC_irq(irq);
330 spin_unlock_irqrestore(&ioapic_lock, flags);
333 static void unmask_IO_APIC_irq (unsigned int irq)
337 spin_lock_irqsave(&ioapic_lock, flags);
338 __unmask_IO_APIC_irq(irq);
339 spin_unlock_irqrestore(&ioapic_lock, flags);
342 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
344 struct IO_APIC_route_entry entry;
346 /* Check delivery_mode to be sure we're not clearing an SMI pin */
347 entry = ioapic_read_entry(apic, pin);
348 if (entry.delivery_mode == dest_SMI)
352 * Disable it in the IO-APIC irq-routing table:
354 ioapic_mask_entry(apic, pin);
357 static void clear_IO_APIC (void)
361 for (apic = 0; apic < nr_ioapics; apic++)
362 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
363 clear_IO_APIC_pin(apic, pin);
367 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
371 struct irq_pin_list *entry = irq_2_pin + irq;
372 unsigned int apicid_value;
375 cpus_and(tmp, cpumask, cpu_online_map);
379 cpus_and(cpumask, tmp, CPU_MASK_ALL);
381 apicid_value = cpu_mask_to_apicid(cpumask);
382 /* Prepare to do the io_apic_write */
383 apicid_value = apicid_value << 24;
384 spin_lock_irqsave(&ioapic_lock, flags);
389 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
392 entry = irq_2_pin + entry->next;
394 set_native_irq_info(irq, cpumask);
395 spin_unlock_irqrestore(&ioapic_lock, flags);
398 #if defined(CONFIG_IRQBALANCE)
399 # include <asm/processor.h> /* kernel_thread() */
400 # include <linux/kernel_stat.h> /* kstat */
401 # include <linux/slab.h> /* kmalloc() */
402 # include <linux/timer.h> /* time_after() */
404 #ifdef CONFIG_BALANCED_IRQ_DEBUG
405 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
406 # define Dprintk(x...) do { TDprintk(x); } while (0)
408 # define TDprintk(x...)
409 # define Dprintk(x...)
412 #define IRQBALANCE_CHECK_ARCH -999
413 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
414 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
415 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
416 #define BALANCED_IRQ_LESS_DELTA (HZ)
418 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
419 static int physical_balance __read_mostly;
420 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
422 static struct irq_cpu_info {
423 unsigned long * last_irq;
424 unsigned long * irq_delta;
426 } irq_cpu_data[NR_CPUS];
428 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
429 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
430 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
432 #define IDLE_ENOUGH(cpu,now) \
433 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
435 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
437 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
439 static cpumask_t balance_irq_affinity[NR_IRQS] = {
440 [0 ... NR_IRQS-1] = CPU_MASK_ALL
443 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
445 balance_irq_affinity[irq] = mask;
448 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
449 unsigned long now, int direction)
457 if (unlikely(cpu == curr_cpu))
460 if (direction == 1) {
469 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
470 (search_idle && !IDLE_ENOUGH(cpu,now)));
475 static inline void balance_irq(int cpu, int irq)
477 unsigned long now = jiffies;
478 cpumask_t allowed_mask;
479 unsigned int new_cpu;
481 if (irqbalance_disabled)
484 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
485 new_cpu = move(cpu, allowed_mask, now, 1);
486 if (cpu != new_cpu) {
487 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
491 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
494 Dprintk("Rotating IRQs among CPUs.\n");
495 for_each_online_cpu(i) {
496 for (j = 0; j < NR_IRQS; j++) {
497 if (!irq_desc[j].action)
499 /* Is it a significant load ? */
500 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
501 useful_load_threshold)
506 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
507 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
511 static void do_irq_balance(void)
514 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
515 unsigned long move_this_load = 0;
516 int max_loaded = 0, min_loaded = 0;
518 unsigned long useful_load_threshold = balanced_irq_interval + 10;
520 int tmp_loaded, first_attempt = 1;
521 unsigned long tmp_cpu_irq;
522 unsigned long imbalance = 0;
523 cpumask_t allowed_mask, target_cpu_mask, tmp;
525 for_each_possible_cpu(i) {
530 package_index = CPU_TO_PACKAGEINDEX(i);
531 for (j = 0; j < NR_IRQS; j++) {
532 unsigned long value_now, delta;
533 /* Is this an active IRQ? */
534 if (!irq_desc[j].action)
536 if ( package_index == i )
537 IRQ_DELTA(package_index,j) = 0;
538 /* Determine the total count per processor per IRQ */
539 value_now = (unsigned long) kstat_cpu(i).irqs[j];
541 /* Determine the activity per processor per IRQ */
542 delta = value_now - LAST_CPU_IRQ(i,j);
544 /* Update last_cpu_irq[][] for the next time */
545 LAST_CPU_IRQ(i,j) = value_now;
547 /* Ignore IRQs whose rate is less than the clock */
548 if (delta < useful_load_threshold)
550 /* update the load for the processor or package total */
551 IRQ_DELTA(package_index,j) += delta;
553 /* Keep track of the higher numbered sibling as well */
554 if (i != package_index)
557 * We have sibling A and sibling B in the package
559 * cpu_irq[A] = load for cpu A + load for cpu B
560 * cpu_irq[B] = load for cpu B
562 CPU_IRQ(package_index) += delta;
565 /* Find the least loaded processor package */
566 for_each_online_cpu(i) {
567 if (i != CPU_TO_PACKAGEINDEX(i))
569 if (min_cpu_irq > CPU_IRQ(i)) {
570 min_cpu_irq = CPU_IRQ(i);
574 max_cpu_irq = ULONG_MAX;
577 /* Look for heaviest loaded processor.
578 * We may come back to get the next heaviest loaded processor.
579 * Skip processors with trivial loads.
583 for_each_online_cpu(i) {
584 if (i != CPU_TO_PACKAGEINDEX(i))
586 if (max_cpu_irq <= CPU_IRQ(i))
588 if (tmp_cpu_irq < CPU_IRQ(i)) {
589 tmp_cpu_irq = CPU_IRQ(i);
594 if (tmp_loaded == -1) {
595 /* In the case of small number of heavy interrupt sources,
596 * loading some of the cpus too much. We use Ingo's original
597 * approach to rotate them around.
599 if (!first_attempt && imbalance >= useful_load_threshold) {
600 rotate_irqs_among_cpus(useful_load_threshold);
603 goto not_worth_the_effort;
606 first_attempt = 0; /* heaviest search */
607 max_cpu_irq = tmp_cpu_irq; /* load */
608 max_loaded = tmp_loaded; /* processor */
609 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
611 Dprintk("max_loaded cpu = %d\n", max_loaded);
612 Dprintk("min_loaded cpu = %d\n", min_loaded);
613 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
614 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
615 Dprintk("load imbalance = %lu\n", imbalance);
617 /* if imbalance is less than approx 10% of max load, then
618 * observe diminishing returns action. - quit
620 if (imbalance < (max_cpu_irq >> 3)) {
621 Dprintk("Imbalance too trivial\n");
622 goto not_worth_the_effort;
626 /* if we select an IRQ to move that can't go where we want, then
627 * see if there is another one to try.
631 for (j = 0; j < NR_IRQS; j++) {
632 /* Is this an active IRQ? */
633 if (!irq_desc[j].action)
635 if (imbalance <= IRQ_DELTA(max_loaded,j))
637 /* Try to find the IRQ that is closest to the imbalance
638 * without going over.
640 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
641 move_this_load = IRQ_DELTA(max_loaded,j);
645 if (selected_irq == -1) {
649 imbalance = move_this_load;
651 /* For physical_balance case, we accumlated both load
652 * values in the one of the siblings cpu_irq[],
653 * to use the same code for physical and logical processors
654 * as much as possible.
656 * NOTE: the cpu_irq[] array holds the sum of the load for
657 * sibling A and sibling B in the slot for the lowest numbered
658 * sibling (A), _AND_ the load for sibling B in the slot for
659 * the higher numbered sibling.
661 * We seek the least loaded sibling by making the comparison
664 load = CPU_IRQ(min_loaded) >> 1;
665 for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
666 if (load > CPU_IRQ(j)) {
667 /* This won't change cpu_sibling_map[min_loaded] */
673 cpus_and(allowed_mask,
675 balance_irq_affinity[selected_irq]);
676 target_cpu_mask = cpumask_of_cpu(min_loaded);
677 cpus_and(tmp, target_cpu_mask, allowed_mask);
679 if (!cpus_empty(tmp)) {
681 Dprintk("irq = %d moved to cpu = %d\n",
682 selected_irq, min_loaded);
683 /* mark for change destination */
684 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
686 /* Since we made a change, come back sooner to
687 * check for more variation.
689 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
690 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
695 not_worth_the_effort:
697 * if we did not find an IRQ to move, then adjust the time interval
700 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
701 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
702 Dprintk("IRQ worth rotating not found\n");
706 static int balanced_irq(void *unused)
709 unsigned long prev_balance_time = jiffies;
710 long time_remaining = balanced_irq_interval;
714 /* push everything to CPU 0 to give us a starting point. */
715 for (i = 0 ; i < NR_IRQS ; i++) {
716 irq_desc[i].pending_mask = cpumask_of_cpu(0);
717 set_pending_irq(i, cpumask_of_cpu(0));
721 time_remaining = schedule_timeout_interruptible(time_remaining);
723 if (time_after(jiffies,
724 prev_balance_time+balanced_irq_interval)) {
727 prev_balance_time = jiffies;
728 time_remaining = balanced_irq_interval;
735 static int __init balanced_irq_init(void)
738 struct cpuinfo_x86 *c;
741 cpus_shift_right(tmp, cpu_online_map, 2);
743 /* When not overwritten by the command line ask subarchitecture. */
744 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
745 irqbalance_disabled = NO_BALANCE_IRQ;
746 if (irqbalance_disabled)
749 /* disable irqbalance completely if there is only one processor online */
750 if (num_online_cpus() < 2) {
751 irqbalance_disabled = 1;
755 * Enable physical balance only if more than 1 physical processor
758 if (smp_num_siblings > 1 && !cpus_empty(tmp))
759 physical_balance = 1;
761 for_each_online_cpu(i) {
762 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
763 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
764 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
765 printk(KERN_ERR "balanced_irq_init: out of memory");
768 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
769 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
772 printk(KERN_INFO "Starting balanced_irq\n");
773 if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
776 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
778 for_each_possible_cpu(i) {
779 kfree(irq_cpu_data[i].irq_delta);
780 irq_cpu_data[i].irq_delta = NULL;
781 kfree(irq_cpu_data[i].last_irq);
782 irq_cpu_data[i].last_irq = NULL;
787 int __init irqbalance_disable(char *str)
789 irqbalance_disabled = 1;
793 __setup("noirqbalance", irqbalance_disable);
795 late_initcall(balanced_irq_init);
796 #endif /* CONFIG_IRQBALANCE */
797 #endif /* CONFIG_SMP */
798 #endif /* !CONFIG_XEN */
801 void fastcall send_IPI_self(int vector)
809 apic_wait_icr_idle();
810 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
812 * Send the IPI. The write to APIC_ICR fires this off.
814 apic_write_around(APIC_ICR, cfg);
817 #endif /* !CONFIG_SMP */
821 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
822 * specific CPU-side IRQs.
826 static int pirq_entries [MAX_PIRQS];
827 static int pirqs_enabled;
828 int skip_ioapic_setup;
830 static int __init ioapic_setup(char *str)
832 skip_ioapic_setup = 1;
836 __setup("noapic", ioapic_setup);
838 static int __init ioapic_pirq_setup(char *str)
841 int ints[MAX_PIRQS+1];
843 get_options(str, ARRAY_SIZE(ints), ints);
845 for (i = 0; i < MAX_PIRQS; i++)
846 pirq_entries[i] = -1;
849 apic_printk(APIC_VERBOSE, KERN_INFO
850 "PIRQ redirection, working around broken MP-BIOS.\n");
852 if (ints[0] < MAX_PIRQS)
855 for (i = 0; i < max; i++) {
856 apic_printk(APIC_VERBOSE, KERN_DEBUG
857 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
859 * PIRQs are mapped upside down, usually.
861 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
866 __setup("pirq=", ioapic_pirq_setup);
869 * Find the IRQ entry number of a certain pin.
871 static int find_irq_entry(int apic, int pin, int type)
875 for (i = 0; i < mp_irq_entries; i++)
876 if (mp_irqs[i].mpc_irqtype == type &&
877 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
878 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
879 mp_irqs[i].mpc_dstirq == pin)
886 * Find the pin to which IRQ[irq] (ISA) is connected
888 static int __init find_isa_irq_pin(int irq, int type)
892 for (i = 0; i < mp_irq_entries; i++) {
893 int lbus = mp_irqs[i].mpc_srcbus;
895 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
896 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
897 mp_bus_id_to_type[lbus] == MP_BUS_MCA
899 (mp_irqs[i].mpc_irqtype == type) &&
900 (mp_irqs[i].mpc_srcbusirq == irq))
902 return mp_irqs[i].mpc_dstirq;
907 static int __init find_isa_irq_apic(int irq, int type)
911 for (i = 0; i < mp_irq_entries; i++) {
912 int lbus = mp_irqs[i].mpc_srcbus;
914 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
915 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
916 mp_bus_id_to_type[lbus] == MP_BUS_MCA
918 (mp_irqs[i].mpc_irqtype == type) &&
919 (mp_irqs[i].mpc_srcbusirq == irq))
922 if (i < mp_irq_entries) {
924 for(apic = 0; apic < nr_ioapics; apic++) {
925 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
934 * Find a specific PCI IRQ entry.
935 * Not an __init, possibly needed by modules
937 static int pin_2_irq(int idx, int apic, int pin);
939 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
941 int apic, i, best_guess = -1;
943 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
944 "slot:%d, pin:%d.\n", bus, slot, pin);
945 if (mp_bus_id_to_pci_bus[bus] == -1) {
946 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
949 for (i = 0; i < mp_irq_entries; i++) {
950 int lbus = mp_irqs[i].mpc_srcbus;
952 for (apic = 0; apic < nr_ioapics; apic++)
953 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
954 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
957 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
958 !mp_irqs[i].mpc_irqtype &&
960 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
961 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
963 if (!(apic || IO_APIC_IRQ(irq)))
966 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
969 * Use the first all-but-pin matching entry as a
970 * best-guess fuzzy result for broken mptables.
978 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
981 * This function currently is only a helper for the i386 smp boot process where
982 * we need to reprogram the ioredtbls to cater for the cpus which have come online
983 * so mask in all cases should simply be TARGET_CPUS
987 void __init setup_ioapic_dest(void)
989 int pin, ioapic, irq, irq_entry;
991 if (skip_ioapic_setup == 1)
994 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
995 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
996 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
999 irq = pin_2_irq(irq_entry, ioapic, pin);
1000 set_ioapic_affinity_irq(irq, TARGET_CPUS);
1005 #endif /* !CONFIG_XEN */
1009 * EISA Edge/Level control register, ELCR
1011 static int EISA_ELCR(unsigned int irq)
1014 unsigned int port = 0x4d0 + (irq >> 3);
1015 return (inb(port) >> (irq & 7)) & 1;
1017 apic_printk(APIC_VERBOSE, KERN_INFO
1018 "Broken MPtable reports ISA irq %d\n", irq);
1022 /* EISA interrupts are always polarity zero and can be edge or level
1023 * trigger depending on the ELCR value. If an interrupt is listed as
1024 * EISA conforming in the MP table, that means its trigger type must
1025 * be read in from the ELCR */
1027 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
1028 #define default_EISA_polarity(idx) (0)
1030 /* ISA interrupts are always polarity zero edge triggered,
1031 * when listed as conforming in the MP table. */
1033 #define default_ISA_trigger(idx) (0)
1034 #define default_ISA_polarity(idx) (0)
1036 /* PCI interrupts are always polarity one level triggered,
1037 * when listed as conforming in the MP table. */
1039 #define default_PCI_trigger(idx) (1)
1040 #define default_PCI_polarity(idx) (1)
1042 /* MCA interrupts are always polarity zero level triggered,
1043 * when listed as conforming in the MP table. */
1045 #define default_MCA_trigger(idx) (1)
1046 #define default_MCA_polarity(idx) (0)
1048 static int __init MPBIOS_polarity(int idx)
1050 int bus = mp_irqs[idx].mpc_srcbus;
1054 * Determine IRQ line polarity (high active or low active):
1056 switch (mp_irqs[idx].mpc_irqflag & 3)
1058 case 0: /* conforms, ie. bus-type dependent polarity */
1060 switch (mp_bus_id_to_type[bus])
1062 case MP_BUS_ISA: /* ISA pin */
1064 polarity = default_ISA_polarity(idx);
1067 case MP_BUS_EISA: /* EISA pin */
1069 polarity = default_EISA_polarity(idx);
1072 case MP_BUS_PCI: /* PCI pin */
1074 polarity = default_PCI_polarity(idx);
1077 case MP_BUS_MCA: /* MCA pin */
1079 polarity = default_MCA_polarity(idx);
1084 printk(KERN_WARNING "broken BIOS!!\n");
1091 case 1: /* high active */
1096 case 2: /* reserved */
1098 printk(KERN_WARNING "broken BIOS!!\n");
1102 case 3: /* low active */
1107 default: /* invalid */
1109 printk(KERN_WARNING "broken BIOS!!\n");
1117 static int MPBIOS_trigger(int idx)
1119 int bus = mp_irqs[idx].mpc_srcbus;
1123 * Determine IRQ trigger mode (edge or level sensitive):
1125 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1127 case 0: /* conforms, ie. bus-type dependent */
1129 switch (mp_bus_id_to_type[bus])
1131 case MP_BUS_ISA: /* ISA pin */
1133 trigger = default_ISA_trigger(idx);
1136 case MP_BUS_EISA: /* EISA pin */
1138 trigger = default_EISA_trigger(idx);
1141 case MP_BUS_PCI: /* PCI pin */
1143 trigger = default_PCI_trigger(idx);
1146 case MP_BUS_MCA: /* MCA pin */
1148 trigger = default_MCA_trigger(idx);
1153 printk(KERN_WARNING "broken BIOS!!\n");
1165 case 2: /* reserved */
1167 printk(KERN_WARNING "broken BIOS!!\n");
1176 default: /* invalid */
1178 printk(KERN_WARNING "broken BIOS!!\n");
1186 static inline int irq_polarity(int idx)
1188 return MPBIOS_polarity(idx);
1191 static inline int irq_trigger(int idx)
1193 return MPBIOS_trigger(idx);
1196 static int pin_2_irq(int idx, int apic, int pin)
1199 int bus = mp_irqs[idx].mpc_srcbus;
1202 * Debugging check, we are in big trouble if this message pops up!
1204 if (mp_irqs[idx].mpc_dstirq != pin)
1205 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1207 switch (mp_bus_id_to_type[bus])
1209 case MP_BUS_ISA: /* ISA pin */
1213 irq = mp_irqs[idx].mpc_srcbusirq;
1216 case MP_BUS_PCI: /* PCI pin */
1219 * PCI IRQs are mapped in order
1223 irq += nr_ioapic_registers[i++];
1227 * For MPS mode, so far only needed by ES7000 platform
1229 if (ioapic_renumber_irq)
1230 irq = ioapic_renumber_irq(apic, irq);
1236 printk(KERN_ERR "unknown bus type %d.\n",bus);
1243 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1245 if ((pin >= 16) && (pin <= 23)) {
1246 if (pirq_entries[pin-16] != -1) {
1247 if (!pirq_entries[pin-16]) {
1248 apic_printk(APIC_VERBOSE, KERN_DEBUG
1249 "disabling PIRQ%d\n", pin-16);
1251 irq = pirq_entries[pin-16];
1252 apic_printk(APIC_VERBOSE, KERN_DEBUG
1253 "using PIRQ%d -> IRQ %d\n",
1261 static inline int IO_APIC_irq_trigger(int irq)
1265 for (apic = 0; apic < nr_ioapics; apic++) {
1266 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1267 idx = find_irq_entry(apic,pin,mp_INT);
1268 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1269 return irq_trigger(idx);
1273 * nonexistent IRQs are edge default
1278 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1279 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly; /* = { FIRST_DEVICE_VECTOR , 0 }; */
1281 static int __assign_irq_vector(int irq)
1283 struct physdev_irq irq_op;
1286 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1288 if (irq_vector[irq] > 0)
1289 return irq_vector[irq];
1291 if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op))
1294 vector = irq_op.vector;
1295 irq_vector[irq] = vector;
1300 static int assign_irq_vector(int irq)
1302 unsigned long flags;
1305 spin_lock_irqsave(&vector_lock, flags);
1306 vector = __assign_irq_vector(irq);
1307 spin_unlock_irqrestore(&vector_lock, flags);
1312 static struct irq_chip ioapic_chip;
1314 #define IOAPIC_AUTO -1
1315 #define IOAPIC_EDGE 0
1316 #define IOAPIC_LEVEL 1
1318 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1320 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1321 trigger == IOAPIC_LEVEL)
1322 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1323 handle_fasteoi_irq, "fasteoi");
1325 irq_desc[irq].status |= IRQ_DELAYED_DISABLE;
1326 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1327 handle_edge_irq, "edge");
1329 set_intr_gate(vector, interrupt[irq]);
1332 #define ioapic_register_intr(_irq,_vector,_trigger) ((void)0)
1335 static void __init setup_IO_APIC_irqs(void)
1337 struct IO_APIC_route_entry entry;
1338 int apic, pin, idx, irq, first_notcon = 1, vector;
1339 unsigned long flags;
1341 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1343 for (apic = 0; apic < nr_ioapics; apic++) {
1344 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1347 * add it to the IO-APIC irq-routing table:
1349 memset(&entry,0,sizeof(entry));
1351 entry.delivery_mode = INT_DELIVERY_MODE;
1352 entry.dest_mode = INT_DEST_MODE;
1353 entry.mask = 0; /* enable IRQ */
1354 entry.dest.logical.logical_dest =
1355 cpu_mask_to_apicid(TARGET_CPUS);
1357 idx = find_irq_entry(apic,pin,mp_INT);
1360 apic_printk(APIC_VERBOSE, KERN_DEBUG
1361 " IO-APIC (apicid-pin) %d-%d",
1362 mp_ioapics[apic].mpc_apicid,
1366 apic_printk(APIC_VERBOSE, ", %d-%d",
1367 mp_ioapics[apic].mpc_apicid, pin);
1371 entry.trigger = irq_trigger(idx);
1372 entry.polarity = irq_polarity(idx);
1374 if (irq_trigger(idx)) {
1379 irq = pin_2_irq(idx, apic, pin);
1381 * skip adding the timer int on secondary nodes, which causes
1382 * a small but painful rift in the time-space continuum
1384 if (multi_timer_check(apic, irq))
1387 add_pin_to_irq(irq, apic, pin);
1389 if (/*!apic &&*/ !IO_APIC_IRQ(irq))
1392 if (IO_APIC_IRQ(irq)) {
1393 vector = assign_irq_vector(irq);
1394 entry.vector = vector;
1395 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1397 if (!apic && (irq < 16))
1398 disable_8259A_irq(irq);
1400 spin_lock_irqsave(&ioapic_lock, flags);
1401 __ioapic_write_entry(apic, pin, entry);
1402 set_native_irq_info(irq, TARGET_CPUS);
1403 spin_unlock_irqrestore(&ioapic_lock, flags);
1408 apic_printk(APIC_VERBOSE, " not connected.\n");
1412 * Set up the 8259A-master output pin:
1415 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1417 struct IO_APIC_route_entry entry;
1419 memset(&entry,0,sizeof(entry));
1421 disable_8259A_irq(0);
1424 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1427 * We use logical delivery to get the timer IRQ
1430 entry.dest_mode = INT_DEST_MODE;
1431 entry.mask = 0; /* unmask IRQ now */
1432 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1433 entry.delivery_mode = INT_DELIVERY_MODE;
1436 entry.vector = vector;
1439 * The timer IRQ doesn't have to know that behind the
1440 * scene we have a 8259A-master in AEOI mode ...
1442 irq_desc[0].chip = &ioapic_chip;
1443 set_irq_handler(0, handle_edge_irq);
1446 * Add it to the IO-APIC irq-routing table:
1448 ioapic_write_entry(apic, pin, entry);
1450 enable_8259A_irq(0);
1453 static inline void UNEXPECTED_IO_APIC(void)
1457 void __init print_IO_APIC(void)
1460 union IO_APIC_reg_00 reg_00;
1461 union IO_APIC_reg_01 reg_01;
1462 union IO_APIC_reg_02 reg_02;
1463 union IO_APIC_reg_03 reg_03;
1464 unsigned long flags;
1466 if (apic_verbosity == APIC_QUIET)
1469 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1470 for (i = 0; i < nr_ioapics; i++)
1471 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1472 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1475 * We are a bit conservative about what we expect. We have to
1476 * know about every hardware change ASAP.
1478 printk(KERN_INFO "testing the IO APIC.......................\n");
1480 for (apic = 0; apic < nr_ioapics; apic++) {
1482 spin_lock_irqsave(&ioapic_lock, flags);
1483 reg_00.raw = io_apic_read(apic, 0);
1484 reg_01.raw = io_apic_read(apic, 1);
1485 if (reg_01.bits.version >= 0x10)
1486 reg_02.raw = io_apic_read(apic, 2);
1487 if (reg_01.bits.version >= 0x20)
1488 reg_03.raw = io_apic_read(apic, 3);
1489 spin_unlock_irqrestore(&ioapic_lock, flags);
1491 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1492 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1493 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1494 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1495 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1496 if (reg_00.bits.ID >= get_physical_broadcast())
1497 UNEXPECTED_IO_APIC();
1498 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1499 UNEXPECTED_IO_APIC();
1501 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1502 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1503 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1504 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1505 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1506 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1507 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1508 (reg_01.bits.entries != 0x2E) &&
1509 (reg_01.bits.entries != 0x3F)
1511 UNEXPECTED_IO_APIC();
1513 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1514 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1515 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1516 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1517 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1518 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1519 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1521 UNEXPECTED_IO_APIC();
1522 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1523 UNEXPECTED_IO_APIC();
1526 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1527 * but the value of reg_02 is read as the previous read register
1528 * value, so ignore it if reg_02 == reg_01.
1530 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1531 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1532 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1533 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1534 UNEXPECTED_IO_APIC();
1538 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1539 * or reg_03, but the value of reg_0[23] is read as the previous read
1540 * register value, so ignore it if reg_03 == reg_0[12].
1542 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1543 reg_03.raw != reg_01.raw) {
1544 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1545 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1546 if (reg_03.bits.__reserved_1)
1547 UNEXPECTED_IO_APIC();
1550 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1552 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1553 " Stat Dest Deli Vect: \n");
1555 for (i = 0; i <= reg_01.bits.entries; i++) {
1556 struct IO_APIC_route_entry entry;
1558 entry = ioapic_read_entry(apic, i);
1560 printk(KERN_DEBUG " %02x %03X %02X ",
1562 entry.dest.logical.logical_dest,
1563 entry.dest.physical.physical_dest
1566 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1571 entry.delivery_status,
1573 entry.delivery_mode,
1578 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1579 for (i = 0; i < NR_IRQS; i++) {
1580 struct irq_pin_list *entry = irq_2_pin + i;
1583 printk(KERN_DEBUG "IRQ%d ", i);
1585 printk("-> %d:%d", entry->apic, entry->pin);
1588 entry = irq_2_pin + entry->next;
1593 printk(KERN_INFO ".................................... done.\n");
1600 static void print_APIC_bitfield (int base)
1605 if (apic_verbosity == APIC_QUIET)
1608 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1609 for (i = 0; i < 8; i++) {
1610 v = apic_read(base + i*0x10);
1611 for (j = 0; j < 32; j++) {
1621 void /*__init*/ print_local_APIC(void * dummy)
1623 unsigned int v, ver, maxlvt;
1625 if (apic_verbosity == APIC_QUIET)
1628 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1629 smp_processor_id(), hard_smp_processor_id());
1630 v = apic_read(APIC_ID);
1631 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1632 v = apic_read(APIC_LVR);
1633 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1634 ver = GET_APIC_VERSION(v);
1635 maxlvt = get_maxlvt();
1637 v = apic_read(APIC_TASKPRI);
1638 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1640 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1641 v = apic_read(APIC_ARBPRI);
1642 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1643 v & APIC_ARBPRI_MASK);
1644 v = apic_read(APIC_PROCPRI);
1645 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1648 v = apic_read(APIC_EOI);
1649 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1650 v = apic_read(APIC_RRR);
1651 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1652 v = apic_read(APIC_LDR);
1653 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1654 v = apic_read(APIC_DFR);
1655 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1656 v = apic_read(APIC_SPIV);
1657 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1659 printk(KERN_DEBUG "... APIC ISR field:\n");
1660 print_APIC_bitfield(APIC_ISR);
1661 printk(KERN_DEBUG "... APIC TMR field:\n");
1662 print_APIC_bitfield(APIC_TMR);
1663 printk(KERN_DEBUG "... APIC IRR field:\n");
1664 print_APIC_bitfield(APIC_IRR);
1666 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1667 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1668 apic_write(APIC_ESR, 0);
1669 v = apic_read(APIC_ESR);
1670 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1673 v = apic_read(APIC_ICR);
1674 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1675 v = apic_read(APIC_ICR2);
1676 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1678 v = apic_read(APIC_LVTT);
1679 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1681 if (maxlvt > 3) { /* PC is LVT#4. */
1682 v = apic_read(APIC_LVTPC);
1683 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1685 v = apic_read(APIC_LVT0);
1686 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1687 v = apic_read(APIC_LVT1);
1688 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1690 if (maxlvt > 2) { /* ERR is LVT#3. */
1691 v = apic_read(APIC_LVTERR);
1692 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1695 v = apic_read(APIC_TMICT);
1696 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1697 v = apic_read(APIC_TMCCT);
1698 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1699 v = apic_read(APIC_TDCR);
1700 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1704 void print_all_local_APICs (void)
1706 on_each_cpu(print_local_APIC, NULL, 1, 1);
1709 void /*__init*/ print_PIC(void)
1712 unsigned long flags;
1714 if (apic_verbosity == APIC_QUIET)
1717 printk(KERN_DEBUG "\nprinting PIC contents\n");
1719 spin_lock_irqsave(&i8259A_lock, flags);
1721 v = inb(0xa1) << 8 | inb(0x21);
1722 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1724 v = inb(0xa0) << 8 | inb(0x20);
1725 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1729 v = inb(0xa0) << 8 | inb(0x20);
1733 spin_unlock_irqrestore(&i8259A_lock, flags);
1735 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1737 v = inb(0x4d1) << 8 | inb(0x4d0);
1738 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1744 void __init print_IO_APIC(void) { }
1745 #endif /* !CONFIG_XEN */
1747 static void __init enable_IO_APIC(void)
1749 union IO_APIC_reg_01 reg_01;
1750 int i8259_apic, i8259_pin;
1752 unsigned long flags;
1754 for (i = 0; i < PIN_MAP_SIZE; i++) {
1755 irq_2_pin[i].pin = -1;
1756 irq_2_pin[i].next = 0;
1759 for (i = 0; i < MAX_PIRQS; i++)
1760 pirq_entries[i] = -1;
1763 * The number of IO-APIC IRQ registers (== #pins):
1765 for (apic = 0; apic < nr_ioapics; apic++) {
1766 spin_lock_irqsave(&ioapic_lock, flags);
1767 reg_01.raw = io_apic_read(apic, 1);
1768 spin_unlock_irqrestore(&ioapic_lock, flags);
1769 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1771 for(apic = 0; apic < nr_ioapics; apic++) {
1773 /* See if any of the pins is in ExtINT mode */
1774 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1775 struct IO_APIC_route_entry entry;
1776 entry = ioapic_read_entry(apic, pin);
1779 /* If the interrupt line is enabled and in ExtInt mode
1780 * I have found the pin where the i8259 is connected.
1782 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1783 ioapic_i8259.apic = apic;
1784 ioapic_i8259.pin = pin;
1790 /* Look to see what if the MP table has reported the ExtINT */
1791 /* If we could not find the appropriate pin by looking at the ioapic
1792 * the i8259 probably is not connected the ioapic but give the
1793 * mptable a chance anyway.
1795 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1796 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1797 /* Trust the MP table if nothing is setup in the hardware */
1798 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1799 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1800 ioapic_i8259.pin = i8259_pin;
1801 ioapic_i8259.apic = i8259_apic;
1803 /* Complain if the MP table and the hardware disagree */
1804 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1805 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1807 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1811 * Do not trust the IO-APIC being empty at bootup
1817 * Not an __init, needed by the reboot code
1819 void disable_IO_APIC(void)
1822 * Clear the IO-APIC before rebooting:
1828 * If the i8259 is routed through an IOAPIC
1829 * Put that IOAPIC in virtual wire mode
1830 * so legacy interrupts can be delivered.
1832 if (ioapic_i8259.pin != -1) {
1833 struct IO_APIC_route_entry entry;
1835 memset(&entry, 0, sizeof(entry));
1836 entry.mask = 0; /* Enabled */
1837 entry.trigger = 0; /* Edge */
1839 entry.polarity = 0; /* High */
1840 entry.delivery_status = 0;
1841 entry.dest_mode = 0; /* Physical */
1842 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1844 entry.dest.physical.physical_dest =
1845 GET_APIC_ID(apic_read(APIC_ID));
1848 * Add it to the IO-APIC irq-routing table:
1850 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1852 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1857 * function to set the IO-APIC physical IDs based on the
1858 * values stored in the MPC table.
1860 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1863 #if !defined(CONFIG_XEN) && !defined(CONFIG_X86_NUMAQ)
1864 static void __init setup_ioapic_ids_from_mpc(void)
1866 union IO_APIC_reg_00 reg_00;
1867 physid_mask_t phys_id_present_map;
1870 unsigned char old_id;
1871 unsigned long flags;
1874 * Don't check I/O APIC IDs for xAPIC systems. They have
1875 * no meaning without the serial APIC bus.
1877 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1878 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1881 * This is broken; anything with a real cpu count has to
1882 * circumvent this idiocy regardless.
1884 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1887 * Set the IOAPIC ID to the value stored in the MPC table.
1889 for (apic = 0; apic < nr_ioapics; apic++) {
1891 /* Read the register 0 value */
1892 spin_lock_irqsave(&ioapic_lock, flags);
1893 reg_00.raw = io_apic_read(apic, 0);
1894 spin_unlock_irqrestore(&ioapic_lock, flags);
1896 old_id = mp_ioapics[apic].mpc_apicid;
1898 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1899 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1900 apic, mp_ioapics[apic].mpc_apicid);
1901 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1903 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1907 * Sanity check, is the ID really free? Every APIC in a
1908 * system must have a unique ID or we get lots of nice
1909 * 'stuck on smp_invalidate_needed IPI wait' messages.
1911 if (check_apicid_used(phys_id_present_map,
1912 mp_ioapics[apic].mpc_apicid)) {
1913 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1914 apic, mp_ioapics[apic].mpc_apicid);
1915 for (i = 0; i < get_physical_broadcast(); i++)
1916 if (!physid_isset(i, phys_id_present_map))
1918 if (i >= get_physical_broadcast())
1919 panic("Max APIC ID exceeded!\n");
1920 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1922 physid_set(i, phys_id_present_map);
1923 mp_ioapics[apic].mpc_apicid = i;
1926 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1927 apic_printk(APIC_VERBOSE, "Setting %d in the "
1928 "phys_id_present_map\n",
1929 mp_ioapics[apic].mpc_apicid);
1930 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1935 * We need to adjust the IRQ routing table
1936 * if the ID changed.
1938 if (old_id != mp_ioapics[apic].mpc_apicid)
1939 for (i = 0; i < mp_irq_entries; i++)
1940 if (mp_irqs[i].mpc_dstapic == old_id)
1941 mp_irqs[i].mpc_dstapic
1942 = mp_ioapics[apic].mpc_apicid;
1945 * Read the right value from the MPC table and
1946 * write it into the ID register.
1948 apic_printk(APIC_VERBOSE, KERN_INFO
1949 "...changing IO-APIC physical APIC ID to %d ...",
1950 mp_ioapics[apic].mpc_apicid);
1952 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1953 spin_lock_irqsave(&ioapic_lock, flags);
1954 io_apic_write(apic, 0, reg_00.raw);
1955 spin_unlock_irqrestore(&ioapic_lock, flags);
1960 spin_lock_irqsave(&ioapic_lock, flags);
1961 reg_00.raw = io_apic_read(apic, 0);
1962 spin_unlock_irqrestore(&ioapic_lock, flags);
1963 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1964 printk("could not set ID!\n");
1966 apic_printk(APIC_VERBOSE, " ok.\n");
1970 static void __init setup_ioapic_ids_from_mpc(void) { }
1973 static int no_timer_check __initdata;
1975 static int __init notimercheck(char *s)
1980 __setup("no_timer_check", notimercheck);
1984 * There is a nasty bug in some older SMP boards, their mptable lies
1985 * about the timer IRQ. We do the following to work around the situation:
1987 * - timer IRQ defaults to IO-APIC IRQ
1988 * - if this function detects that timer IRQs are defunct, then we fall
1989 * back to ISA timer IRQs
1991 int __init timer_irq_works(void)
1993 unsigned long t1 = jiffies;
1999 /* Let ten ticks pass... */
2000 mdelay((10 * 1000) / HZ);
2003 * Expect a few ticks at least, to be sure some possible
2004 * glue logic does not lock up after one or two first
2005 * ticks in a non-ExtINT mode. Also the local APIC
2006 * might have cached one ExtINT interrupt. Finally, at
2007 * least one tick may be lost due to delays.
2009 if (jiffies - t1 > 4)
2016 * In the SMP+IOAPIC case it might happen that there are an unspecified
2017 * number of pending IRQ events unhandled. These cases are very rare,
2018 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2019 * better to do it this way as thus we do not have to be aware of
2020 * 'pending' interrupts in the IRQ path, except at this point.
2023 * Edge triggered needs to resend any interrupt
2024 * that was delayed but this is now handled in the device
2031 * Starting up a edge-triggered IO-APIC interrupt is
2032 * nasty - we need to make sure that we get the edge.
2033 * If it is already asserted for some reason, we need
2034 * return 1 to indicate that is was pending.
2036 * This is not complete - we should be able to fake
2037 * an edge even if it isn't on the 8259A...
2039 * (We do this for level-triggered IRQs too - it cannot hurt.)
2041 static unsigned int startup_ioapic_irq(unsigned int irq)
2043 int was_pending = 0;
2044 unsigned long flags;
2046 spin_lock_irqsave(&ioapic_lock, flags);
2048 disable_8259A_irq(irq);
2049 if (i8259A_irq_pending(irq))
2052 __unmask_IO_APIC_irq(irq);
2053 spin_unlock_irqrestore(&ioapic_lock, flags);
2058 static void ack_ioapic_irq(unsigned int irq)
2060 move_native_irq(irq);
2064 static void ack_ioapic_quirk_irq(unsigned int irq)
2069 move_native_irq(irq);
2071 * It appears there is an erratum which affects at least version 0x11
2072 * of I/O APIC (that's the 82093AA and cores integrated into various
2073 * chipsets). Under certain conditions a level-triggered interrupt is
2074 * erroneously delivered as edge-triggered one but the respective IRR
2075 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2076 * message but it will never arrive and further interrupts are blocked
2077 * from the source. The exact reason is so far unknown, but the
2078 * phenomenon was observed when two consecutive interrupt requests
2079 * from a given source get delivered to the same CPU and the source is
2080 * temporarily disabled in between.
2082 * A workaround is to simulate an EOI message manually. We achieve it
2083 * by setting the trigger mode to edge and then to level when the edge
2084 * trigger mode gets detected in the TMR of a local APIC for a
2085 * level-triggered interrupt. We mask the source for the time of the
2086 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2087 * The idea is from Manfred Spraul. --macro
2089 i = irq_vector[irq];
2091 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2095 if (!(v & (1 << (i & 0x1f)))) {
2096 atomic_inc(&irq_mis_count);
2097 spin_lock(&ioapic_lock);
2098 __mask_and_edge_IO_APIC_irq(irq);
2099 __unmask_and_level_IO_APIC_irq(irq);
2100 spin_unlock(&ioapic_lock);
2104 static int ioapic_retrigger_irq(unsigned int irq)
2106 send_IPI_self(irq_vector[irq]);
2111 static struct irq_chip ioapic_chip __read_mostly = {
2113 .startup = startup_ioapic_irq,
2114 .mask = mask_IO_APIC_irq,
2115 .unmask = unmask_IO_APIC_irq,
2116 .ack = ack_ioapic_irq,
2117 .eoi = ack_ioapic_quirk_irq,
2119 .set_affinity = set_ioapic_affinity_irq,
2121 .retrigger = ioapic_retrigger_irq,
2124 #endif /* !CONFIG_XEN */
2126 static inline void init_IO_APIC_traps(void)
2131 * NOTE! The local APIC isn't very good at handling
2132 * multiple interrupts at the same interrupt level.
2133 * As the interrupt level is determined by taking the
2134 * vector number and shifting that right by 4, we
2135 * want to spread these out a bit so that they don't
2136 * all fall in the same interrupt level.
2138 * Also, we've got to be careful not to trash gate
2139 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2141 for (irq = 0; irq < NR_IRQS ; irq++) {
2143 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
2145 * Hmm.. We don't have an entry for this,
2146 * so default to an old-fashioned 8259
2147 * interrupt if we can..
2150 make_8259A_irq(irq);
2153 /* Strange. Oh, well.. */
2154 irq_desc[irq].chip = &no_irq_chip;
2162 * The local APIC irq-chip implementation:
2165 static void ack_apic(unsigned int irq)
2170 static void mask_lapic_irq (unsigned int irq)
2174 v = apic_read(APIC_LVT0);
2175 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2178 static void unmask_lapic_irq (unsigned int irq)
2182 v = apic_read(APIC_LVT0);
2183 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2186 static struct irq_chip lapic_chip __read_mostly = {
2187 .name = "local-APIC-edge",
2188 .mask = mask_lapic_irq,
2189 .unmask = unmask_lapic_irq,
2193 static void setup_nmi (void)
2196 * Dirty trick to enable the NMI watchdog ...
2197 * We put the 8259A master into AEOI mode and
2198 * unmask on all local APICs LVT0 as NMI.
2200 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2201 * is from Maciej W. Rozycki - so we do not have to EOI from
2202 * the NMI handler or the timer interrupt.
2204 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2206 on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2208 apic_printk(APIC_VERBOSE, " done.\n");
2212 * This looks a bit hackish but it's about the only one way of sending
2213 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2214 * not support the ExtINT mode, unfortunately. We need to send these
2215 * cycles as some i82489DX-based boards have glue logic that keeps the
2216 * 8259A interrupt line asserted until INTA. --macro
2218 static inline void unlock_ExtINT_logic(void)
2221 struct IO_APIC_route_entry entry0, entry1;
2222 unsigned char save_control, save_freq_select;
2224 pin = find_isa_irq_pin(8, mp_INT);
2229 apic = find_isa_irq_apic(8, mp_INT);
2235 entry0 = ioapic_read_entry(apic, pin);
2236 clear_IO_APIC_pin(apic, pin);
2238 memset(&entry1, 0, sizeof(entry1));
2240 entry1.dest_mode = 0; /* physical delivery */
2241 entry1.mask = 0; /* unmask IRQ now */
2242 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2243 entry1.delivery_mode = dest_ExtINT;
2244 entry1.polarity = entry0.polarity;
2248 ioapic_write_entry(apic, pin, entry1);
2250 save_control = CMOS_READ(RTC_CONTROL);
2251 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2252 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2254 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2259 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2263 CMOS_WRITE(save_control, RTC_CONTROL);
2264 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2265 clear_IO_APIC_pin(apic, pin);
2267 ioapic_write_entry(apic, pin, entry0);
2269 #endif /* !CONFIG_XEN */
2271 int timer_uses_ioapic_pin_0;
2275 * This code may look a bit paranoid, but it's supposed to cooperate with
2276 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2277 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2278 * fanatically on his truly buggy board.
2280 static inline void __init check_timer(void)
2282 int apic1, pin1, apic2, pin2;
2286 * get/set the timer IRQ vector:
2288 disable_8259A_irq(0);
2289 vector = assign_irq_vector(0);
2290 set_intr_gate(vector, interrupt[0]);
2293 * Subtle, code in do_timer_interrupt() expects an AEOI
2294 * mode for the 8259A whenever interrupts are routed
2295 * through I/O APICs. Also IRQ0 has to be enabled in
2296 * the 8259A which implies the virtual wire has to be
2297 * disabled in the local APIC.
2299 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2302 if (timer_over_8254 > 0)
2303 enable_8259A_irq(0);
2305 pin1 = find_isa_irq_pin(0, mp_INT);
2306 apic1 = find_isa_irq_apic(0, mp_INT);
2307 pin2 = ioapic_i8259.pin;
2308 apic2 = ioapic_i8259.apic;
2311 timer_uses_ioapic_pin_0 = 1;
2313 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2314 vector, apic1, pin1, apic2, pin2);
2318 * Ok, does IRQ0 through the IOAPIC work?
2320 unmask_IO_APIC_irq(0);
2321 if (timer_irq_works()) {
2322 if (nmi_watchdog == NMI_IO_APIC) {
2323 disable_8259A_irq(0);
2325 enable_8259A_irq(0);
2327 if (disable_timer_pin_1 > 0)
2328 clear_IO_APIC_pin(0, pin1);
2331 clear_IO_APIC_pin(apic1, pin1);
2332 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2336 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2338 printk("\n..... (found pin %d) ...", pin2);
2340 * legacy devices should be connected to IO APIC #0
2342 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2343 if (timer_irq_works()) {
2346 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2348 add_pin_to_irq(0, apic2, pin2);
2349 if (nmi_watchdog == NMI_IO_APIC) {
2355 * Cleanup, just in case ...
2357 clear_IO_APIC_pin(apic2, pin2);
2359 printk(" failed.\n");
2361 if (nmi_watchdog == NMI_IO_APIC) {
2362 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2366 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2368 disable_8259A_irq(0);
2369 set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2371 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2372 enable_8259A_irq(0);
2374 if (timer_irq_works()) {
2375 printk(" works.\n");
2378 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2379 printk(" failed.\n");
2381 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2386 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2388 unlock_ExtINT_logic();
2390 if (timer_irq_works()) {
2391 printk(" works.\n");
2394 printk(" failed :(.\n");
2395 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2396 "report. Then try booting with the 'noapic' option");
2399 #define check_timer() ((void)0)
2400 #endif /* CONFIG_XEN */
2404 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2405 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2406 * Linux doesn't really care, as it's not actually used
2407 * for any interrupt handling anyway.
2409 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2411 void __init setup_IO_APIC(void)
2416 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2418 io_apic_irqs = ~PIC_IRQS;
2420 printk("ENABLING IO-APIC IRQs\n");
2423 * Set up IO-APIC IRQ routing.
2426 setup_ioapic_ids_from_mpc();
2430 setup_IO_APIC_irqs();
2431 init_IO_APIC_traps();
2437 static int __init setup_disable_8254_timer(char *s)
2439 timer_over_8254 = -1;
2442 static int __init setup_enable_8254_timer(char *s)
2444 timer_over_8254 = 2;
2448 __setup("disable_8254_timer", setup_disable_8254_timer);
2449 __setup("enable_8254_timer", setup_enable_8254_timer);
2452 * Called after all the initialization is done. If we didnt find any
2453 * APIC bugs then we can allow the modify fast path
2456 static int __init io_apic_bug_finalize(void)
2458 if(sis_apic_bug == -1)
2460 if (is_initial_xendomain()) {
2461 dom0_op_t op = { .cmd = DOM0_PLATFORM_QUIRK };
2462 op.u.platform_quirk.quirk_id = sis_apic_bug ?
2463 QUIRK_IOAPIC_BAD_REGSEL : QUIRK_IOAPIC_GOOD_REGSEL;
2464 HYPERVISOR_dom0_op(&op);
2469 late_initcall(io_apic_bug_finalize);
2471 struct sysfs_ioapic_data {
2472 struct sys_device dev;
2473 struct IO_APIC_route_entry entry[0];
2475 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2477 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2479 struct IO_APIC_route_entry *entry;
2480 struct sysfs_ioapic_data *data;
2483 data = container_of(dev, struct sysfs_ioapic_data, dev);
2484 entry = data->entry;
2485 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2486 entry[i] = ioapic_read_entry(dev->id, i);
2491 static int ioapic_resume(struct sys_device *dev)
2493 struct IO_APIC_route_entry *entry;
2494 struct sysfs_ioapic_data *data;
2495 unsigned long flags;
2496 union IO_APIC_reg_00 reg_00;
2499 data = container_of(dev, struct sysfs_ioapic_data, dev);
2500 entry = data->entry;
2502 spin_lock_irqsave(&ioapic_lock, flags);
2503 reg_00.raw = io_apic_read(dev->id, 0);
2504 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2505 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2506 io_apic_write(dev->id, 0, reg_00.raw);
2508 spin_unlock_irqrestore(&ioapic_lock, flags);
2509 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2510 ioapic_write_entry(dev->id, i, entry[i]);
2515 static struct sysdev_class ioapic_sysdev_class = {
2516 set_kset_name("ioapic"),
2517 .suspend = ioapic_suspend,
2518 .resume = ioapic_resume,
2521 static int __init ioapic_init_sysfs(void)
2523 struct sys_device * dev;
2524 int i, size, error = 0;
2526 error = sysdev_class_register(&ioapic_sysdev_class);
2530 for (i = 0; i < nr_ioapics; i++ ) {
2531 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2532 * sizeof(struct IO_APIC_route_entry);
2533 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2534 if (!mp_ioapic_data[i]) {
2535 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2538 memset(mp_ioapic_data[i], 0, size);
2539 dev = &mp_ioapic_data[i]->dev;
2541 dev->cls = &ioapic_sysdev_class;
2542 error = sysdev_register(dev);
2544 kfree(mp_ioapic_data[i]);
2545 mp_ioapic_data[i] = NULL;
2546 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2554 device_initcall(ioapic_init_sysfs);
2557 * Dynamic irq allocate and deallocation
2559 int create_irq(void)
2561 /* Allocate an unused irq */
2562 int irq, new, vector = 0;
2563 unsigned long flags;
2566 spin_lock_irqsave(&vector_lock, flags);
2567 for (new = (NR_IRQS - 1); new >= 0; new--) {
2568 if (platform_legacy_irq(new))
2570 if (irq_vector[new] != 0)
2572 vector = __assign_irq_vector(new);
2573 if (likely(vector > 0))
2577 spin_unlock_irqrestore(&vector_lock, flags);
2581 set_intr_gate(vector, interrupt[irq]);
2583 dynamic_irq_init(irq);
2588 void destroy_irq(unsigned int irq)
2590 unsigned long flags;
2592 dynamic_irq_cleanup(irq);
2594 spin_lock_irqsave(&vector_lock, flags);
2595 irq_vector[irq] = 0;
2596 spin_unlock_irqrestore(&vector_lock, flags);
2600 * MSI mesage composition
2602 #ifdef CONFIG_PCI_MSI
2603 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2608 vector = assign_irq_vector(irq);
2610 dest = cpu_mask_to_apicid(TARGET_CPUS);
2612 msg->address_hi = MSI_ADDR_BASE_HI;
2615 ((INT_DEST_MODE == 0) ?
2616 MSI_ADDR_DEST_MODE_PHYSICAL:
2617 MSI_ADDR_DEST_MODE_LOGICAL) |
2618 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2619 MSI_ADDR_REDIRECTION_CPU:
2620 MSI_ADDR_REDIRECTION_LOWPRI) |
2621 MSI_ADDR_DEST_ID(dest);
2624 MSI_DATA_TRIGGER_EDGE |
2625 MSI_DATA_LEVEL_ASSERT |
2626 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2627 MSI_DATA_DELIVERY_FIXED:
2628 MSI_DATA_DELIVERY_LOWPRI) |
2629 MSI_DATA_VECTOR(vector);
2635 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2642 cpus_and(tmp, mask, cpu_online_map);
2643 if (cpus_empty(tmp))
2646 vector = assign_irq_vector(irq);
2650 dest = cpu_mask_to_apicid(mask);
2652 read_msi_msg(irq, &msg);
2654 msg.data &= ~MSI_DATA_VECTOR_MASK;
2655 msg.data |= MSI_DATA_VECTOR(vector);
2656 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2657 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2659 write_msi_msg(irq, &msg);
2660 set_native_irq_info(irq, mask);
2662 #endif /* CONFIG_SMP */
2665 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2666 * which implement the MSI or MSI-X Capability Structure.
2668 static struct irq_chip msi_chip = {
2670 .unmask = unmask_msi_irq,
2671 .mask = mask_msi_irq,
2672 .ack = ack_ioapic_irq,
2674 .set_affinity = set_msi_irq_affinity,
2676 .retrigger = ioapic_retrigger_irq,
2679 int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev)
2683 ret = msi_compose_msg(dev, irq, &msg);
2687 write_msi_msg(irq, &msg);
2689 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2695 void arch_teardown_msi_irq(unsigned int irq)
2700 #endif /* CONFIG_PCI_MSI */
2703 * Hypertransport interrupt support
2705 #ifdef CONFIG_HT_IRQ
2709 static void target_ht_irq(unsigned int irq, unsigned int dest)
2711 struct ht_irq_msg msg;
2712 fetch_ht_irq_msg(irq, &msg);
2714 msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2715 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2717 msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2718 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2720 write_ht_irq_msg(irq, &msg);
2723 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2728 cpus_and(tmp, mask, cpu_online_map);
2729 if (cpus_empty(tmp))
2732 cpus_and(mask, tmp, CPU_MASK_ALL);
2734 dest = cpu_mask_to_apicid(mask);
2736 target_ht_irq(irq, dest);
2737 set_native_irq_info(irq, mask);
2741 static struct irq_chip ht_irq_chip = {
2743 .mask = mask_ht_irq,
2744 .unmask = unmask_ht_irq,
2745 .ack = ack_ioapic_irq,
2747 .set_affinity = set_ht_irq_affinity,
2749 .retrigger = ioapic_retrigger_irq,
2752 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2756 vector = assign_irq_vector(irq);
2758 struct ht_irq_msg msg;
2763 cpu_set(vector >> 8, tmp);
2764 dest = cpu_mask_to_apicid(tmp);
2766 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2770 HT_IRQ_LOW_DEST_ID(dest) |
2771 HT_IRQ_LOW_VECTOR(vector) |
2772 ((INT_DEST_MODE == 0) ?
2773 HT_IRQ_LOW_DM_PHYSICAL :
2774 HT_IRQ_LOW_DM_LOGICAL) |
2775 HT_IRQ_LOW_RQEOI_EDGE |
2776 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2777 HT_IRQ_LOW_MT_FIXED :
2778 HT_IRQ_LOW_MT_ARBITRATED) |
2779 HT_IRQ_LOW_IRQ_MASKED;
2781 write_ht_irq_msg(irq, &msg);
2783 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2784 handle_edge_irq, "edge");
2788 #endif /* CONFIG_HT_IRQ */
2790 /* --------------------------------------------------------------------------
2791 ACPI-based IOAPIC Configuration
2792 -------------------------------------------------------------------------- */
2796 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2799 union IO_APIC_reg_00 reg_00;
2800 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2802 unsigned long flags;
2806 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2807 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2808 * supports up to 16 on one shared APIC bus.
2810 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2811 * advantage of new APIC bus architecture.
2814 if (physids_empty(apic_id_map))
2815 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2817 spin_lock_irqsave(&ioapic_lock, flags);
2818 reg_00.raw = io_apic_read(ioapic, 0);
2819 spin_unlock_irqrestore(&ioapic_lock, flags);
2821 if (apic_id >= get_physical_broadcast()) {
2822 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2823 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2824 apic_id = reg_00.bits.ID;
2828 * Every APIC in a system must have a unique ID or we get lots of nice
2829 * 'stuck on smp_invalidate_needed IPI wait' messages.
2831 if (check_apicid_used(apic_id_map, apic_id)) {
2833 for (i = 0; i < get_physical_broadcast(); i++) {
2834 if (!check_apicid_used(apic_id_map, i))
2838 if (i == get_physical_broadcast())
2839 panic("Max apic_id exceeded!\n");
2841 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2842 "trying %d\n", ioapic, apic_id, i);
2847 tmp = apicid_to_cpu_present(apic_id);
2848 physids_or(apic_id_map, apic_id_map, tmp);
2850 if (reg_00.bits.ID != apic_id) {
2851 reg_00.bits.ID = apic_id;
2853 spin_lock_irqsave(&ioapic_lock, flags);
2854 io_apic_write(ioapic, 0, reg_00.raw);
2855 reg_00.raw = io_apic_read(ioapic, 0);
2856 spin_unlock_irqrestore(&ioapic_lock, flags);
2859 if (reg_00.bits.ID != apic_id) {
2860 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2865 apic_printk(APIC_VERBOSE, KERN_INFO
2866 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2867 #endif /* !CONFIG_XEN */
2873 int __init io_apic_get_version (int ioapic)
2875 union IO_APIC_reg_01 reg_01;
2876 unsigned long flags;
2878 spin_lock_irqsave(&ioapic_lock, flags);
2879 reg_01.raw = io_apic_read(ioapic, 1);
2880 spin_unlock_irqrestore(&ioapic_lock, flags);
2882 return reg_01.bits.version;
2886 int __init io_apic_get_redir_entries (int ioapic)
2888 union IO_APIC_reg_01 reg_01;
2889 unsigned long flags;
2891 spin_lock_irqsave(&ioapic_lock, flags);
2892 reg_01.raw = io_apic_read(ioapic, 1);
2893 spin_unlock_irqrestore(&ioapic_lock, flags);
2895 return reg_01.bits.entries;
2899 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2901 struct IO_APIC_route_entry entry;
2902 unsigned long flags;
2904 if (!IO_APIC_IRQ(irq)) {
2905 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2911 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2912 * Note that we mask (disable) IRQs now -- these get enabled when the
2913 * corresponding device driver registers for this IRQ.
2916 memset(&entry,0,sizeof(entry));
2918 entry.delivery_mode = INT_DELIVERY_MODE;
2919 entry.dest_mode = INT_DEST_MODE;
2920 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2921 entry.trigger = edge_level;
2922 entry.polarity = active_high_low;
2926 * IRQs < 16 are already in the irq_2_pin[] map
2929 add_pin_to_irq(irq, ioapic, pin);
2931 entry.vector = assign_irq_vector(irq);
2933 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2934 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2935 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2936 edge_level, active_high_low);
2938 ioapic_register_intr(irq, entry.vector, edge_level);
2940 if (!ioapic && (irq < 16))
2941 disable_8259A_irq(irq);
2943 spin_lock_irqsave(&ioapic_lock, flags);
2944 __ioapic_write_entry(ioapic, pin, entry);
2945 set_native_irq_info(irq, TARGET_CPUS);
2946 spin_unlock_irqrestore(&ioapic_lock, flags);
2951 #endif /* CONFIG_ACPI */
2953 static int __init parse_disable_timer_pin_1(char *arg)
2955 disable_timer_pin_1 = 1;
2958 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2960 static int __init parse_enable_timer_pin_1(char *arg)
2962 disable_timer_pin_1 = -1;
2965 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2967 static int __init parse_noapic(char *arg)
2969 /* disable IO-APIC */
2970 disable_ioapic_setup();
2973 early_param("noapic", parse_noapic);