2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/config.h>
30 #include <linux/smp_lock.h>
31 #include <linux/mc146818rtc.h>
32 #include <linux/compiler.h>
33 #include <linux/acpi.h>
35 #include <linux/sysdev.h>
39 #include <asm/timer.h>
41 #include <mach_apic.h>
45 int (*ioapic_renumber_irq)(int ioapic, int irq);
46 atomic_t irq_mis_count;
48 static DEFINE_SPINLOCK(ioapic_lock);
51 * Is the SiS APIC rmw bug present ?
52 * -1 = don't know, 0 = no, 1 = yes
54 int sis_apic_bug = -1;
57 * # of IRQ routing registers
59 int nr_ioapic_registers[MAX_IO_APICS];
62 * Rough estimation of how many shared IRQs there are, can
65 #define MAX_PLUS_SHARED_IRQS NR_IRQS
66 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
69 * This is performance-critical, we want to do it O(1)
71 * the indexing order of this array favors 1:1 mappings
72 * between pins and IRQs.
75 static struct irq_pin_list {
77 } irq_2_pin[PIN_MAP_SIZE];
79 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
81 #define vector_to_irq(vector) \
82 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
84 #define vector_to_irq(vector) (vector)
88 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
89 * shared ISA-space IRQs, so we have to support them. We are super
90 * fast in the common case, and fast for shared ISA-space IRQs.
92 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
94 static int first_free_entry = NR_IRQS;
95 struct irq_pin_list *entry = irq_2_pin + irq;
98 entry = irq_2_pin + entry->next;
100 if (entry->pin != -1) {
101 entry->next = first_free_entry;
102 entry = irq_2_pin + entry->next;
103 if (++first_free_entry >= PIN_MAP_SIZE)
104 panic("io_apic.c: whoops");
111 * Reroute an IRQ to a different pin.
113 static void __init replace_pin_at_irq(unsigned int irq,
114 int oldapic, int oldpin,
115 int newapic, int newpin)
117 struct irq_pin_list *entry = irq_2_pin + irq;
120 if (entry->apic == oldapic && entry->pin == oldpin) {
121 entry->apic = newapic;
126 entry = irq_2_pin + entry->next;
130 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
132 struct irq_pin_list *entry = irq_2_pin + irq;
133 unsigned int pin, reg;
139 reg = io_apic_read(entry->apic, 0x10 + pin*2);
142 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
145 entry = irq_2_pin + entry->next;
150 static void __mask_IO_APIC_irq (unsigned int irq)
152 __modify_IO_APIC_irq(irq, 0x00010000, 0);
156 static void __unmask_IO_APIC_irq (unsigned int irq)
158 __modify_IO_APIC_irq(irq, 0, 0x00010000);
161 /* mask = 1, trigger = 0 */
162 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
164 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
167 /* mask = 0, trigger = 1 */
168 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
170 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
173 static void mask_IO_APIC_irq (unsigned int irq)
177 spin_lock_irqsave(&ioapic_lock, flags);
178 __mask_IO_APIC_irq(irq);
179 spin_unlock_irqrestore(&ioapic_lock, flags);
182 static void unmask_IO_APIC_irq (unsigned int irq)
186 spin_lock_irqsave(&ioapic_lock, flags);
187 __unmask_IO_APIC_irq(irq);
188 spin_unlock_irqrestore(&ioapic_lock, flags);
191 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
193 struct IO_APIC_route_entry entry;
196 /* Check delivery_mode to be sure we're not clearing an SMI pin */
197 spin_lock_irqsave(&ioapic_lock, flags);
198 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
199 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
200 spin_unlock_irqrestore(&ioapic_lock, flags);
201 if (entry.delivery_mode == dest_SMI)
205 * Disable it in the IO-APIC irq-routing table:
207 memset(&entry, 0, sizeof(entry));
209 spin_lock_irqsave(&ioapic_lock, flags);
210 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
211 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
212 spin_unlock_irqrestore(&ioapic_lock, flags);
215 static void clear_IO_APIC (void)
219 for (apic = 0; apic < nr_ioapics; apic++)
220 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
221 clear_IO_APIC_pin(apic, pin);
224 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
228 struct irq_pin_list *entry = irq_2_pin + irq;
229 unsigned int apicid_value;
231 apicid_value = cpu_mask_to_apicid(cpumask);
232 /* Prepare to do the io_apic_write */
233 apicid_value = apicid_value << 24;
234 spin_lock_irqsave(&ioapic_lock, flags);
239 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
242 entry = irq_2_pin + entry->next;
244 spin_unlock_irqrestore(&ioapic_lock, flags);
247 #if defined(CONFIG_IRQBALANCE)
248 # include <asm/processor.h> /* kernel_thread() */
249 # include <linux/kernel_stat.h> /* kstat */
250 # include <linux/slab.h> /* kmalloc() */
251 # include <linux/timer.h> /* time_after() */
253 # ifdef CONFIG_BALANCED_IRQ_DEBUG
254 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
255 # define Dprintk(x...) do { TDprintk(x); } while (0)
257 # define TDprintk(x...)
258 # define Dprintk(x...)
261 cpumask_t __cacheline_aligned pending_irq_balance_cpumask[NR_IRQS];
263 #define IRQBALANCE_CHECK_ARCH -999
264 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
265 static int physical_balance = 0;
267 struct irq_cpu_info {
268 unsigned long * last_irq;
269 unsigned long * irq_delta;
271 } irq_cpu_data[NR_CPUS];
273 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
274 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
275 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
277 #define IDLE_ENOUGH(cpu,now) \
278 (idle_cpu(cpu) && ((now) - irq_stat[(cpu)].idle_timestamp > 1))
280 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
282 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
284 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
285 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
286 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
287 #define BALANCED_IRQ_LESS_DELTA (HZ)
289 long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
291 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
292 unsigned long now, int direction)
300 if (unlikely(cpu == curr_cpu))
303 if (direction == 1) {
312 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
313 (search_idle && !IDLE_ENOUGH(cpu,now)));
318 static inline void balance_irq(int cpu, int irq)
320 unsigned long now = jiffies;
321 cpumask_t allowed_mask;
322 unsigned int new_cpu;
324 if (irqbalance_disabled)
327 cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
328 new_cpu = move(cpu, allowed_mask, now, 1);
329 if (cpu != new_cpu) {
330 irq_desc_t *desc = irq_desc + irq;
333 spin_lock_irqsave(&desc->lock, flags);
334 pending_irq_balance_cpumask[irq] = cpumask_of_cpu(new_cpu);
335 spin_unlock_irqrestore(&desc->lock, flags);
339 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
342 Dprintk("Rotating IRQs among CPUs.\n");
343 for (i = 0; i < NR_CPUS; i++) {
344 for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
345 if (!irq_desc[j].action)
347 /* Is it a significant load ? */
348 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
349 useful_load_threshold)
354 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
355 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
359 static void do_irq_balance(void)
362 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
363 unsigned long move_this_load = 0;
364 int max_loaded = 0, min_loaded = 0;
366 unsigned long useful_load_threshold = balanced_irq_interval + 10;
368 int tmp_loaded, first_attempt = 1;
369 unsigned long tmp_cpu_irq;
370 unsigned long imbalance = 0;
371 cpumask_t allowed_mask, target_cpu_mask, tmp;
373 for (i = 0; i < NR_CPUS; i++) {
378 package_index = CPU_TO_PACKAGEINDEX(i);
379 for (j = 0; j < NR_IRQS; j++) {
380 unsigned long value_now, delta;
381 /* Is this an active IRQ? */
382 if (!irq_desc[j].action)
384 if ( package_index == i )
385 IRQ_DELTA(package_index,j) = 0;
386 /* Determine the total count per processor per IRQ */
387 value_now = (unsigned long) kstat_cpu(i).irqs[j];
389 /* Determine the activity per processor per IRQ */
390 delta = value_now - LAST_CPU_IRQ(i,j);
392 /* Update last_cpu_irq[][] for the next time */
393 LAST_CPU_IRQ(i,j) = value_now;
395 /* Ignore IRQs whose rate is less than the clock */
396 if (delta < useful_load_threshold)
398 /* update the load for the processor or package total */
399 IRQ_DELTA(package_index,j) += delta;
401 /* Keep track of the higher numbered sibling as well */
402 if (i != package_index)
405 * We have sibling A and sibling B in the package
407 * cpu_irq[A] = load for cpu A + load for cpu B
408 * cpu_irq[B] = load for cpu B
410 CPU_IRQ(package_index) += delta;
413 /* Find the least loaded processor package */
414 for (i = 0; i < NR_CPUS; i++) {
417 if (i != CPU_TO_PACKAGEINDEX(i))
419 if (min_cpu_irq > CPU_IRQ(i)) {
420 min_cpu_irq = CPU_IRQ(i);
424 max_cpu_irq = ULONG_MAX;
427 /* Look for heaviest loaded processor.
428 * We may come back to get the next heaviest loaded processor.
429 * Skip processors with trivial loads.
433 for (i = 0; i < NR_CPUS; i++) {
436 if (i != CPU_TO_PACKAGEINDEX(i))
438 if (max_cpu_irq <= CPU_IRQ(i))
440 if (tmp_cpu_irq < CPU_IRQ(i)) {
441 tmp_cpu_irq = CPU_IRQ(i);
446 if (tmp_loaded == -1) {
447 /* In the case of small number of heavy interrupt sources,
448 * loading some of the cpus too much. We use Ingo's original
449 * approach to rotate them around.
451 if (!first_attempt && imbalance >= useful_load_threshold) {
452 rotate_irqs_among_cpus(useful_load_threshold);
455 goto not_worth_the_effort;
458 first_attempt = 0; /* heaviest search */
459 max_cpu_irq = tmp_cpu_irq; /* load */
460 max_loaded = tmp_loaded; /* processor */
461 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
463 Dprintk("max_loaded cpu = %d\n", max_loaded);
464 Dprintk("min_loaded cpu = %d\n", min_loaded);
465 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
466 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
467 Dprintk("load imbalance = %lu\n", imbalance);
469 /* if imbalance is less than approx 10% of max load, then
470 * observe diminishing returns action. - quit
472 if (imbalance < (max_cpu_irq >> 3)) {
473 Dprintk("Imbalance too trivial\n");
474 goto not_worth_the_effort;
478 /* if we select an IRQ to move that can't go where we want, then
479 * see if there is another one to try.
483 for (j = 0; j < NR_IRQS; j++) {
484 /* Is this an active IRQ? */
485 if (!irq_desc[j].action)
487 if (imbalance <= IRQ_DELTA(max_loaded,j))
489 /* Try to find the IRQ that is closest to the imbalance
490 * without going over.
492 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
493 move_this_load = IRQ_DELTA(max_loaded,j);
497 if (selected_irq == -1) {
501 imbalance = move_this_load;
503 /* For physical_balance case, we accumlated both load
504 * values in the one of the siblings cpu_irq[],
505 * to use the same code for physical and logical processors
506 * as much as possible.
508 * NOTE: the cpu_irq[] array holds the sum of the load for
509 * sibling A and sibling B in the slot for the lowest numbered
510 * sibling (A), _AND_ the load for sibling B in the slot for
511 * the higher numbered sibling.
513 * We seek the least loaded sibling by making the comparison
516 load = CPU_IRQ(min_loaded) >> 1;
517 for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
518 if (load > CPU_IRQ(j)) {
519 /* This won't change cpu_sibling_map[min_loaded] */
525 cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
526 target_cpu_mask = cpumask_of_cpu(min_loaded);
527 cpus_and(tmp, target_cpu_mask, allowed_mask);
529 if (!cpus_empty(tmp)) {
530 irq_desc_t *desc = irq_desc + selected_irq;
533 Dprintk("irq = %d moved to cpu = %d\n",
534 selected_irq, min_loaded);
535 /* mark for change destination */
536 spin_lock_irqsave(&desc->lock, flags);
537 pending_irq_balance_cpumask[selected_irq] =
538 cpumask_of_cpu(min_loaded);
539 spin_unlock_irqrestore(&desc->lock, flags);
540 /* Since we made a change, come back sooner to
541 * check for more variation.
543 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
544 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
549 not_worth_the_effort:
551 * if we did not find an IRQ to move, then adjust the time interval
554 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
555 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
556 Dprintk("IRQ worth rotating not found\n");
560 static int balanced_irq(void *unused)
563 unsigned long prev_balance_time = jiffies;
564 long time_remaining = balanced_irq_interval;
568 /* push everything to CPU 0 to give us a starting point. */
569 for (i = 0 ; i < NR_IRQS ; i++) {
570 pending_irq_balance_cpumask[i] = cpumask_of_cpu(0);
574 set_current_state(TASK_INTERRUPTIBLE);
575 time_remaining = schedule_timeout(time_remaining);
576 try_to_freeze(PF_FREEZE);
577 if (time_after(jiffies,
578 prev_balance_time+balanced_irq_interval)) {
580 prev_balance_time = jiffies;
581 time_remaining = balanced_irq_interval;
587 static int __init balanced_irq_init(void)
590 struct cpuinfo_x86 *c;
593 cpus_shift_right(tmp, cpu_online_map, 2);
595 /* When not overwritten by the command line ask subarchitecture. */
596 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
597 irqbalance_disabled = NO_BALANCE_IRQ;
598 if (irqbalance_disabled)
601 /* disable irqbalance completely if there is only one processor online */
602 if (num_online_cpus() < 2) {
603 irqbalance_disabled = 1;
607 * Enable physical balance only if more than 1 physical processor
610 if (smp_num_siblings > 1 && !cpus_empty(tmp))
611 physical_balance = 1;
613 for (i = 0; i < NR_CPUS; i++) {
616 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
617 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
618 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
619 printk(KERN_ERR "balanced_irq_init: out of memory");
622 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
623 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
626 printk(KERN_INFO "Starting balanced_irq\n");
627 if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
630 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
632 for (i = 0; i < NR_CPUS; i++) {
633 if(irq_cpu_data[i].irq_delta)
634 kfree(irq_cpu_data[i].irq_delta);
635 if(irq_cpu_data[i].last_irq)
636 kfree(irq_cpu_data[i].last_irq);
641 int __init irqbalance_disable(char *str)
643 irqbalance_disabled = 1;
647 __setup("noirqbalance", irqbalance_disable);
649 static inline void move_irq(int irq)
651 /* note - we hold the desc->lock */
652 if (unlikely(!cpus_empty(pending_irq_balance_cpumask[irq]))) {
653 set_ioapic_affinity_irq(irq, pending_irq_balance_cpumask[irq]);
654 cpus_clear(pending_irq_balance_cpumask[irq]);
658 late_initcall(balanced_irq_init);
660 #else /* !CONFIG_IRQBALANCE */
661 static inline void move_irq(int irq) { }
662 #endif /* CONFIG_IRQBALANCE */
665 void fastcall send_IPI_self(int vector)
672 apic_wait_icr_idle();
673 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
675 * Send the IPI. The write to APIC_ICR fires this off.
677 apic_write_around(APIC_ICR, cfg);
679 #endif /* !CONFIG_SMP */
683 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
684 * specific CPU-side IRQs.
688 int pirq_entries [MAX_PIRQS];
690 int skip_ioapic_setup;
692 static int __init ioapic_setup(char *str)
694 skip_ioapic_setup = 1;
698 __setup("noapic", ioapic_setup);
700 static int __init ioapic_pirq_setup(char *str)
703 int ints[MAX_PIRQS+1];
705 get_options(str, ARRAY_SIZE(ints), ints);
707 for (i = 0; i < MAX_PIRQS; i++)
708 pirq_entries[i] = -1;
711 apic_printk(APIC_VERBOSE, KERN_INFO
712 "PIRQ redirection, working around broken MP-BIOS.\n");
714 if (ints[0] < MAX_PIRQS)
717 for (i = 0; i < max; i++) {
718 apic_printk(APIC_VERBOSE, KERN_DEBUG
719 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
721 * PIRQs are mapped upside down, usually.
723 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
728 __setup("pirq=", ioapic_pirq_setup);
731 * Find the IRQ entry number of a certain pin.
733 static int find_irq_entry(int apic, int pin, int type)
737 for (i = 0; i < mp_irq_entries; i++)
738 if (mp_irqs[i].mpc_irqtype == type &&
739 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
740 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
741 mp_irqs[i].mpc_dstirq == pin)
748 * Find the pin to which IRQ[irq] (ISA) is connected
750 static int find_isa_irq_pin(int irq, int type)
754 for (i = 0; i < mp_irq_entries; i++) {
755 int lbus = mp_irqs[i].mpc_srcbus;
757 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
758 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
759 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
760 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
762 (mp_irqs[i].mpc_irqtype == type) &&
763 (mp_irqs[i].mpc_srcbusirq == irq))
765 return mp_irqs[i].mpc_dstirq;
771 * Find a specific PCI IRQ entry.
772 * Not an __init, possibly needed by modules
774 static int pin_2_irq(int idx, int apic, int pin);
776 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
778 int apic, i, best_guess = -1;
780 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
781 "slot:%d, pin:%d.\n", bus, slot, pin);
782 if (mp_bus_id_to_pci_bus[bus] == -1) {
783 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
786 for (i = 0; i < mp_irq_entries; i++) {
787 int lbus = mp_irqs[i].mpc_srcbus;
789 for (apic = 0; apic < nr_ioapics; apic++)
790 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
791 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
794 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
795 !mp_irqs[i].mpc_irqtype &&
797 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
798 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
800 if (!(apic || IO_APIC_IRQ(irq)))
803 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
806 * Use the first all-but-pin matching entry as a
807 * best-guess fuzzy result for broken mptables.
817 * This function currently is only a helper for the i386 smp boot process where
818 * we need to reprogram the ioredtbls to cater for the cpus which have come online
819 * so mask in all cases should simply be TARGET_CPUS
821 void __init setup_ioapic_dest(void)
823 int pin, ioapic, irq, irq_entry;
825 if (skip_ioapic_setup == 1)
828 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
829 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
830 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
833 irq = pin_2_irq(irq_entry, ioapic, pin);
834 set_ioapic_affinity_irq(irq, TARGET_CPUS);
841 * EISA Edge/Level control register, ELCR
843 static int EISA_ELCR(unsigned int irq)
846 unsigned int port = 0x4d0 + (irq >> 3);
847 return (inb(port) >> (irq & 7)) & 1;
849 apic_printk(APIC_VERBOSE, KERN_INFO
850 "Broken MPtable reports ISA irq %d\n", irq);
854 /* EISA interrupts are always polarity zero and can be edge or level
855 * trigger depending on the ELCR value. If an interrupt is listed as
856 * EISA conforming in the MP table, that means its trigger type must
857 * be read in from the ELCR */
859 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
860 #define default_EISA_polarity(idx) (0)
862 /* ISA interrupts are always polarity zero edge triggered,
863 * when listed as conforming in the MP table. */
865 #define default_ISA_trigger(idx) (0)
866 #define default_ISA_polarity(idx) (0)
868 /* PCI interrupts are always polarity one level triggered,
869 * when listed as conforming in the MP table. */
871 #define default_PCI_trigger(idx) (1)
872 #define default_PCI_polarity(idx) (1)
874 /* MCA interrupts are always polarity zero level triggered,
875 * when listed as conforming in the MP table. */
877 #define default_MCA_trigger(idx) (1)
878 #define default_MCA_polarity(idx) (0)
880 /* NEC98 interrupts are always polarity zero edge triggered,
881 * when listed as conforming in the MP table. */
883 #define default_NEC98_trigger(idx) (0)
884 #define default_NEC98_polarity(idx) (0)
886 static int __init MPBIOS_polarity(int idx)
888 int bus = mp_irqs[idx].mpc_srcbus;
892 * Determine IRQ line polarity (high active or low active):
894 switch (mp_irqs[idx].mpc_irqflag & 3)
896 case 0: /* conforms, ie. bus-type dependent polarity */
898 switch (mp_bus_id_to_type[bus])
900 case MP_BUS_ISA: /* ISA pin */
902 polarity = default_ISA_polarity(idx);
905 case MP_BUS_EISA: /* EISA pin */
907 polarity = default_EISA_polarity(idx);
910 case MP_BUS_PCI: /* PCI pin */
912 polarity = default_PCI_polarity(idx);
915 case MP_BUS_MCA: /* MCA pin */
917 polarity = default_MCA_polarity(idx);
920 case MP_BUS_NEC98: /* NEC 98 pin */
922 polarity = default_NEC98_polarity(idx);
927 printk(KERN_WARNING "broken BIOS!!\n");
934 case 1: /* high active */
939 case 2: /* reserved */
941 printk(KERN_WARNING "broken BIOS!!\n");
945 case 3: /* low active */
950 default: /* invalid */
952 printk(KERN_WARNING "broken BIOS!!\n");
960 static int MPBIOS_trigger(int idx)
962 int bus = mp_irqs[idx].mpc_srcbus;
966 * Determine IRQ trigger mode (edge or level sensitive):
968 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
970 case 0: /* conforms, ie. bus-type dependent */
972 switch (mp_bus_id_to_type[bus])
974 case MP_BUS_ISA: /* ISA pin */
976 trigger = default_ISA_trigger(idx);
979 case MP_BUS_EISA: /* EISA pin */
981 trigger = default_EISA_trigger(idx);
984 case MP_BUS_PCI: /* PCI pin */
986 trigger = default_PCI_trigger(idx);
989 case MP_BUS_MCA: /* MCA pin */
991 trigger = default_MCA_trigger(idx);
994 case MP_BUS_NEC98: /* NEC 98 pin */
996 trigger = default_NEC98_trigger(idx);
1001 printk(KERN_WARNING "broken BIOS!!\n");
1013 case 2: /* reserved */
1015 printk(KERN_WARNING "broken BIOS!!\n");
1024 default: /* invalid */
1026 printk(KERN_WARNING "broken BIOS!!\n");
1034 static inline int irq_polarity(int idx)
1036 return MPBIOS_polarity(idx);
1039 static inline int irq_trigger(int idx)
1041 return MPBIOS_trigger(idx);
1044 static int pin_2_irq(int idx, int apic, int pin)
1047 int bus = mp_irqs[idx].mpc_srcbus;
1050 * Debugging check, we are in big trouble if this message pops up!
1052 if (mp_irqs[idx].mpc_dstirq != pin)
1053 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1055 switch (mp_bus_id_to_type[bus])
1057 case MP_BUS_ISA: /* ISA pin */
1062 irq = mp_irqs[idx].mpc_srcbusirq;
1065 case MP_BUS_PCI: /* PCI pin */
1068 * PCI IRQs are mapped in order
1072 irq += nr_ioapic_registers[i++];
1076 * For MPS mode, so far only needed by ES7000 platform
1078 if (ioapic_renumber_irq)
1079 irq = ioapic_renumber_irq(apic, irq);
1085 printk(KERN_ERR "unknown bus type %d.\n",bus);
1092 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1094 if ((pin >= 16) && (pin <= 23)) {
1095 if (pirq_entries[pin-16] != -1) {
1096 if (!pirq_entries[pin-16]) {
1097 apic_printk(APIC_VERBOSE, KERN_DEBUG
1098 "disabling PIRQ%d\n", pin-16);
1100 irq = pirq_entries[pin-16];
1101 apic_printk(APIC_VERBOSE, KERN_DEBUG
1102 "using PIRQ%d -> IRQ %d\n",
1110 static inline int IO_APIC_irq_trigger(int irq)
1114 for (apic = 0; apic < nr_ioapics; apic++) {
1115 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1116 idx = find_irq_entry(apic,pin,mp_INT);
1117 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1118 return irq_trigger(idx);
1122 * nonexistent IRQs are edge default
1127 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1128 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
1130 int assign_irq_vector(int irq)
1132 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1134 BUG_ON(irq >= NR_IRQ_VECTORS);
1135 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1136 return IO_APIC_VECTOR(irq);
1138 current_vector += 8;
1139 if (current_vector == SYSCALL_VECTOR)
1142 if (current_vector >= FIRST_SYSTEM_VECTOR) {
1146 current_vector = FIRST_DEVICE_VECTOR + offset;
1149 vector_irq[current_vector] = irq;
1150 if (irq != AUTO_ASSIGN)
1151 IO_APIC_VECTOR(irq) = current_vector;
1153 return current_vector;
1156 static struct hw_interrupt_type ioapic_level_type;
1157 static struct hw_interrupt_type ioapic_edge_type;
1159 #define IOAPIC_AUTO -1
1160 #define IOAPIC_EDGE 0
1161 #define IOAPIC_LEVEL 1
1163 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1165 if (use_pci_vector() && !platform_legacy_irq(irq)) {
1166 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1167 trigger == IOAPIC_LEVEL)
1168 irq_desc[vector].handler = &ioapic_level_type;
1170 irq_desc[vector].handler = &ioapic_edge_type;
1171 set_intr_gate(vector, interrupt[vector]);
1173 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1174 trigger == IOAPIC_LEVEL)
1175 irq_desc[irq].handler = &ioapic_level_type;
1177 irq_desc[irq].handler = &ioapic_edge_type;
1178 set_intr_gate(vector, interrupt[irq]);
1182 void __init setup_IO_APIC_irqs(void)
1184 struct IO_APIC_route_entry entry;
1185 int apic, pin, idx, irq, first_notcon = 1, vector;
1186 unsigned long flags;
1188 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1190 for (apic = 0; apic < nr_ioapics; apic++) {
1191 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1194 * add it to the IO-APIC irq-routing table:
1196 memset(&entry,0,sizeof(entry));
1198 entry.delivery_mode = INT_DELIVERY_MODE;
1199 entry.dest_mode = INT_DEST_MODE;
1200 entry.mask = 0; /* enable IRQ */
1201 entry.dest.logical.logical_dest =
1202 cpu_mask_to_apicid(TARGET_CPUS);
1204 idx = find_irq_entry(apic,pin,mp_INT);
1207 apic_printk(APIC_VERBOSE, KERN_DEBUG
1208 " IO-APIC (apicid-pin) %d-%d",
1209 mp_ioapics[apic].mpc_apicid,
1213 apic_printk(APIC_VERBOSE, ", %d-%d",
1214 mp_ioapics[apic].mpc_apicid, pin);
1218 entry.trigger = irq_trigger(idx);
1219 entry.polarity = irq_polarity(idx);
1221 if (irq_trigger(idx)) {
1226 irq = pin_2_irq(idx, apic, pin);
1228 * skip adding the timer int on secondary nodes, which causes
1229 * a small but painful rift in the time-space continuum
1231 if (multi_timer_check(apic, irq))
1234 add_pin_to_irq(irq, apic, pin);
1236 if (!apic && !IO_APIC_IRQ(irq))
1239 if (IO_APIC_IRQ(irq)) {
1240 vector = assign_irq_vector(irq);
1241 entry.vector = vector;
1242 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1244 if (!apic && (irq < 16))
1245 disable_8259A_irq(irq);
1247 spin_lock_irqsave(&ioapic_lock, flags);
1248 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1249 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1250 spin_unlock_irqrestore(&ioapic_lock, flags);
1255 apic_printk(APIC_VERBOSE, " not connected.\n");
1259 * Set up the 8259A-master output pin:
1261 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
1263 struct IO_APIC_route_entry entry;
1264 unsigned long flags;
1266 memset(&entry,0,sizeof(entry));
1268 disable_8259A_irq(0);
1271 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1274 * We use logical delivery to get the timer IRQ
1277 entry.dest_mode = INT_DEST_MODE;
1278 entry.mask = 0; /* unmask IRQ now */
1279 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1280 entry.delivery_mode = INT_DELIVERY_MODE;
1283 entry.vector = vector;
1286 * The timer IRQ doesn't have to know that behind the
1287 * scene we have a 8259A-master in AEOI mode ...
1289 irq_desc[0].handler = &ioapic_edge_type;
1292 * Add it to the IO-APIC irq-routing table:
1294 spin_lock_irqsave(&ioapic_lock, flags);
1295 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1296 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1297 spin_unlock_irqrestore(&ioapic_lock, flags);
1299 enable_8259A_irq(0);
1302 static inline void UNEXPECTED_IO_APIC(void)
1306 void __init print_IO_APIC(void)
1309 union IO_APIC_reg_00 reg_00;
1310 union IO_APIC_reg_01 reg_01;
1311 union IO_APIC_reg_02 reg_02;
1312 union IO_APIC_reg_03 reg_03;
1313 unsigned long flags;
1315 if (apic_verbosity == APIC_QUIET)
1318 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1319 for (i = 0; i < nr_ioapics; i++)
1320 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1321 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1324 * We are a bit conservative about what we expect. We have to
1325 * know about every hardware change ASAP.
1327 printk(KERN_INFO "testing the IO APIC.......................\n");
1329 for (apic = 0; apic < nr_ioapics; apic++) {
1331 spin_lock_irqsave(&ioapic_lock, flags);
1332 reg_00.raw = io_apic_read(apic, 0);
1333 reg_01.raw = io_apic_read(apic, 1);
1334 if (reg_01.bits.version >= 0x10)
1335 reg_02.raw = io_apic_read(apic, 2);
1336 if (reg_01.bits.version >= 0x20)
1337 reg_03.raw = io_apic_read(apic, 3);
1338 spin_unlock_irqrestore(&ioapic_lock, flags);
1340 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1341 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1342 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1343 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1344 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1345 if (reg_00.bits.ID >= get_physical_broadcast())
1346 UNEXPECTED_IO_APIC();
1347 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1348 UNEXPECTED_IO_APIC();
1350 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1351 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1352 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1353 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1354 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1355 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1356 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1357 (reg_01.bits.entries != 0x2E) &&
1358 (reg_01.bits.entries != 0x3F)
1360 UNEXPECTED_IO_APIC();
1362 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1363 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1364 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1365 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1366 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1367 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1368 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1370 UNEXPECTED_IO_APIC();
1371 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1372 UNEXPECTED_IO_APIC();
1375 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1376 * but the value of reg_02 is read as the previous read register
1377 * value, so ignore it if reg_02 == reg_01.
1379 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1380 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1381 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1382 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1383 UNEXPECTED_IO_APIC();
1387 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1388 * or reg_03, but the value of reg_0[23] is read as the previous read
1389 * register value, so ignore it if reg_03 == reg_0[12].
1391 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1392 reg_03.raw != reg_01.raw) {
1393 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1394 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1395 if (reg_03.bits.__reserved_1)
1396 UNEXPECTED_IO_APIC();
1399 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1401 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1402 " Stat Dest Deli Vect: \n");
1404 for (i = 0; i <= reg_01.bits.entries; i++) {
1405 struct IO_APIC_route_entry entry;
1407 spin_lock_irqsave(&ioapic_lock, flags);
1408 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1409 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1410 spin_unlock_irqrestore(&ioapic_lock, flags);
1412 printk(KERN_DEBUG " %02x %03X %02X ",
1414 entry.dest.logical.logical_dest,
1415 entry.dest.physical.physical_dest
1418 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1423 entry.delivery_status,
1425 entry.delivery_mode,
1430 if (use_pci_vector())
1431 printk(KERN_INFO "Using vector-based indexing\n");
1432 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1433 for (i = 0; i < NR_IRQS; i++) {
1434 struct irq_pin_list *entry = irq_2_pin + i;
1437 if (use_pci_vector() && !platform_legacy_irq(i))
1438 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1440 printk(KERN_DEBUG "IRQ%d ", i);
1442 printk("-> %d:%d", entry->apic, entry->pin);
1445 entry = irq_2_pin + entry->next;
1450 printk(KERN_INFO ".................................... done.\n");
1455 static void print_APIC_bitfield (int base)
1460 if (apic_verbosity == APIC_QUIET)
1463 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1464 for (i = 0; i < 8; i++) {
1465 v = apic_read(base + i*0x10);
1466 for (j = 0; j < 32; j++) {
1476 void /*__init*/ print_local_APIC(void * dummy)
1478 unsigned int v, ver, maxlvt;
1480 if (apic_verbosity == APIC_QUIET)
1483 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1484 smp_processor_id(), hard_smp_processor_id());
1485 v = apic_read(APIC_ID);
1486 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1487 v = apic_read(APIC_LVR);
1488 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1489 ver = GET_APIC_VERSION(v);
1490 maxlvt = get_maxlvt();
1492 v = apic_read(APIC_TASKPRI);
1493 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1495 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1496 v = apic_read(APIC_ARBPRI);
1497 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1498 v & APIC_ARBPRI_MASK);
1499 v = apic_read(APIC_PROCPRI);
1500 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1503 v = apic_read(APIC_EOI);
1504 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1505 v = apic_read(APIC_RRR);
1506 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1507 v = apic_read(APIC_LDR);
1508 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1509 v = apic_read(APIC_DFR);
1510 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1511 v = apic_read(APIC_SPIV);
1512 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1514 printk(KERN_DEBUG "... APIC ISR field:\n");
1515 print_APIC_bitfield(APIC_ISR);
1516 printk(KERN_DEBUG "... APIC TMR field:\n");
1517 print_APIC_bitfield(APIC_TMR);
1518 printk(KERN_DEBUG "... APIC IRR field:\n");
1519 print_APIC_bitfield(APIC_IRR);
1521 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1522 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1523 apic_write(APIC_ESR, 0);
1524 v = apic_read(APIC_ESR);
1525 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1528 v = apic_read(APIC_ICR);
1529 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1530 v = apic_read(APIC_ICR2);
1531 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1533 v = apic_read(APIC_LVTT);
1534 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1536 if (maxlvt > 3) { /* PC is LVT#4. */
1537 v = apic_read(APIC_LVTPC);
1538 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1540 v = apic_read(APIC_LVT0);
1541 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1542 v = apic_read(APIC_LVT1);
1543 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1545 if (maxlvt > 2) { /* ERR is LVT#3. */
1546 v = apic_read(APIC_LVTERR);
1547 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1550 v = apic_read(APIC_TMICT);
1551 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1552 v = apic_read(APIC_TMCCT);
1553 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1554 v = apic_read(APIC_TDCR);
1555 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1559 void print_all_local_APICs (void)
1561 on_each_cpu(print_local_APIC, NULL, 1, 1);
1564 void /*__init*/ print_PIC(void)
1566 extern spinlock_t i8259A_lock;
1568 unsigned long flags;
1570 if (apic_verbosity == APIC_QUIET)
1573 printk(KERN_DEBUG "\nprinting PIC contents\n");
1575 spin_lock_irqsave(&i8259A_lock, flags);
1577 v = inb(0xa1) << 8 | inb(0x21);
1578 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1580 v = inb(0xa0) << 8 | inb(0x20);
1581 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1585 v = inb(0xa0) << 8 | inb(0x20);
1589 spin_unlock_irqrestore(&i8259A_lock, flags);
1591 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1593 v = inb(0x4d1) << 8 | inb(0x4d0);
1594 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1597 static void __init enable_IO_APIC(void)
1599 union IO_APIC_reg_01 reg_01;
1601 unsigned long flags;
1603 for (i = 0; i < PIN_MAP_SIZE; i++) {
1604 irq_2_pin[i].pin = -1;
1605 irq_2_pin[i].next = 0;
1608 for (i = 0; i < MAX_PIRQS; i++)
1609 pirq_entries[i] = -1;
1612 * The number of IO-APIC IRQ registers (== #pins):
1614 for (i = 0; i < nr_ioapics; i++) {
1615 spin_lock_irqsave(&ioapic_lock, flags);
1616 reg_01.raw = io_apic_read(i, 1);
1617 spin_unlock_irqrestore(&ioapic_lock, flags);
1618 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1622 * Do not trust the IO-APIC being empty at bootup
1628 * Not an __init, needed by the reboot code
1630 void disable_IO_APIC(void)
1633 * Clear the IO-APIC before rebooting:
1637 disconnect_bsp_APIC();
1641 * function to set the IO-APIC physical IDs based on the
1642 * values stored in the MPC table.
1644 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1647 #ifndef CONFIG_X86_NUMAQ
1648 static void __init setup_ioapic_ids_from_mpc(void)
1650 union IO_APIC_reg_00 reg_00;
1651 physid_mask_t phys_id_present_map;
1654 unsigned char old_id;
1655 unsigned long flags;
1658 * This is broken; anything with a real cpu count has to
1659 * circumvent this idiocy regardless.
1661 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1664 * Set the IOAPIC ID to the value stored in the MPC table.
1666 for (apic = 0; apic < nr_ioapics; apic++) {
1668 /* Read the register 0 value */
1669 spin_lock_irqsave(&ioapic_lock, flags);
1670 reg_00.raw = io_apic_read(apic, 0);
1671 spin_unlock_irqrestore(&ioapic_lock, flags);
1673 old_id = mp_ioapics[apic].mpc_apicid;
1675 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1676 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1677 apic, mp_ioapics[apic].mpc_apicid);
1678 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1680 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1683 /* Don't check I/O APIC IDs for some xAPIC systems. They have
1684 * no meaning without the serial APIC bus. */
1685 if (NO_IOAPIC_CHECK)
1688 * Sanity check, is the ID really free? Every APIC in a
1689 * system must have a unique ID or we get lots of nice
1690 * 'stuck on smp_invalidate_needed IPI wait' messages.
1692 if (check_apicid_used(phys_id_present_map,
1693 mp_ioapics[apic].mpc_apicid)) {
1694 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1695 apic, mp_ioapics[apic].mpc_apicid);
1696 for (i = 0; i < get_physical_broadcast(); i++)
1697 if (!physid_isset(i, phys_id_present_map))
1699 if (i >= get_physical_broadcast())
1700 panic("Max APIC ID exceeded!\n");
1701 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1703 physid_set(i, phys_id_present_map);
1704 mp_ioapics[apic].mpc_apicid = i;
1707 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1708 apic_printk(APIC_VERBOSE, "Setting %d in the "
1709 "phys_id_present_map\n",
1710 mp_ioapics[apic].mpc_apicid);
1711 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1716 * We need to adjust the IRQ routing table
1717 * if the ID changed.
1719 if (old_id != mp_ioapics[apic].mpc_apicid)
1720 for (i = 0; i < mp_irq_entries; i++)
1721 if (mp_irqs[i].mpc_dstapic == old_id)
1722 mp_irqs[i].mpc_dstapic
1723 = mp_ioapics[apic].mpc_apicid;
1726 * Read the right value from the MPC table and
1727 * write it into the ID register.
1729 apic_printk(APIC_VERBOSE, KERN_INFO
1730 "...changing IO-APIC physical APIC ID to %d ...",
1731 mp_ioapics[apic].mpc_apicid);
1733 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1734 spin_lock_irqsave(&ioapic_lock, flags);
1735 io_apic_write(apic, 0, reg_00.raw);
1736 spin_unlock_irqrestore(&ioapic_lock, flags);
1741 spin_lock_irqsave(&ioapic_lock, flags);
1742 reg_00.raw = io_apic_read(apic, 0);
1743 spin_unlock_irqrestore(&ioapic_lock, flags);
1744 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1745 printk("could not set ID!\n");
1747 apic_printk(APIC_VERBOSE, " ok.\n");
1751 static void __init setup_ioapic_ids_from_mpc(void) { }
1755 * There is a nasty bug in some older SMP boards, their mptable lies
1756 * about the timer IRQ. We do the following to work around the situation:
1758 * - timer IRQ defaults to IO-APIC IRQ
1759 * - if this function detects that timer IRQs are defunct, then we fall
1760 * back to ISA timer IRQs
1762 static int __init timer_irq_works(void)
1764 unsigned long t1 = jiffies;
1767 /* Let ten ticks pass... */
1768 mdelay((10 * 1000) / HZ);
1771 * Expect a few ticks at least, to be sure some possible
1772 * glue logic does not lock up after one or two first
1773 * ticks in a non-ExtINT mode. Also the local APIC
1774 * might have cached one ExtINT interrupt. Finally, at
1775 * least one tick may be lost due to delays.
1777 if (jiffies - t1 > 4)
1784 * In the SMP+IOAPIC case it might happen that there are an unspecified
1785 * number of pending IRQ events unhandled. These cases are very rare,
1786 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1787 * better to do it this way as thus we do not have to be aware of
1788 * 'pending' interrupts in the IRQ path, except at this point.
1791 * Edge triggered needs to resend any interrupt
1792 * that was delayed but this is now handled in the device
1797 * Starting up a edge-triggered IO-APIC interrupt is
1798 * nasty - we need to make sure that we get the edge.
1799 * If it is already asserted for some reason, we need
1800 * return 1 to indicate that is was pending.
1802 * This is not complete - we should be able to fake
1803 * an edge even if it isn't on the 8259A...
1805 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1807 int was_pending = 0;
1808 unsigned long flags;
1810 spin_lock_irqsave(&ioapic_lock, flags);
1812 disable_8259A_irq(irq);
1813 if (i8259A_irq_pending(irq))
1816 __unmask_IO_APIC_irq(irq);
1817 spin_unlock_irqrestore(&ioapic_lock, flags);
1823 * Once we have recorded IRQ_PENDING already, we can mask the
1824 * interrupt for real. This prevents IRQ storms from unhandled
1827 static void ack_edge_ioapic_irq(unsigned int irq)
1830 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1831 == (IRQ_PENDING | IRQ_DISABLED))
1832 mask_IO_APIC_irq(irq);
1837 * Level triggered interrupts can just be masked,
1838 * and shutting down and starting up the interrupt
1839 * is the same as enabling and disabling them -- except
1840 * with a startup need to return a "was pending" value.
1842 * Level triggered interrupts are special because we
1843 * do not touch any IO-APIC register while handling
1844 * them. We ack the APIC in the end-IRQ handler, not
1845 * in the start-IRQ-handler. Protection against reentrance
1846 * from the same interrupt is still provided, both by the
1847 * generic IRQ layer and by the fact that an unacked local
1848 * APIC does not accept IRQs.
1850 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1852 unmask_IO_APIC_irq(irq);
1854 return 0; /* don't check for pending */
1857 static void end_level_ioapic_irq (unsigned int irq)
1864 * It appears there is an erratum which affects at least version 0x11
1865 * of I/O APIC (that's the 82093AA and cores integrated into various
1866 * chipsets). Under certain conditions a level-triggered interrupt is
1867 * erroneously delivered as edge-triggered one but the respective IRR
1868 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1869 * message but it will never arrive and further interrupts are blocked
1870 * from the source. The exact reason is so far unknown, but the
1871 * phenomenon was observed when two consecutive interrupt requests
1872 * from a given source get delivered to the same CPU and the source is
1873 * temporarily disabled in between.
1875 * A workaround is to simulate an EOI message manually. We achieve it
1876 * by setting the trigger mode to edge and then to level when the edge
1877 * trigger mode gets detected in the TMR of a local APIC for a
1878 * level-triggered interrupt. We mask the source for the time of the
1879 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1880 * The idea is from Manfred Spraul. --macro
1882 i = IO_APIC_VECTOR(irq);
1884 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1888 if (!(v & (1 << (i & 0x1f)))) {
1889 atomic_inc(&irq_mis_count);
1890 spin_lock(&ioapic_lock);
1891 __mask_and_edge_IO_APIC_irq(irq);
1892 __unmask_and_level_IO_APIC_irq(irq);
1893 spin_unlock(&ioapic_lock);
1897 #ifdef CONFIG_PCI_MSI
1898 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1900 int irq = vector_to_irq(vector);
1902 return startup_edge_ioapic_irq(irq);
1905 static void ack_edge_ioapic_vector(unsigned int vector)
1907 int irq = vector_to_irq(vector);
1909 ack_edge_ioapic_irq(irq);
1912 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1914 int irq = vector_to_irq(vector);
1916 return startup_level_ioapic_irq (irq);
1919 static void end_level_ioapic_vector (unsigned int vector)
1921 int irq = vector_to_irq(vector);
1923 end_level_ioapic_irq(irq);
1926 static void mask_IO_APIC_vector (unsigned int vector)
1928 int irq = vector_to_irq(vector);
1930 mask_IO_APIC_irq(irq);
1933 static void unmask_IO_APIC_vector (unsigned int vector)
1935 int irq = vector_to_irq(vector);
1937 unmask_IO_APIC_irq(irq);
1940 static void set_ioapic_affinity_vector (unsigned int vector,
1943 int irq = vector_to_irq(vector);
1945 set_ioapic_affinity_irq(irq, cpu_mask);
1950 * Level and edge triggered IO-APIC interrupts need different handling,
1951 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1952 * handled with the level-triggered descriptor, but that one has slightly
1953 * more overhead. Level-triggered interrupts cannot be handled with the
1954 * edge-triggered handler, without risking IRQ storms and other ugly
1957 static struct hw_interrupt_type ioapic_edge_type = {
1958 .typename = "IO-APIC-edge",
1959 .startup = startup_edge_ioapic,
1960 .shutdown = shutdown_edge_ioapic,
1961 .enable = enable_edge_ioapic,
1962 .disable = disable_edge_ioapic,
1963 .ack = ack_edge_ioapic,
1964 .end = end_edge_ioapic,
1965 .set_affinity = set_ioapic_affinity,
1968 static struct hw_interrupt_type ioapic_level_type = {
1969 .typename = "IO-APIC-level",
1970 .startup = startup_level_ioapic,
1971 .shutdown = shutdown_level_ioapic,
1972 .enable = enable_level_ioapic,
1973 .disable = disable_level_ioapic,
1974 .ack = mask_and_ack_level_ioapic,
1975 .end = end_level_ioapic,
1976 .set_affinity = set_ioapic_affinity,
1979 static inline void init_IO_APIC_traps(void)
1984 * NOTE! The local APIC isn't very good at handling
1985 * multiple interrupts at the same interrupt level.
1986 * As the interrupt level is determined by taking the
1987 * vector number and shifting that right by 4, we
1988 * want to spread these out a bit so that they don't
1989 * all fall in the same interrupt level.
1991 * Also, we've got to be careful not to trash gate
1992 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1994 for (irq = 0; irq < NR_IRQS ; irq++) {
1996 if (use_pci_vector()) {
1997 if (!platform_legacy_irq(tmp))
1998 if ((tmp = vector_to_irq(tmp)) == -1)
2001 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2003 * Hmm.. We don't have an entry for this,
2004 * so default to an old-fashioned 8259
2005 * interrupt if we can..
2008 make_8259A_irq(irq);
2010 /* Strange. Oh, well.. */
2011 irq_desc[irq].handler = &no_irq_type;
2016 static void enable_lapic_irq (unsigned int irq)
2020 v = apic_read(APIC_LVT0);
2021 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2024 static void disable_lapic_irq (unsigned int irq)
2028 v = apic_read(APIC_LVT0);
2029 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2032 static void ack_lapic_irq (unsigned int irq)
2037 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2039 static struct hw_interrupt_type lapic_irq_type = {
2040 .typename = "local-APIC-edge",
2041 .startup = NULL, /* startup_irq() not used for IRQ0 */
2042 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
2043 .enable = enable_lapic_irq,
2044 .disable = disable_lapic_irq,
2045 .ack = ack_lapic_irq,
2046 .end = end_lapic_irq
2049 static void setup_nmi (void)
2052 * Dirty trick to enable the NMI watchdog ...
2053 * We put the 8259A master into AEOI mode and
2054 * unmask on all local APICs LVT0 as NMI.
2056 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2057 * is from Maciej W. Rozycki - so we do not have to EOI from
2058 * the NMI handler or the timer interrupt.
2060 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2062 on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2064 apic_printk(APIC_VERBOSE, " done.\n");
2068 * This looks a bit hackish but it's about the only one way of sending
2069 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2070 * not support the ExtINT mode, unfortunately. We need to send these
2071 * cycles as some i82489DX-based boards have glue logic that keeps the
2072 * 8259A interrupt line asserted until INTA. --macro
2074 static inline void unlock_ExtINT_logic(void)
2077 struct IO_APIC_route_entry entry0, entry1;
2078 unsigned char save_control, save_freq_select;
2079 unsigned long flags;
2081 pin = find_isa_irq_pin(8, mp_INT);
2085 spin_lock_irqsave(&ioapic_lock, flags);
2086 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
2087 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
2088 spin_unlock_irqrestore(&ioapic_lock, flags);
2089 clear_IO_APIC_pin(0, pin);
2091 memset(&entry1, 0, sizeof(entry1));
2093 entry1.dest_mode = 0; /* physical delivery */
2094 entry1.mask = 0; /* unmask IRQ now */
2095 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2096 entry1.delivery_mode = dest_ExtINT;
2097 entry1.polarity = entry0.polarity;
2101 spin_lock_irqsave(&ioapic_lock, flags);
2102 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2103 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2104 spin_unlock_irqrestore(&ioapic_lock, flags);
2106 save_control = CMOS_READ(RTC_CONTROL);
2107 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2108 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2110 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2115 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2119 CMOS_WRITE(save_control, RTC_CONTROL);
2120 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2121 clear_IO_APIC_pin(0, pin);
2123 spin_lock_irqsave(&ioapic_lock, flags);
2124 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2125 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2126 spin_unlock_irqrestore(&ioapic_lock, flags);
2130 * This code may look a bit paranoid, but it's supposed to cooperate with
2131 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2132 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2133 * fanatically on his truly buggy board.
2135 static inline void check_timer(void)
2141 * get/set the timer IRQ vector:
2143 disable_8259A_irq(0);
2144 vector = assign_irq_vector(0);
2145 set_intr_gate(vector, interrupt[0]);
2148 * Subtle, code in do_timer_interrupt() expects an AEOI
2149 * mode for the 8259A whenever interrupts are routed
2150 * through I/O APICs. Also IRQ0 has to be enabled in
2151 * the 8259A which implies the virtual wire has to be
2152 * disabled in the local APIC.
2154 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2157 enable_8259A_irq(0);
2159 pin1 = find_isa_irq_pin(0, mp_INT);
2160 pin2 = find_isa_irq_pin(0, mp_ExtINT);
2162 printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
2166 * Ok, does IRQ0 through the IOAPIC work?
2168 unmask_IO_APIC_irq(0);
2169 if (timer_irq_works()) {
2170 if (nmi_watchdog == NMI_IO_APIC) {
2171 disable_8259A_irq(0);
2173 enable_8259A_irq(0);
2174 check_nmi_watchdog();
2178 clear_IO_APIC_pin(0, pin1);
2179 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2182 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2184 printk("\n..... (found pin %d) ...", pin2);
2186 * legacy devices should be connected to IO APIC #0
2188 setup_ExtINT_IRQ0_pin(pin2, vector);
2189 if (timer_irq_works()) {
2192 replace_pin_at_irq(0, 0, pin1, 0, pin2);
2194 add_pin_to_irq(0, 0, pin2);
2195 if (nmi_watchdog == NMI_IO_APIC) {
2197 check_nmi_watchdog();
2202 * Cleanup, just in case ...
2204 clear_IO_APIC_pin(0, pin2);
2206 printk(" failed.\n");
2208 if (nmi_watchdog == NMI_IO_APIC) {
2209 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2213 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2215 disable_8259A_irq(0);
2216 irq_desc[0].handler = &lapic_irq_type;
2217 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2218 enable_8259A_irq(0);
2220 if (timer_irq_works()) {
2221 printk(" works.\n");
2224 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2225 printk(" failed.\n");
2227 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2232 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2234 unlock_ExtINT_logic();
2236 if (timer_irq_works()) {
2237 printk(" works.\n");
2240 printk(" failed :(.\n");
2241 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2242 "report. Then try booting with the 'noapic' option");
2247 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2248 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2249 * Linux doesn't really care, as it's not actually used
2250 * for any interrupt handling anyway.
2252 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2254 void __init setup_IO_APIC(void)
2259 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2261 io_apic_irqs = ~PIC_IRQS;
2263 printk("ENABLING IO-APIC IRQs\n");
2266 * Set up IO-APIC IRQ routing.
2269 setup_ioapic_ids_from_mpc();
2271 setup_IO_APIC_irqs();
2272 init_IO_APIC_traps();
2279 * Called after all the initialization is done. If we didnt find any
2280 * APIC bugs then we can allow the modify fast path
2283 static int __init io_apic_bug_finalize(void)
2285 if(sis_apic_bug == -1)
2290 late_initcall(io_apic_bug_finalize);
2292 struct sysfs_ioapic_data {
2293 struct sys_device dev;
2294 struct IO_APIC_route_entry entry[0];
2296 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2298 static int ioapic_suspend(struct sys_device *dev, u32 state)
2300 struct IO_APIC_route_entry *entry;
2301 struct sysfs_ioapic_data *data;
2302 unsigned long flags;
2305 data = container_of(dev, struct sysfs_ioapic_data, dev);
2306 entry = data->entry;
2307 spin_lock_irqsave(&ioapic_lock, flags);
2308 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2309 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2310 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2312 spin_unlock_irqrestore(&ioapic_lock, flags);
2317 static int ioapic_resume(struct sys_device *dev)
2319 struct IO_APIC_route_entry *entry;
2320 struct sysfs_ioapic_data *data;
2321 unsigned long flags;
2322 union IO_APIC_reg_00 reg_00;
2325 data = container_of(dev, struct sysfs_ioapic_data, dev);
2326 entry = data->entry;
2328 spin_lock_irqsave(&ioapic_lock, flags);
2329 reg_00.raw = io_apic_read(dev->id, 0);
2330 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2331 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2332 io_apic_write(dev->id, 0, reg_00.raw);
2334 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2335 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2336 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2338 spin_unlock_irqrestore(&ioapic_lock, flags);
2343 static struct sysdev_class ioapic_sysdev_class = {
2344 set_kset_name("ioapic"),
2345 .suspend = ioapic_suspend,
2346 .resume = ioapic_resume,
2349 static int __init ioapic_init_sysfs(void)
2351 struct sys_device * dev;
2352 int i, size, error = 0;
2354 error = sysdev_class_register(&ioapic_sysdev_class);
2358 for (i = 0; i < nr_ioapics; i++ ) {
2359 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2360 * sizeof(struct IO_APIC_route_entry);
2361 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2362 if (!mp_ioapic_data[i]) {
2363 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2366 memset(mp_ioapic_data[i], 0, size);
2367 dev = &mp_ioapic_data[i]->dev;
2369 dev->cls = &ioapic_sysdev_class;
2370 error = sysdev_register(dev);
2372 kfree(mp_ioapic_data[i]);
2373 mp_ioapic_data[i] = NULL;
2374 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2382 device_initcall(ioapic_init_sysfs);
2384 /* --------------------------------------------------------------------------
2385 ACPI-based IOAPIC Configuration
2386 -------------------------------------------------------------------------- */
2388 #ifdef CONFIG_ACPI_BOOT
2390 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2392 union IO_APIC_reg_00 reg_00;
2393 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2395 unsigned long flags;
2399 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2400 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2401 * supports up to 16 on one shared APIC bus.
2403 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2404 * advantage of new APIC bus architecture.
2407 if (physids_empty(apic_id_map))
2408 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2410 spin_lock_irqsave(&ioapic_lock, flags);
2411 reg_00.raw = io_apic_read(ioapic, 0);
2412 spin_unlock_irqrestore(&ioapic_lock, flags);
2414 if (apic_id >= get_physical_broadcast()) {
2415 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2416 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2417 apic_id = reg_00.bits.ID;
2421 * Every APIC in a system must have a unique ID or we get lots of nice
2422 * 'stuck on smp_invalidate_needed IPI wait' messages.
2424 if (check_apicid_used(apic_id_map, apic_id)) {
2426 for (i = 0; i < get_physical_broadcast(); i++) {
2427 if (!check_apicid_used(apic_id_map, i))
2431 if (i == get_physical_broadcast())
2432 panic("Max apic_id exceeded!\n");
2434 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2435 "trying %d\n", ioapic, apic_id, i);
2440 tmp = apicid_to_cpu_present(apic_id);
2441 physids_or(apic_id_map, apic_id_map, tmp);
2443 if (reg_00.bits.ID != apic_id) {
2444 reg_00.bits.ID = apic_id;
2446 spin_lock_irqsave(&ioapic_lock, flags);
2447 io_apic_write(ioapic, 0, reg_00.raw);
2448 reg_00.raw = io_apic_read(ioapic, 0);
2449 spin_unlock_irqrestore(&ioapic_lock, flags);
2452 if (reg_00.bits.ID != apic_id)
2453 panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
2456 apic_printk(APIC_VERBOSE, KERN_INFO
2457 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2463 int __init io_apic_get_version (int ioapic)
2465 union IO_APIC_reg_01 reg_01;
2466 unsigned long flags;
2468 spin_lock_irqsave(&ioapic_lock, flags);
2469 reg_01.raw = io_apic_read(ioapic, 1);
2470 spin_unlock_irqrestore(&ioapic_lock, flags);
2472 return reg_01.bits.version;
2476 int __init io_apic_get_redir_entries (int ioapic)
2478 union IO_APIC_reg_01 reg_01;
2479 unsigned long flags;
2481 spin_lock_irqsave(&ioapic_lock, flags);
2482 reg_01.raw = io_apic_read(ioapic, 1);
2483 spin_unlock_irqrestore(&ioapic_lock, flags);
2485 return reg_01.bits.entries;
2489 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2491 struct IO_APIC_route_entry entry;
2492 unsigned long flags;
2494 if (!IO_APIC_IRQ(irq)) {
2495 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2501 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2502 * Note that we mask (disable) IRQs now -- these get enabled when the
2503 * corresponding device driver registers for this IRQ.
2506 memset(&entry,0,sizeof(entry));
2508 entry.delivery_mode = INT_DELIVERY_MODE;
2509 entry.dest_mode = INT_DEST_MODE;
2510 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2511 entry.trigger = edge_level;
2512 entry.polarity = active_high_low;
2516 * IRQs < 16 are already in the irq_2_pin[] map
2519 add_pin_to_irq(irq, ioapic, pin);
2521 entry.vector = assign_irq_vector(irq);
2523 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2524 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2525 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2526 edge_level, active_high_low);
2528 ioapic_register_intr(irq, entry.vector, edge_level);
2530 if (!ioapic && (irq < 16))
2531 disable_8259A_irq(irq);
2533 spin_lock_irqsave(&ioapic_lock, flags);
2534 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2535 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2536 spin_unlock_irqrestore(&ioapic_lock, flags);
2541 #endif /*CONFIG_ACPI_BOOT*/