2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/config.h>
30 #include <linux/smp_lock.h>
31 #include <linux/mc146818rtc.h>
32 #include <linux/compiler.h>
33 #include <linux/acpi.h>
35 #include <linux/sysdev.h>
39 #include <asm/timer.h>
41 #include <mach_apic.h>
45 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
48 * Is the SiS APIC rmw bug present ?
49 * -1 = don't know, 0 = no, 1 = yes
51 int sis_apic_bug = -1;
54 * # of IRQ routing registers
56 int nr_ioapic_registers[MAX_IO_APICS];
59 * Rough estimation of how many shared IRQs there are, can
62 #define MAX_PLUS_SHARED_IRQS NR_IRQS
63 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
66 * This is performance-critical, we want to do it O(1)
68 * the indexing order of this array favors 1:1 mappings
69 * between pins and IRQs.
72 static struct irq_pin_list {
74 } irq_2_pin[PIN_MAP_SIZE];
76 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
78 #define vector_to_irq(vector) \
79 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
81 #define vector_to_irq(vector) (vector)
85 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
86 * shared ISA-space IRQs, so we have to support them. We are super
87 * fast in the common case, and fast for shared ISA-space IRQs.
89 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
91 static int first_free_entry = NR_IRQS;
92 struct irq_pin_list *entry = irq_2_pin + irq;
95 entry = irq_2_pin + entry->next;
97 if (entry->pin != -1) {
98 entry->next = first_free_entry;
99 entry = irq_2_pin + entry->next;
100 if (++first_free_entry >= PIN_MAP_SIZE)
101 panic("io_apic.c: whoops");
108 * Reroute an IRQ to a different pin.
110 static void __init replace_pin_at_irq(unsigned int irq,
111 int oldapic, int oldpin,
112 int newapic, int newpin)
114 struct irq_pin_list *entry = irq_2_pin + irq;
117 if (entry->apic == oldapic && entry->pin == oldpin) {
118 entry->apic = newapic;
123 entry = irq_2_pin + entry->next;
127 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
129 struct irq_pin_list *entry = irq_2_pin + irq;
130 unsigned int pin, reg;
136 reg = io_apic_read(entry->apic, 0x10 + pin*2);
139 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
142 entry = irq_2_pin + entry->next;
147 static void __mask_IO_APIC_irq (unsigned int irq)
149 __modify_IO_APIC_irq(irq, 0x00010000, 0);
153 static void __unmask_IO_APIC_irq (unsigned int irq)
155 __modify_IO_APIC_irq(irq, 0, 0x00010000);
158 /* mask = 1, trigger = 0 */
159 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
161 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
164 /* mask = 0, trigger = 1 */
165 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
167 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
170 static void mask_IO_APIC_irq (unsigned int irq)
174 spin_lock_irqsave(&ioapic_lock, flags);
175 __mask_IO_APIC_irq(irq);
176 spin_unlock_irqrestore(&ioapic_lock, flags);
179 static void unmask_IO_APIC_irq (unsigned int irq)
183 spin_lock_irqsave(&ioapic_lock, flags);
184 __unmask_IO_APIC_irq(irq);
185 spin_unlock_irqrestore(&ioapic_lock, flags);
188 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
190 struct IO_APIC_route_entry entry;
193 /* Check delivery_mode to be sure we're not clearing an SMI pin */
194 spin_lock_irqsave(&ioapic_lock, flags);
195 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
196 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
197 spin_unlock_irqrestore(&ioapic_lock, flags);
198 if (entry.delivery_mode == dest_SMI)
202 * Disable it in the IO-APIC irq-routing table:
204 memset(&entry, 0, sizeof(entry));
206 spin_lock_irqsave(&ioapic_lock, flags);
207 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
208 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
209 spin_unlock_irqrestore(&ioapic_lock, flags);
212 static void clear_IO_APIC (void)
216 for (apic = 0; apic < nr_ioapics; apic++)
217 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
218 clear_IO_APIC_pin(apic, pin);
221 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
225 struct irq_pin_list *entry = irq_2_pin + irq;
226 unsigned int apicid_value;
228 apicid_value = cpu_mask_to_apicid(cpumask);
229 /* Prepare to do the io_apic_write */
230 apicid_value = apicid_value << 24;
231 spin_lock_irqsave(&ioapic_lock, flags);
236 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
239 entry = irq_2_pin + entry->next;
241 spin_unlock_irqrestore(&ioapic_lock, flags);
244 #if defined(CONFIG_IRQBALANCE)
245 # include <asm/processor.h> /* kernel_thread() */
246 # include <linux/kernel_stat.h> /* kstat */
247 # include <linux/slab.h> /* kmalloc() */
248 # include <linux/timer.h> /* time_after() */
250 # ifdef CONFIG_BALANCED_IRQ_DEBUG
251 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
252 # define Dprintk(x...) do { TDprintk(x); } while (0)
254 # define TDprintk(x...)
255 # define Dprintk(x...)
258 extern cpumask_t irq_affinity[NR_IRQS];
260 cpumask_t __cacheline_aligned pending_irq_balance_cpumask[NR_IRQS];
262 #define IRQBALANCE_CHECK_ARCH -999
263 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
264 static int physical_balance = 0;
266 struct irq_cpu_info {
267 unsigned long * last_irq;
268 unsigned long * irq_delta;
270 } irq_cpu_data[NR_CPUS];
272 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
273 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
274 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
276 #define IDLE_ENOUGH(cpu,now) \
277 (idle_cpu(cpu) && ((now) - irq_stat[(cpu)].idle_timestamp > 1))
279 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
281 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
283 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
284 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
285 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
286 #define BALANCED_IRQ_LESS_DELTA (HZ)
288 long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
290 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
291 unsigned long now, int direction)
299 if (unlikely(cpu == curr_cpu))
302 if (direction == 1) {
311 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
312 (search_idle && !IDLE_ENOUGH(cpu,now)));
317 static inline void balance_irq(int cpu, int irq)
319 unsigned long now = jiffies;
320 cpumask_t allowed_mask;
321 unsigned int new_cpu;
323 if (irqbalance_disabled)
326 cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
327 new_cpu = move(cpu, allowed_mask, now, 1);
328 if (cpu != new_cpu) {
329 irq_desc_t *desc = irq_desc + irq;
332 spin_lock_irqsave(&desc->lock, flags);
333 pending_irq_balance_cpumask[irq] = cpumask_of_cpu(new_cpu);
334 spin_unlock_irqrestore(&desc->lock, flags);
338 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
341 Dprintk("Rotating IRQs among CPUs.\n");
342 for (i = 0; i < NR_CPUS; i++) {
343 for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
344 if (!irq_desc[j].action)
346 /* Is it a significant load ? */
347 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
348 useful_load_threshold)
353 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
354 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
358 static void do_irq_balance(void)
361 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
362 unsigned long move_this_load = 0;
363 int max_loaded = 0, min_loaded = 0;
365 unsigned long useful_load_threshold = balanced_irq_interval + 10;
367 int tmp_loaded, first_attempt = 1;
368 unsigned long tmp_cpu_irq;
369 unsigned long imbalance = 0;
370 cpumask_t allowed_mask, target_cpu_mask, tmp;
372 for (i = 0; i < NR_CPUS; i++) {
377 package_index = CPU_TO_PACKAGEINDEX(i);
378 for (j = 0; j < NR_IRQS; j++) {
379 unsigned long value_now, delta;
380 /* Is this an active IRQ? */
381 if (!irq_desc[j].action)
383 if ( package_index == i )
384 IRQ_DELTA(package_index,j) = 0;
385 /* Determine the total count per processor per IRQ */
386 value_now = (unsigned long) kstat_cpu(i).irqs[j];
388 /* Determine the activity per processor per IRQ */
389 delta = value_now - LAST_CPU_IRQ(i,j);
391 /* Update last_cpu_irq[][] for the next time */
392 LAST_CPU_IRQ(i,j) = value_now;
394 /* Ignore IRQs whose rate is less than the clock */
395 if (delta < useful_load_threshold)
397 /* update the load for the processor or package total */
398 IRQ_DELTA(package_index,j) += delta;
400 /* Keep track of the higher numbered sibling as well */
401 if (i != package_index)
404 * We have sibling A and sibling B in the package
406 * cpu_irq[A] = load for cpu A + load for cpu B
407 * cpu_irq[B] = load for cpu B
409 CPU_IRQ(package_index) += delta;
412 /* Find the least loaded processor package */
413 for (i = 0; i < NR_CPUS; i++) {
416 if (i != CPU_TO_PACKAGEINDEX(i))
418 if (min_cpu_irq > CPU_IRQ(i)) {
419 min_cpu_irq = CPU_IRQ(i);
423 max_cpu_irq = ULONG_MAX;
426 /* Look for heaviest loaded processor.
427 * We may come back to get the next heaviest loaded processor.
428 * Skip processors with trivial loads.
432 for (i = 0; i < NR_CPUS; i++) {
435 if (i != CPU_TO_PACKAGEINDEX(i))
437 if (max_cpu_irq <= CPU_IRQ(i))
439 if (tmp_cpu_irq < CPU_IRQ(i)) {
440 tmp_cpu_irq = CPU_IRQ(i);
445 if (tmp_loaded == -1) {
446 /* In the case of small number of heavy interrupt sources,
447 * loading some of the cpus too much. We use Ingo's original
448 * approach to rotate them around.
450 if (!first_attempt && imbalance >= useful_load_threshold) {
451 rotate_irqs_among_cpus(useful_load_threshold);
454 goto not_worth_the_effort;
457 first_attempt = 0; /* heaviest search */
458 max_cpu_irq = tmp_cpu_irq; /* load */
459 max_loaded = tmp_loaded; /* processor */
460 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
462 Dprintk("max_loaded cpu = %d\n", max_loaded);
463 Dprintk("min_loaded cpu = %d\n", min_loaded);
464 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
465 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
466 Dprintk("load imbalance = %lu\n", imbalance);
468 /* if imbalance is less than approx 10% of max load, then
469 * observe diminishing returns action. - quit
471 if (imbalance < (max_cpu_irq >> 3)) {
472 Dprintk("Imbalance too trivial\n");
473 goto not_worth_the_effort;
477 /* if we select an IRQ to move that can't go where we want, then
478 * see if there is another one to try.
482 for (j = 0; j < NR_IRQS; j++) {
483 /* Is this an active IRQ? */
484 if (!irq_desc[j].action)
486 if (imbalance <= IRQ_DELTA(max_loaded,j))
488 /* Try to find the IRQ that is closest to the imbalance
489 * without going over.
491 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
492 move_this_load = IRQ_DELTA(max_loaded,j);
496 if (selected_irq == -1) {
500 imbalance = move_this_load;
502 /* For physical_balance case, we accumlated both load
503 * values in the one of the siblings cpu_irq[],
504 * to use the same code for physical and logical processors
505 * as much as possible.
507 * NOTE: the cpu_irq[] array holds the sum of the load for
508 * sibling A and sibling B in the slot for the lowest numbered
509 * sibling (A), _AND_ the load for sibling B in the slot for
510 * the higher numbered sibling.
512 * We seek the least loaded sibling by making the comparison
515 load = CPU_IRQ(min_loaded) >> 1;
516 for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
517 if (load > CPU_IRQ(j)) {
518 /* This won't change cpu_sibling_map[min_loaded] */
524 cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
525 target_cpu_mask = cpumask_of_cpu(min_loaded);
526 cpus_and(tmp, target_cpu_mask, allowed_mask);
528 if (!cpus_empty(tmp)) {
529 irq_desc_t *desc = irq_desc + selected_irq;
532 Dprintk("irq = %d moved to cpu = %d\n",
533 selected_irq, min_loaded);
534 /* mark for change destination */
535 spin_lock_irqsave(&desc->lock, flags);
536 pending_irq_balance_cpumask[selected_irq] =
537 cpumask_of_cpu(min_loaded);
538 spin_unlock_irqrestore(&desc->lock, flags);
539 /* Since we made a change, come back sooner to
540 * check for more variation.
542 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
543 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
548 not_worth_the_effort:
550 * if we did not find an IRQ to move, then adjust the time interval
553 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
554 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
555 Dprintk("IRQ worth rotating not found\n");
559 static int balanced_irq(void *unused)
562 unsigned long prev_balance_time = jiffies;
563 long time_remaining = balanced_irq_interval;
567 /* push everything to CPU 0 to give us a starting point. */
568 for (i = 0 ; i < NR_IRQS ; i++) {
569 pending_irq_balance_cpumask[i] = cpumask_of_cpu(0);
573 set_current_state(TASK_INTERRUPTIBLE);
574 time_remaining = schedule_timeout(time_remaining);
575 if (time_after(jiffies,
576 prev_balance_time+balanced_irq_interval)) {
578 prev_balance_time = jiffies;
579 time_remaining = balanced_irq_interval;
585 static int __init balanced_irq_init(void)
588 struct cpuinfo_x86 *c;
591 cpus_shift_right(tmp, cpu_online_map, 2);
593 /* When not overwritten by the command line ask subarchitecture. */
594 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
595 irqbalance_disabled = NO_BALANCE_IRQ;
596 if (irqbalance_disabled)
599 /* disable irqbalance completely if there is only one processor online */
600 if (num_online_cpus() < 2) {
601 irqbalance_disabled = 1;
605 * Enable physical balance only if more than 1 physical processor
608 if (smp_num_siblings > 1 && !cpus_empty(tmp))
609 physical_balance = 1;
611 for (i = 0; i < NR_CPUS; i++) {
614 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
615 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
616 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
617 printk(KERN_ERR "balanced_irq_init: out of memory");
620 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
621 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
624 printk(KERN_INFO "Starting balanced_irq\n");
625 if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
628 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
630 for (i = 0; i < NR_CPUS; i++) {
631 if(irq_cpu_data[i].irq_delta)
632 kfree(irq_cpu_data[i].irq_delta);
633 if(irq_cpu_data[i].last_irq)
634 kfree(irq_cpu_data[i].last_irq);
639 int __init irqbalance_disable(char *str)
641 irqbalance_disabled = 1;
645 __setup("noirqbalance", irqbalance_disable);
647 static inline void move_irq(int irq)
649 /* note - we hold the desc->lock */
650 if (unlikely(!cpus_empty(pending_irq_balance_cpumask[irq]))) {
651 set_ioapic_affinity_irq(irq, pending_irq_balance_cpumask[irq]);
652 cpus_clear(pending_irq_balance_cpumask[irq]);
656 late_initcall(balanced_irq_init);
658 #else /* !CONFIG_IRQBALANCE */
659 static inline void move_irq(int irq) { }
660 #endif /* CONFIG_IRQBALANCE */
663 void fastcall send_IPI_self(int vector)
670 apic_wait_icr_idle();
671 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
673 * Send the IPI. The write to APIC_ICR fires this off.
675 apic_write_around(APIC_ICR, cfg);
677 #endif /* !CONFIG_SMP */
681 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
682 * specific CPU-side IRQs.
686 int pirq_entries [MAX_PIRQS];
688 int skip_ioapic_setup;
690 static int __init ioapic_setup(char *str)
692 skip_ioapic_setup = 1;
696 __setup("noapic", ioapic_setup);
698 static int __init ioapic_pirq_setup(char *str)
701 int ints[MAX_PIRQS+1];
703 get_options(str, ARRAY_SIZE(ints), ints);
705 for (i = 0; i < MAX_PIRQS; i++)
706 pirq_entries[i] = -1;
709 apic_printk(APIC_VERBOSE, KERN_INFO
710 "PIRQ redirection, working around broken MP-BIOS.\n");
712 if (ints[0] < MAX_PIRQS)
715 for (i = 0; i < max; i++) {
716 apic_printk(APIC_VERBOSE, KERN_DEBUG
717 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
719 * PIRQs are mapped upside down, usually.
721 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
726 __setup("pirq=", ioapic_pirq_setup);
729 * Find the IRQ entry number of a certain pin.
731 static int find_irq_entry(int apic, int pin, int type)
735 for (i = 0; i < mp_irq_entries; i++)
736 if (mp_irqs[i].mpc_irqtype == type &&
737 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
738 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
739 mp_irqs[i].mpc_dstirq == pin)
746 * Find the pin to which IRQ[irq] (ISA) is connected
748 static int find_isa_irq_pin(int irq, int type)
752 for (i = 0; i < mp_irq_entries; i++) {
753 int lbus = mp_irqs[i].mpc_srcbus;
755 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
756 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
757 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
758 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
760 (mp_irqs[i].mpc_irqtype == type) &&
761 (mp_irqs[i].mpc_srcbusirq == irq))
763 return mp_irqs[i].mpc_dstirq;
769 * Find a specific PCI IRQ entry.
770 * Not an __init, possibly needed by modules
772 static int pin_2_irq(int idx, int apic, int pin);
774 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
776 int apic, i, best_guess = -1;
778 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
779 "slot:%d, pin:%d.\n", bus, slot, pin);
780 if (mp_bus_id_to_pci_bus[bus] == -1) {
781 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
784 for (i = 0; i < mp_irq_entries; i++) {
785 int lbus = mp_irqs[i].mpc_srcbus;
787 for (apic = 0; apic < nr_ioapics; apic++)
788 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
789 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
792 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
793 !mp_irqs[i].mpc_irqtype &&
795 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
796 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
798 if (!(apic || IO_APIC_IRQ(irq)))
801 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
804 * Use the first all-but-pin matching entry as a
805 * best-guess fuzzy result for broken mptables.
815 * This function currently is only a helper for the i386 smp boot process where
816 * we need to reprogram the ioredtbls to cater for the cpus which have come online
817 * so mask in all cases should simply be TARGET_CPUS
819 void __init setup_ioapic_dest(void)
821 int pin, ioapic, irq, irq_entry;
823 if (skip_ioapic_setup == 1)
826 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
827 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
828 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
831 irq = pin_2_irq(irq_entry, ioapic, pin);
832 set_ioapic_affinity_irq(irq, TARGET_CPUS);
839 * EISA Edge/Level control register, ELCR
841 static int EISA_ELCR(unsigned int irq)
844 unsigned int port = 0x4d0 + (irq >> 3);
845 return (inb(port) >> (irq & 7)) & 1;
847 apic_printk(APIC_VERBOSE, KERN_INFO
848 "Broken MPtable reports ISA irq %d\n", irq);
852 /* EISA interrupts are always polarity zero and can be edge or level
853 * trigger depending on the ELCR value. If an interrupt is listed as
854 * EISA conforming in the MP table, that means its trigger type must
855 * be read in from the ELCR */
857 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
858 #define default_EISA_polarity(idx) (0)
860 /* ISA interrupts are always polarity zero edge triggered,
861 * when listed as conforming in the MP table. */
863 #define default_ISA_trigger(idx) (0)
864 #define default_ISA_polarity(idx) (0)
866 /* PCI interrupts are always polarity one level triggered,
867 * when listed as conforming in the MP table. */
869 #define default_PCI_trigger(idx) (1)
870 #define default_PCI_polarity(idx) (1)
872 /* MCA interrupts are always polarity zero level triggered,
873 * when listed as conforming in the MP table. */
875 #define default_MCA_trigger(idx) (1)
876 #define default_MCA_polarity(idx) (0)
878 /* NEC98 interrupts are always polarity zero edge triggered,
879 * when listed as conforming in the MP table. */
881 #define default_NEC98_trigger(idx) (0)
882 #define default_NEC98_polarity(idx) (0)
884 static int __init MPBIOS_polarity(int idx)
886 int bus = mp_irqs[idx].mpc_srcbus;
890 * Determine IRQ line polarity (high active or low active):
892 switch (mp_irqs[idx].mpc_irqflag & 3)
894 case 0: /* conforms, ie. bus-type dependent polarity */
896 switch (mp_bus_id_to_type[bus])
898 case MP_BUS_ISA: /* ISA pin */
900 polarity = default_ISA_polarity(idx);
903 case MP_BUS_EISA: /* EISA pin */
905 polarity = default_EISA_polarity(idx);
908 case MP_BUS_PCI: /* PCI pin */
910 polarity = default_PCI_polarity(idx);
913 case MP_BUS_MCA: /* MCA pin */
915 polarity = default_MCA_polarity(idx);
918 case MP_BUS_NEC98: /* NEC 98 pin */
920 polarity = default_NEC98_polarity(idx);
925 printk(KERN_WARNING "broken BIOS!!\n");
932 case 1: /* high active */
937 case 2: /* reserved */
939 printk(KERN_WARNING "broken BIOS!!\n");
943 case 3: /* low active */
948 default: /* invalid */
950 printk(KERN_WARNING "broken BIOS!!\n");
958 static int MPBIOS_trigger(int idx)
960 int bus = mp_irqs[idx].mpc_srcbus;
964 * Determine IRQ trigger mode (edge or level sensitive):
966 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
968 case 0: /* conforms, ie. bus-type dependent */
970 switch (mp_bus_id_to_type[bus])
972 case MP_BUS_ISA: /* ISA pin */
974 trigger = default_ISA_trigger(idx);
977 case MP_BUS_EISA: /* EISA pin */
979 trigger = default_EISA_trigger(idx);
982 case MP_BUS_PCI: /* PCI pin */
984 trigger = default_PCI_trigger(idx);
987 case MP_BUS_MCA: /* MCA pin */
989 trigger = default_MCA_trigger(idx);
992 case MP_BUS_NEC98: /* NEC 98 pin */
994 trigger = default_NEC98_trigger(idx);
999 printk(KERN_WARNING "broken BIOS!!\n");
1011 case 2: /* reserved */
1013 printk(KERN_WARNING "broken BIOS!!\n");
1022 default: /* invalid */
1024 printk(KERN_WARNING "broken BIOS!!\n");
1032 static inline int irq_polarity(int idx)
1034 return MPBIOS_polarity(idx);
1037 static inline int irq_trigger(int idx)
1039 return MPBIOS_trigger(idx);
1042 static int pin_2_irq(int idx, int apic, int pin)
1045 int bus = mp_irqs[idx].mpc_srcbus;
1048 * Debugging check, we are in big trouble if this message pops up!
1050 if (mp_irqs[idx].mpc_dstirq != pin)
1051 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1053 switch (mp_bus_id_to_type[bus])
1055 case MP_BUS_ISA: /* ISA pin */
1060 irq = mp_irqs[idx].mpc_srcbusirq;
1063 case MP_BUS_PCI: /* PCI pin */
1066 * PCI IRQs are mapped in order
1070 irq += nr_ioapic_registers[i++];
1072 if ((!apic) && (irq < 16))
1078 printk(KERN_ERR "unknown bus type %d.\n",bus);
1085 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1087 if ((pin >= 16) && (pin <= 23)) {
1088 if (pirq_entries[pin-16] != -1) {
1089 if (!pirq_entries[pin-16]) {
1090 apic_printk(APIC_VERBOSE, KERN_DEBUG
1091 "disabling PIRQ%d\n", pin-16);
1093 irq = pirq_entries[pin-16];
1094 apic_printk(APIC_VERBOSE, KERN_DEBUG
1095 "using PIRQ%d -> IRQ %d\n",
1103 static inline int IO_APIC_irq_trigger(int irq)
1107 for (apic = 0; apic < nr_ioapics; apic++) {
1108 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1109 idx = find_irq_entry(apic,pin,mp_INT);
1110 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1111 return irq_trigger(idx);
1115 * nonexistent IRQs are edge default
1120 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1121 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
1123 int assign_irq_vector(int irq)
1125 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1127 BUG_ON(irq >= NR_IRQ_VECTORS);
1128 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1129 return IO_APIC_VECTOR(irq);
1131 current_vector += 8;
1132 if (current_vector == SYSCALL_VECTOR)
1135 if (current_vector >= FIRST_SYSTEM_VECTOR) {
1139 current_vector = FIRST_DEVICE_VECTOR + offset;
1142 vector_irq[current_vector] = irq;
1143 if (irq != AUTO_ASSIGN)
1144 IO_APIC_VECTOR(irq) = current_vector;
1146 return current_vector;
1149 static struct hw_interrupt_type ioapic_level_type;
1150 static struct hw_interrupt_type ioapic_edge_type;
1152 #define IOAPIC_AUTO -1
1153 #define IOAPIC_EDGE 0
1154 #define IOAPIC_LEVEL 1
1156 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1158 if (use_pci_vector() && !platform_legacy_irq(irq)) {
1159 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1160 trigger == IOAPIC_LEVEL)
1161 irq_desc[vector].handler = &ioapic_level_type;
1163 irq_desc[vector].handler = &ioapic_edge_type;
1164 set_intr_gate(vector, interrupt[vector]);
1166 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1167 trigger == IOAPIC_LEVEL)
1168 irq_desc[irq].handler = &ioapic_level_type;
1170 irq_desc[irq].handler = &ioapic_edge_type;
1171 set_intr_gate(vector, interrupt[irq]);
1175 void __init setup_IO_APIC_irqs(void)
1177 struct IO_APIC_route_entry entry;
1178 int apic, pin, idx, irq, first_notcon = 1, vector;
1179 unsigned long flags;
1181 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1183 for (apic = 0; apic < nr_ioapics; apic++) {
1184 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1187 * add it to the IO-APIC irq-routing table:
1189 memset(&entry,0,sizeof(entry));
1191 entry.delivery_mode = INT_DELIVERY_MODE;
1192 entry.dest_mode = INT_DEST_MODE;
1193 entry.mask = 0; /* enable IRQ */
1194 entry.dest.logical.logical_dest =
1195 cpu_mask_to_apicid(TARGET_CPUS);
1197 idx = find_irq_entry(apic,pin,mp_INT);
1200 apic_printk(APIC_VERBOSE, KERN_DEBUG
1201 " IO-APIC (apicid-pin) %d-%d",
1202 mp_ioapics[apic].mpc_apicid,
1206 apic_printk(APIC_VERBOSE, ", %d-%d",
1207 mp_ioapics[apic].mpc_apicid, pin);
1211 entry.trigger = irq_trigger(idx);
1212 entry.polarity = irq_polarity(idx);
1214 if (irq_trigger(idx)) {
1219 irq = pin_2_irq(idx, apic, pin);
1221 * skip adding the timer int on secondary nodes, which causes
1222 * a small but painful rift in the time-space continuum
1224 if (multi_timer_check(apic, irq))
1227 add_pin_to_irq(irq, apic, pin);
1229 if (!apic && !IO_APIC_IRQ(irq))
1232 if (IO_APIC_IRQ(irq)) {
1233 vector = assign_irq_vector(irq);
1234 entry.vector = vector;
1235 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1237 if (!apic && (irq < 16))
1238 disable_8259A_irq(irq);
1240 spin_lock_irqsave(&ioapic_lock, flags);
1241 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1242 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1243 spin_unlock_irqrestore(&ioapic_lock, flags);
1248 apic_printk(APIC_VERBOSE, " not connected.\n");
1252 * Set up the 8259A-master output pin:
1254 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
1256 struct IO_APIC_route_entry entry;
1257 unsigned long flags;
1259 memset(&entry,0,sizeof(entry));
1261 disable_8259A_irq(0);
1264 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1267 * We use logical delivery to get the timer IRQ
1270 entry.dest_mode = INT_DEST_MODE;
1271 entry.mask = 0; /* unmask IRQ now */
1272 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1273 entry.delivery_mode = INT_DELIVERY_MODE;
1276 entry.vector = vector;
1279 * The timer IRQ doesn't have to know that behind the
1280 * scene we have a 8259A-master in AEOI mode ...
1282 irq_desc[0].handler = &ioapic_edge_type;
1285 * Add it to the IO-APIC irq-routing table:
1287 spin_lock_irqsave(&ioapic_lock, flags);
1288 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1289 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1290 spin_unlock_irqrestore(&ioapic_lock, flags);
1292 enable_8259A_irq(0);
1295 static inline void UNEXPECTED_IO_APIC(void)
1299 void __init print_IO_APIC(void)
1302 union IO_APIC_reg_00 reg_00;
1303 union IO_APIC_reg_01 reg_01;
1304 union IO_APIC_reg_02 reg_02;
1305 union IO_APIC_reg_03 reg_03;
1306 unsigned long flags;
1308 if (apic_verbosity == APIC_QUIET)
1311 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1312 for (i = 0; i < nr_ioapics; i++)
1313 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1314 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1317 * We are a bit conservative about what we expect. We have to
1318 * know about every hardware change ASAP.
1320 printk(KERN_INFO "testing the IO APIC.......................\n");
1322 for (apic = 0; apic < nr_ioapics; apic++) {
1324 spin_lock_irqsave(&ioapic_lock, flags);
1325 reg_00.raw = io_apic_read(apic, 0);
1326 reg_01.raw = io_apic_read(apic, 1);
1327 if (reg_01.bits.version >= 0x10)
1328 reg_02.raw = io_apic_read(apic, 2);
1329 if (reg_01.bits.version >= 0x20)
1330 reg_03.raw = io_apic_read(apic, 3);
1331 spin_unlock_irqrestore(&ioapic_lock, flags);
1333 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1334 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1335 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1336 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1337 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1338 if (reg_00.bits.ID >= get_physical_broadcast())
1339 UNEXPECTED_IO_APIC();
1340 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1341 UNEXPECTED_IO_APIC();
1343 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1344 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1345 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1346 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1347 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1348 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1349 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1350 (reg_01.bits.entries != 0x2E) &&
1351 (reg_01.bits.entries != 0x3F)
1353 UNEXPECTED_IO_APIC();
1355 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1356 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1357 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1358 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1359 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1360 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1361 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1363 UNEXPECTED_IO_APIC();
1364 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1365 UNEXPECTED_IO_APIC();
1368 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1369 * but the value of reg_02 is read as the previous read register
1370 * value, so ignore it if reg_02 == reg_01.
1372 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1373 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1374 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1375 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1376 UNEXPECTED_IO_APIC();
1380 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1381 * or reg_03, but the value of reg_0[23] is read as the previous read
1382 * register value, so ignore it if reg_03 == reg_0[12].
1384 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1385 reg_03.raw != reg_01.raw) {
1386 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1387 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1388 if (reg_03.bits.__reserved_1)
1389 UNEXPECTED_IO_APIC();
1392 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1394 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1395 " Stat Dest Deli Vect: \n");
1397 for (i = 0; i <= reg_01.bits.entries; i++) {
1398 struct IO_APIC_route_entry entry;
1400 spin_lock_irqsave(&ioapic_lock, flags);
1401 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1402 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1403 spin_unlock_irqrestore(&ioapic_lock, flags);
1405 printk(KERN_DEBUG " %02x %03X %02X ",
1407 entry.dest.logical.logical_dest,
1408 entry.dest.physical.physical_dest
1411 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1416 entry.delivery_status,
1418 entry.delivery_mode,
1423 if (use_pci_vector())
1424 printk(KERN_INFO "Using vector-based indexing\n");
1425 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1426 for (i = 0; i < NR_IRQS; i++) {
1427 struct irq_pin_list *entry = irq_2_pin + i;
1430 if (use_pci_vector() && !platform_legacy_irq(i))
1431 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1433 printk(KERN_DEBUG "IRQ%d ", i);
1435 printk("-> %d:%d", entry->apic, entry->pin);
1438 entry = irq_2_pin + entry->next;
1443 printk(KERN_INFO ".................................... done.\n");
1448 static void print_APIC_bitfield (int base)
1453 if (apic_verbosity == APIC_QUIET)
1456 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1457 for (i = 0; i < 8; i++) {
1458 v = apic_read(base + i*0x10);
1459 for (j = 0; j < 32; j++) {
1469 void /*__init*/ print_local_APIC(void * dummy)
1471 unsigned int v, ver, maxlvt;
1473 if (apic_verbosity == APIC_QUIET)
1476 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1477 smp_processor_id(), hard_smp_processor_id());
1478 v = apic_read(APIC_ID);
1479 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1480 v = apic_read(APIC_LVR);
1481 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1482 ver = GET_APIC_VERSION(v);
1483 maxlvt = get_maxlvt();
1485 v = apic_read(APIC_TASKPRI);
1486 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1488 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1489 v = apic_read(APIC_ARBPRI);
1490 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1491 v & APIC_ARBPRI_MASK);
1492 v = apic_read(APIC_PROCPRI);
1493 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1496 v = apic_read(APIC_EOI);
1497 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1498 v = apic_read(APIC_RRR);
1499 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1500 v = apic_read(APIC_LDR);
1501 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1502 v = apic_read(APIC_DFR);
1503 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1504 v = apic_read(APIC_SPIV);
1505 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1507 printk(KERN_DEBUG "... APIC ISR field:\n");
1508 print_APIC_bitfield(APIC_ISR);
1509 printk(KERN_DEBUG "... APIC TMR field:\n");
1510 print_APIC_bitfield(APIC_TMR);
1511 printk(KERN_DEBUG "... APIC IRR field:\n");
1512 print_APIC_bitfield(APIC_IRR);
1514 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1515 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1516 apic_write(APIC_ESR, 0);
1517 v = apic_read(APIC_ESR);
1518 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1521 v = apic_read(APIC_ICR);
1522 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1523 v = apic_read(APIC_ICR2);
1524 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1526 v = apic_read(APIC_LVTT);
1527 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1529 if (maxlvt > 3) { /* PC is LVT#4. */
1530 v = apic_read(APIC_LVTPC);
1531 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1533 v = apic_read(APIC_LVT0);
1534 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1535 v = apic_read(APIC_LVT1);
1536 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1538 if (maxlvt > 2) { /* ERR is LVT#3. */
1539 v = apic_read(APIC_LVTERR);
1540 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1543 v = apic_read(APIC_TMICT);
1544 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1545 v = apic_read(APIC_TMCCT);
1546 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1547 v = apic_read(APIC_TDCR);
1548 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1552 void print_all_local_APICs (void)
1554 on_each_cpu(print_local_APIC, NULL, 1, 1);
1557 void /*__init*/ print_PIC(void)
1559 extern spinlock_t i8259A_lock;
1561 unsigned long flags;
1563 if (apic_verbosity == APIC_QUIET)
1566 printk(KERN_DEBUG "\nprinting PIC contents\n");
1568 spin_lock_irqsave(&i8259A_lock, flags);
1570 v = inb(0xa1) << 8 | inb(0x21);
1571 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1573 v = inb(0xa0) << 8 | inb(0x20);
1574 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1578 v = inb(0xa0) << 8 | inb(0x20);
1582 spin_unlock_irqrestore(&i8259A_lock, flags);
1584 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1586 v = inb(0x4d1) << 8 | inb(0x4d0);
1587 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1590 static void __init enable_IO_APIC(void)
1592 union IO_APIC_reg_01 reg_01;
1594 unsigned long flags;
1596 for (i = 0; i < PIN_MAP_SIZE; i++) {
1597 irq_2_pin[i].pin = -1;
1598 irq_2_pin[i].next = 0;
1601 for (i = 0; i < MAX_PIRQS; i++)
1602 pirq_entries[i] = -1;
1605 * The number of IO-APIC IRQ registers (== #pins):
1607 for (i = 0; i < nr_ioapics; i++) {
1608 spin_lock_irqsave(&ioapic_lock, flags);
1609 reg_01.raw = io_apic_read(i, 1);
1610 spin_unlock_irqrestore(&ioapic_lock, flags);
1611 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1615 * Do not trust the IO-APIC being empty at bootup
1621 * Not an __init, needed by the reboot code
1623 void disable_IO_APIC(void)
1627 * Clear the IO-APIC before rebooting:
1632 * If the i82559 is routed through an IOAPIC
1633 * Put that IOAPIC in virtual wire mode
1634 * so legacy interrups can be delivered.
1636 pin = find_isa_irq_pin(0, mp_ExtINT);
1638 struct IO_APIC_route_entry entry;
1639 unsigned long flags;
1641 memset(&entry, 0, sizeof(entry));
1642 entry.mask = 0; /* Enabled */
1643 entry.trigger = 0; /* Edge */
1645 entry.polarity = 0; /* High */
1646 entry.delivery_status = 0;
1647 entry.dest_mode = 0; /* Physical */
1648 entry.delivery_mode = 7; /* ExtInt */
1650 entry.dest.physical.physical_dest = 0;
1654 * Add it to the IO-APIC irq-routing table:
1656 spin_lock_irqsave(&ioapic_lock, flags);
1657 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1658 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1659 spin_unlock_irqrestore(&ioapic_lock, flags);
1661 disconnect_bsp_APIC();
1665 * function to set the IO-APIC physical IDs based on the
1666 * values stored in the MPC table.
1668 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1671 #ifndef CONFIG_X86_NUMAQ
1672 static void __init setup_ioapic_ids_from_mpc(void)
1674 union IO_APIC_reg_00 reg_00;
1675 physid_mask_t phys_id_present_map;
1678 unsigned char old_id;
1679 unsigned long flags;
1682 * This is broken; anything with a real cpu count has to
1683 * circumvent this idiocy regardless.
1685 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1688 * Set the IOAPIC ID to the value stored in the MPC table.
1690 for (apic = 0; apic < nr_ioapics; apic++) {
1692 /* Read the register 0 value */
1693 spin_lock_irqsave(&ioapic_lock, flags);
1694 reg_00.raw = io_apic_read(apic, 0);
1695 spin_unlock_irqrestore(&ioapic_lock, flags);
1697 old_id = mp_ioapics[apic].mpc_apicid;
1699 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1700 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1701 apic, mp_ioapics[apic].mpc_apicid);
1702 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1704 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1707 /* Don't check I/O APIC IDs for some xAPIC systems. They have
1708 * no meaning without the serial APIC bus. */
1709 if (NO_IOAPIC_CHECK)
1712 * Sanity check, is the ID really free? Every APIC in a
1713 * system must have a unique ID or we get lots of nice
1714 * 'stuck on smp_invalidate_needed IPI wait' messages.
1716 if (check_apicid_used(phys_id_present_map,
1717 mp_ioapics[apic].mpc_apicid)) {
1718 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1719 apic, mp_ioapics[apic].mpc_apicid);
1720 for (i = 0; i < get_physical_broadcast(); i++)
1721 if (!physid_isset(i, phys_id_present_map))
1723 if (i >= get_physical_broadcast())
1724 panic("Max APIC ID exceeded!\n");
1725 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1727 physid_set(i, phys_id_present_map);
1728 mp_ioapics[apic].mpc_apicid = i;
1731 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1732 apic_printk(APIC_VERBOSE, "Setting %d in the "
1733 "phys_id_present_map\n",
1734 mp_ioapics[apic].mpc_apicid);
1735 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1740 * We need to adjust the IRQ routing table
1741 * if the ID changed.
1743 if (old_id != mp_ioapics[apic].mpc_apicid)
1744 for (i = 0; i < mp_irq_entries; i++)
1745 if (mp_irqs[i].mpc_dstapic == old_id)
1746 mp_irqs[i].mpc_dstapic
1747 = mp_ioapics[apic].mpc_apicid;
1750 * Read the right value from the MPC table and
1751 * write it into the ID register.
1753 apic_printk(APIC_VERBOSE, KERN_INFO
1754 "...changing IO-APIC physical APIC ID to %d ...",
1755 mp_ioapics[apic].mpc_apicid);
1757 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1758 spin_lock_irqsave(&ioapic_lock, flags);
1759 io_apic_write(apic, 0, reg_00.raw);
1760 spin_unlock_irqrestore(&ioapic_lock, flags);
1765 spin_lock_irqsave(&ioapic_lock, flags);
1766 reg_00.raw = io_apic_read(apic, 0);
1767 spin_unlock_irqrestore(&ioapic_lock, flags);
1768 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1769 printk("could not set ID!\n");
1771 apic_printk(APIC_VERBOSE, " ok.\n");
1775 static void __init setup_ioapic_ids_from_mpc(void) { }
1779 * There is a nasty bug in some older SMP boards, their mptable lies
1780 * about the timer IRQ. We do the following to work around the situation:
1782 * - timer IRQ defaults to IO-APIC IRQ
1783 * - if this function detects that timer IRQs are defunct, then we fall
1784 * back to ISA timer IRQs
1786 static int __init timer_irq_works(void)
1788 unsigned long t1 = jiffies;
1791 /* Let ten ticks pass... */
1792 mdelay((10 * 1000) / HZ);
1795 * Expect a few ticks at least, to be sure some possible
1796 * glue logic does not lock up after one or two first
1797 * ticks in a non-ExtINT mode. Also the local APIC
1798 * might have cached one ExtINT interrupt. Finally, at
1799 * least one tick may be lost due to delays.
1801 if (jiffies - t1 > 4)
1808 * In the SMP+IOAPIC case it might happen that there are an unspecified
1809 * number of pending IRQ events unhandled. These cases are very rare,
1810 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1811 * better to do it this way as thus we do not have to be aware of
1812 * 'pending' interrupts in the IRQ path, except at this point.
1815 * Edge triggered needs to resend any interrupt
1816 * that was delayed but this is now handled in the device
1821 * Starting up a edge-triggered IO-APIC interrupt is
1822 * nasty - we need to make sure that we get the edge.
1823 * If it is already asserted for some reason, we need
1824 * return 1 to indicate that is was pending.
1826 * This is not complete - we should be able to fake
1827 * an edge even if it isn't on the 8259A...
1829 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1831 int was_pending = 0;
1832 unsigned long flags;
1834 spin_lock_irqsave(&ioapic_lock, flags);
1836 disable_8259A_irq(irq);
1837 if (i8259A_irq_pending(irq))
1840 __unmask_IO_APIC_irq(irq);
1841 spin_unlock_irqrestore(&ioapic_lock, flags);
1847 * Once we have recorded IRQ_PENDING already, we can mask the
1848 * interrupt for real. This prevents IRQ storms from unhandled
1851 static void ack_edge_ioapic_irq(unsigned int irq)
1854 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1855 == (IRQ_PENDING | IRQ_DISABLED))
1856 mask_IO_APIC_irq(irq);
1861 * Level triggered interrupts can just be masked,
1862 * and shutting down and starting up the interrupt
1863 * is the same as enabling and disabling them -- except
1864 * with a startup need to return a "was pending" value.
1866 * Level triggered interrupts are special because we
1867 * do not touch any IO-APIC register while handling
1868 * them. We ack the APIC in the end-IRQ handler, not
1869 * in the start-IRQ-handler. Protection against reentrance
1870 * from the same interrupt is still provided, both by the
1871 * generic IRQ layer and by the fact that an unacked local
1872 * APIC does not accept IRQs.
1874 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1876 unmask_IO_APIC_irq(irq);
1878 return 0; /* don't check for pending */
1881 static void end_level_ioapic_irq (unsigned int irq)
1888 * It appears there is an erratum which affects at least version 0x11
1889 * of I/O APIC (that's the 82093AA and cores integrated into various
1890 * chipsets). Under certain conditions a level-triggered interrupt is
1891 * erroneously delivered as edge-triggered one but the respective IRR
1892 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1893 * message but it will never arrive and further interrupts are blocked
1894 * from the source. The exact reason is so far unknown, but the
1895 * phenomenon was observed when two consecutive interrupt requests
1896 * from a given source get delivered to the same CPU and the source is
1897 * temporarily disabled in between.
1899 * A workaround is to simulate an EOI message manually. We achieve it
1900 * by setting the trigger mode to edge and then to level when the edge
1901 * trigger mode gets detected in the TMR of a local APIC for a
1902 * level-triggered interrupt. We mask the source for the time of the
1903 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1904 * The idea is from Manfred Spraul. --macro
1906 i = IO_APIC_VECTOR(irq);
1908 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1912 if (!(v & (1 << (i & 0x1f)))) {
1913 #ifdef APIC_MISMATCH_DEBUG
1914 atomic_inc(&irq_mis_count);
1916 spin_lock(&ioapic_lock);
1917 __mask_and_edge_IO_APIC_irq(irq);
1918 __unmask_and_level_IO_APIC_irq(irq);
1919 spin_unlock(&ioapic_lock);
1923 #ifdef CONFIG_PCI_MSI
1924 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1926 int irq = vector_to_irq(vector);
1928 return startup_edge_ioapic_irq(irq);
1931 static void ack_edge_ioapic_vector(unsigned int vector)
1933 int irq = vector_to_irq(vector);
1935 ack_edge_ioapic_irq(irq);
1938 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1940 int irq = vector_to_irq(vector);
1942 return startup_level_ioapic_irq (irq);
1945 static void end_level_ioapic_vector (unsigned int vector)
1947 int irq = vector_to_irq(vector);
1949 end_level_ioapic_irq(irq);
1952 static void mask_IO_APIC_vector (unsigned int vector)
1954 int irq = vector_to_irq(vector);
1956 mask_IO_APIC_irq(irq);
1959 static void unmask_IO_APIC_vector (unsigned int vector)
1961 int irq = vector_to_irq(vector);
1963 unmask_IO_APIC_irq(irq);
1966 static void set_ioapic_affinity_vector (unsigned int vector,
1969 int irq = vector_to_irq(vector);
1971 set_ioapic_affinity_irq(irq, cpu_mask);
1976 * Level and edge triggered IO-APIC interrupts need different handling,
1977 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1978 * handled with the level-triggered descriptor, but that one has slightly
1979 * more overhead. Level-triggered interrupts cannot be handled with the
1980 * edge-triggered handler, without risking IRQ storms and other ugly
1983 static struct hw_interrupt_type ioapic_edge_type = {
1984 .typename = "IO-APIC-edge",
1985 .startup = startup_edge_ioapic,
1986 .shutdown = shutdown_edge_ioapic,
1987 .enable = enable_edge_ioapic,
1988 .disable = disable_edge_ioapic,
1989 .ack = ack_edge_ioapic,
1990 .end = end_edge_ioapic,
1991 .set_affinity = set_ioapic_affinity,
1994 static struct hw_interrupt_type ioapic_level_type = {
1995 .typename = "IO-APIC-level",
1996 .startup = startup_level_ioapic,
1997 .shutdown = shutdown_level_ioapic,
1998 .enable = enable_level_ioapic,
1999 .disable = disable_level_ioapic,
2000 .ack = mask_and_ack_level_ioapic,
2001 .end = end_level_ioapic,
2002 .set_affinity = set_ioapic_affinity,
2005 static inline void init_IO_APIC_traps(void)
2010 * NOTE! The local APIC isn't very good at handling
2011 * multiple interrupts at the same interrupt level.
2012 * As the interrupt level is determined by taking the
2013 * vector number and shifting that right by 4, we
2014 * want to spread these out a bit so that they don't
2015 * all fall in the same interrupt level.
2017 * Also, we've got to be careful not to trash gate
2018 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2020 for (irq = 0; irq < NR_IRQS ; irq++) {
2022 if (use_pci_vector()) {
2023 if (!platform_legacy_irq(tmp))
2024 if ((tmp = vector_to_irq(tmp)) == -1)
2027 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2029 * Hmm.. We don't have an entry for this,
2030 * so default to an old-fashioned 8259
2031 * interrupt if we can..
2034 make_8259A_irq(irq);
2036 /* Strange. Oh, well.. */
2037 irq_desc[irq].handler = &no_irq_type;
2042 static void enable_lapic_irq (unsigned int irq)
2046 v = apic_read(APIC_LVT0);
2047 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2050 static void disable_lapic_irq (unsigned int irq)
2054 v = apic_read(APIC_LVT0);
2055 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2058 static void ack_lapic_irq (unsigned int irq)
2063 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2065 static struct hw_interrupt_type lapic_irq_type = {
2066 .typename = "local-APIC-edge",
2067 .startup = NULL, /* startup_irq() not used for IRQ0 */
2068 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
2069 .enable = enable_lapic_irq,
2070 .disable = disable_lapic_irq,
2071 .ack = ack_lapic_irq,
2072 .end = end_lapic_irq
2075 static void setup_nmi (void)
2078 * Dirty trick to enable the NMI watchdog ...
2079 * We put the 8259A master into AEOI mode and
2080 * unmask on all local APICs LVT0 as NMI.
2082 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2083 * is from Maciej W. Rozycki - so we do not have to EOI from
2084 * the NMI handler or the timer interrupt.
2086 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2088 on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2090 apic_printk(APIC_VERBOSE, " done.\n");
2094 * This looks a bit hackish but it's about the only one way of sending
2095 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2096 * not support the ExtINT mode, unfortunately. We need to send these
2097 * cycles as some i82489DX-based boards have glue logic that keeps the
2098 * 8259A interrupt line asserted until INTA. --macro
2100 static inline void unlock_ExtINT_logic(void)
2103 struct IO_APIC_route_entry entry0, entry1;
2104 unsigned char save_control, save_freq_select;
2105 unsigned long flags;
2107 pin = find_isa_irq_pin(8, mp_INT);
2111 spin_lock_irqsave(&ioapic_lock, flags);
2112 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
2113 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
2114 spin_unlock_irqrestore(&ioapic_lock, flags);
2115 clear_IO_APIC_pin(0, pin);
2117 memset(&entry1, 0, sizeof(entry1));
2119 entry1.dest_mode = 0; /* physical delivery */
2120 entry1.mask = 0; /* unmask IRQ now */
2121 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2122 entry1.delivery_mode = dest_ExtINT;
2123 entry1.polarity = entry0.polarity;
2127 spin_lock_irqsave(&ioapic_lock, flags);
2128 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2129 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2130 spin_unlock_irqrestore(&ioapic_lock, flags);
2132 save_control = CMOS_READ(RTC_CONTROL);
2133 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2134 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2136 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2141 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2145 CMOS_WRITE(save_control, RTC_CONTROL);
2146 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2147 clear_IO_APIC_pin(0, pin);
2149 spin_lock_irqsave(&ioapic_lock, flags);
2150 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2151 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2152 spin_unlock_irqrestore(&ioapic_lock, flags);
2156 * This code may look a bit paranoid, but it's supposed to cooperate with
2157 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2158 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2159 * fanatically on his truly buggy board.
2161 static inline void check_timer(void)
2167 * get/set the timer IRQ vector:
2169 disable_8259A_irq(0);
2170 vector = assign_irq_vector(0);
2171 set_intr_gate(vector, interrupt[0]);
2174 * Subtle, code in do_timer_interrupt() expects an AEOI
2175 * mode for the 8259A whenever interrupts are routed
2176 * through I/O APICs. Also IRQ0 has to be enabled in
2177 * the 8259A which implies the virtual wire has to be
2178 * disabled in the local APIC.
2180 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2183 enable_8259A_irq(0);
2185 pin1 = find_isa_irq_pin(0, mp_INT);
2186 pin2 = find_isa_irq_pin(0, mp_ExtINT);
2188 printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
2192 * Ok, does IRQ0 through the IOAPIC work?
2194 unmask_IO_APIC_irq(0);
2195 if (timer_irq_works()) {
2196 if (nmi_watchdog == NMI_IO_APIC) {
2197 disable_8259A_irq(0);
2199 enable_8259A_irq(0);
2200 check_nmi_watchdog();
2204 clear_IO_APIC_pin(0, pin1);
2205 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2208 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2210 printk("\n..... (found pin %d) ...", pin2);
2212 * legacy devices should be connected to IO APIC #0
2214 setup_ExtINT_IRQ0_pin(pin2, vector);
2215 if (timer_irq_works()) {
2218 replace_pin_at_irq(0, 0, pin1, 0, pin2);
2220 add_pin_to_irq(0, 0, pin2);
2221 if (nmi_watchdog == NMI_IO_APIC) {
2223 check_nmi_watchdog();
2228 * Cleanup, just in case ...
2230 clear_IO_APIC_pin(0, pin2);
2232 printk(" failed.\n");
2234 if (nmi_watchdog == NMI_IO_APIC) {
2235 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2239 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2241 disable_8259A_irq(0);
2242 irq_desc[0].handler = &lapic_irq_type;
2243 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2244 enable_8259A_irq(0);
2246 if (timer_irq_works()) {
2247 printk(" works.\n");
2250 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2251 printk(" failed.\n");
2253 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2258 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2260 unlock_ExtINT_logic();
2262 if (timer_irq_works()) {
2263 printk(" works.\n");
2266 printk(" failed :(.\n");
2267 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2268 "report. Then try booting with the 'noapic' option");
2273 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2274 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2275 * Linux doesn't really care, as it's not actually used
2276 * for any interrupt handling anyway.
2278 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2280 void __init setup_IO_APIC(void)
2285 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2287 io_apic_irqs = ~PIC_IRQS;
2289 printk("ENABLING IO-APIC IRQs\n");
2292 * Set up IO-APIC IRQ routing.
2295 setup_ioapic_ids_from_mpc();
2297 setup_IO_APIC_irqs();
2298 init_IO_APIC_traps();
2305 * Called after all the initialization is done. If we didnt find any
2306 * APIC bugs then we can allow the modify fast path
2309 static int __init io_apic_bug_finalize(void)
2311 if(sis_apic_bug == -1)
2316 late_initcall(io_apic_bug_finalize);
2318 struct sysfs_ioapic_data {
2319 struct sys_device dev;
2320 struct IO_APIC_route_entry entry[0];
2322 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2324 static int ioapic_suspend(struct sys_device *dev, u32 state)
2326 struct IO_APIC_route_entry *entry;
2327 struct sysfs_ioapic_data *data;
2328 unsigned long flags;
2331 data = container_of(dev, struct sysfs_ioapic_data, dev);
2332 entry = data->entry;
2333 spin_lock_irqsave(&ioapic_lock, flags);
2334 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2335 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2336 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2338 spin_unlock_irqrestore(&ioapic_lock, flags);
2343 static int ioapic_resume(struct sys_device *dev)
2345 struct IO_APIC_route_entry *entry;
2346 struct sysfs_ioapic_data *data;
2347 unsigned long flags;
2348 union IO_APIC_reg_00 reg_00;
2351 data = container_of(dev, struct sysfs_ioapic_data, dev);
2352 entry = data->entry;
2354 spin_lock_irqsave(&ioapic_lock, flags);
2355 reg_00.raw = io_apic_read(dev->id, 0);
2356 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2357 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2358 io_apic_write(dev->id, 0, reg_00.raw);
2360 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2361 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2362 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2364 spin_unlock_irqrestore(&ioapic_lock, flags);
2369 static struct sysdev_class ioapic_sysdev_class = {
2370 set_kset_name("ioapic"),
2371 .suspend = ioapic_suspend,
2372 .resume = ioapic_resume,
2375 static int __init ioapic_init_sysfs(void)
2377 struct sys_device * dev;
2378 int i, size, error = 0;
2380 error = sysdev_class_register(&ioapic_sysdev_class);
2384 for (i = 0; i < nr_ioapics; i++ ) {
2385 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2386 * sizeof(struct IO_APIC_route_entry);
2387 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2388 if (!mp_ioapic_data[i]) {
2389 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2392 memset(mp_ioapic_data[i], 0, size);
2393 dev = &mp_ioapic_data[i]->dev;
2395 dev->cls = &ioapic_sysdev_class;
2396 error = sysdev_register(dev);
2398 kfree(mp_ioapic_data[i]);
2399 mp_ioapic_data[i] = NULL;
2400 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2408 device_initcall(ioapic_init_sysfs);
2410 /* --------------------------------------------------------------------------
2411 ACPI-based IOAPIC Configuration
2412 -------------------------------------------------------------------------- */
2414 #ifdef CONFIG_ACPI_BOOT
2416 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2418 union IO_APIC_reg_00 reg_00;
2419 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2421 unsigned long flags;
2425 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2426 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2427 * supports up to 16 on one shared APIC bus.
2429 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2430 * advantage of new APIC bus architecture.
2433 if (physids_empty(apic_id_map))
2434 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2436 spin_lock_irqsave(&ioapic_lock, flags);
2437 reg_00.raw = io_apic_read(ioapic, 0);
2438 spin_unlock_irqrestore(&ioapic_lock, flags);
2440 if (apic_id >= get_physical_broadcast()) {
2441 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2442 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2443 apic_id = reg_00.bits.ID;
2447 * Every APIC in a system must have a unique ID or we get lots of nice
2448 * 'stuck on smp_invalidate_needed IPI wait' messages.
2450 if (check_apicid_used(apic_id_map, apic_id)) {
2452 for (i = 0; i < get_physical_broadcast(); i++) {
2453 if (!check_apicid_used(apic_id_map, i))
2457 if (i == get_physical_broadcast())
2458 panic("Max apic_id exceeded!\n");
2460 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2461 "trying %d\n", ioapic, apic_id, i);
2466 tmp = apicid_to_cpu_present(apic_id);
2467 physids_or(apic_id_map, apic_id_map, tmp);
2469 if (reg_00.bits.ID != apic_id) {
2470 reg_00.bits.ID = apic_id;
2472 spin_lock_irqsave(&ioapic_lock, flags);
2473 io_apic_write(ioapic, 0, reg_00.raw);
2474 reg_00.raw = io_apic_read(ioapic, 0);
2475 spin_unlock_irqrestore(&ioapic_lock, flags);
2478 if (reg_00.bits.ID != apic_id)
2479 panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
2482 apic_printk(APIC_VERBOSE, KERN_INFO
2483 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2489 int __init io_apic_get_version (int ioapic)
2491 union IO_APIC_reg_01 reg_01;
2492 unsigned long flags;
2494 spin_lock_irqsave(&ioapic_lock, flags);
2495 reg_01.raw = io_apic_read(ioapic, 1);
2496 spin_unlock_irqrestore(&ioapic_lock, flags);
2498 return reg_01.bits.version;
2502 int __init io_apic_get_redir_entries (int ioapic)
2504 union IO_APIC_reg_01 reg_01;
2505 unsigned long flags;
2507 spin_lock_irqsave(&ioapic_lock, flags);
2508 reg_01.raw = io_apic_read(ioapic, 1);
2509 spin_unlock_irqrestore(&ioapic_lock, flags);
2511 return reg_01.bits.entries;
2515 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2517 struct IO_APIC_route_entry entry;
2518 unsigned long flags;
2520 if (!IO_APIC_IRQ(irq)) {
2521 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2527 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2528 * Note that we mask (disable) IRQs now -- these get enabled when the
2529 * corresponding device driver registers for this IRQ.
2532 memset(&entry,0,sizeof(entry));
2534 entry.delivery_mode = INT_DELIVERY_MODE;
2535 entry.dest_mode = INT_DEST_MODE;
2536 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2537 entry.trigger = edge_level;
2538 entry.polarity = active_high_low;
2542 * IRQs < 16 are already in the irq_2_pin[] map
2545 add_pin_to_irq(irq, ioapic, pin);
2547 entry.vector = assign_irq_vector(irq);
2549 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2550 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2551 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2552 edge_level, active_high_low);
2554 ioapic_register_intr(irq, entry.vector, edge_level);
2556 if (!ioapic && (irq < 16))
2557 disable_8259A_irq(irq);
2559 spin_lock_irqsave(&ioapic_lock, flags);
2560 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2561 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2562 spin_unlock_irqrestore(&ioapic_lock, flags);
2567 #endif /*CONFIG_ACPI_BOOT*/