arch/i386/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/sched.h>
  29 #include <linux/config.h>
  30 #include <linux/smp_lock.h>
  31 #include <linux/mc146818rtc.h>
  32 #include <linux/compiler.h>
  33 #include <linux/acpi.h>
  34
  35 #include <linux/sysdev.h>
  36 #include <asm/io.h>
  37 #include <asm/smp.h>
  38 #include <asm/desc.h>
  39 #include <asm/timer.h>
  40
  41 #include <mach_apic.h>
  42
  43 #include "io_ports.h"
  44
  45 int (*ioapic_renumber_irq)(int ioapic, int irq);
  46 atomic_t irq_mis_count;
  47
  48 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
  49
  50 /*
  51  *      Is the SiS APIC rmw bug present ?
  52  *      -1 = don't know, 0 = no, 1 = yes
  53  */
  54 int sis_apic_bug = -1;
  55
  56 /*
  57  * # of IRQ routing registers
  58  */
  59 int nr_ioapic_registers[MAX_IO_APICS];
  60
  61 /*
  62  * Rough estimation of how many shared IRQs there are, can
  63  * be changed anytime.
  64  */
  65 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  66 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  67
  68 /*
  69  * This is performance-critical, we want to do it O(1)
  70  *
  71  * the indexing order of this array favors 1:1 mappings
  72  * between pins and IRQs.
  73  */
  74
  75 static struct irq_pin_list {
  76         int apic, pin, next;
  77 } irq_2_pin[PIN_MAP_SIZE];
  78
  79 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
  80 #ifdef CONFIG_PCI_MSI
  81 #define vector_to_irq(vector)   \
  82         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  83 #else
  84 #define vector_to_irq(vector)   (vector)
  85 #endif
  86
  87 /*
  88  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  89  * shared ISA-space IRQs, so we have to support them. We are super
  90  * fast in the common case, and fast for shared ISA-space IRQs.
  91  */
  92 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
  93 {
  94         static int first_free_entry = NR_IRQS;
  95         struct irq_pin_list *entry = irq_2_pin + irq;
  96
  97         while (entry->next)
  98                 entry = irq_2_pin + entry->next;
  99
 100         if (entry->pin != -1) {
 101                 entry->next = first_free_entry;
 102                 entry = irq_2_pin + entry->next;
 103                 if (++first_free_entry >= PIN_MAP_SIZE)
 104                         panic("io_apic.c: whoops");
 105         }
 106         entry->apic = apic;
 107         entry->pin = pin;
 108 }
 109
 110 /*
 111  * Reroute an IRQ to a different pin.
 112  */
 113 static void __init replace_pin_at_irq(unsigned int irq,
 114                                       int oldapic, int oldpin,
 115                                       int newapic, int newpin)
 116 {
 117         struct irq_pin_list *entry = irq_2_pin + irq;
 118
 119         while (1) {
 120                 if (entry->apic == oldapic && entry->pin == oldpin) {
 121                         entry->apic = newapic;
 122                         entry->pin = newpin;
 123                 }
 124                 if (!entry->next)
 125                         break;
 126                 entry = irq_2_pin + entry->next;
 127         }
 128 }
 129
 130 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 131 {
 132         struct irq_pin_list *entry = irq_2_pin + irq;
 133         unsigned int pin, reg;
 134
 135         for (;;) {
 136                 pin = entry->pin;
 137                 if (pin == -1)
 138                         break;
 139                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 140                 reg &= ~disable;
 141                 reg |= enable;
 142                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 143                 if (!entry->next)
 144                         break;
 145                 entry = irq_2_pin + entry->next;
 146         }
 147 }
 148
 149 /* mask = 1 */
 150 static void __mask_IO_APIC_irq (unsigned int irq)
 151 {
 152         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 153 }
 154
 155 /* mask = 0 */
 156 static void __unmask_IO_APIC_irq (unsigned int irq)
 157 {
 158         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 159 }
 160
 161 /* mask = 1, trigger = 0 */
 162 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 163 {
 164         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 165 }
 166
 167 /* mask = 0, trigger = 1 */
 168 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 169 {
 170         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 171 }
 172
 173 static void mask_IO_APIC_irq (unsigned int irq)
 174 {
 175         unsigned long flags;
 176
 177         spin_lock_irqsave(&ioapic_lock, flags);
 178         __mask_IO_APIC_irq(irq);
 179         spin_unlock_irqrestore(&ioapic_lock, flags);
 180 }
 181
 182 static void unmask_IO_APIC_irq (unsigned int irq)
 183 {
 184         unsigned long flags;
 185
 186         spin_lock_irqsave(&ioapic_lock, flags);
 187         __unmask_IO_APIC_irq(irq);
 188         spin_unlock_irqrestore(&ioapic_lock, flags);
 189 }
 190
 191 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 192 {
 193         struct IO_APIC_route_entry entry;
 194         unsigned long flags;
 195
 196         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 197         spin_lock_irqsave(&ioapic_lock, flags);
 198         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 199         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 200         spin_unlock_irqrestore(&ioapic_lock, flags);
 201         if (entry.delivery_mode == dest_SMI)
 202                 return;
 203
 204         /*
 205          * Disable it in the IO-APIC irq-routing table:
 206          */
 207         memset(&entry, 0, sizeof(entry));
 208         entry.mask = 1;
 209         spin_lock_irqsave(&ioapic_lock, flags);
 210         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 211         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 212         spin_unlock_irqrestore(&ioapic_lock, flags);
 213 }
 214
 215 static void clear_IO_APIC (void)
 216 {
 217         int apic, pin;
 218
 219         for (apic = 0; apic < nr_ioapics; apic++)
 220                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 221                         clear_IO_APIC_pin(apic, pin);
 222 }
 223
 224 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 225 {
 226         unsigned long flags;
 227         int pin;
 228         struct irq_pin_list *entry = irq_2_pin + irq;
 229         unsigned int apicid_value;
 230
 231         apicid_value = cpu_mask_to_apicid(cpumask);
 232         /* Prepare to do the io_apic_write */
 233         apicid_value = apicid_value << 24;
 234         spin_lock_irqsave(&ioapic_lock, flags);
 235         for (;;) {
 236                 pin = entry->pin;
 237                 if (pin == -1)
 238                         break;
 239                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 240                 if (!entry->next)
 241                         break;
 242                 entry = irq_2_pin + entry->next;
 243         }
 244         spin_unlock_irqrestore(&ioapic_lock, flags);
 245 }
 246
 247 #if defined(CONFIG_IRQBALANCE)
 248 # include <asm/processor.h>     /* kernel_thread() */
 249 # include <linux/kernel_stat.h> /* kstat */
 250 # include <linux/slab.h>                /* kmalloc() */
 251 # include <linux/timer.h>       /* time_after() */
 252
 253 # ifdef CONFIG_BALANCED_IRQ_DEBUG
 254 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 255 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 256 # else
 257 #  define TDprintk(x...)
 258 #  define Dprintk(x...)
 259 # endif
 260
 261 cpumask_t __cacheline_aligned pending_irq_balance_cpumask[NR_IRQS];
 262
 263 #define IRQBALANCE_CHECK_ARCH -999
 264 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
 265 static int physical_balance = 0;
 266
 267 struct irq_cpu_info {
 268         unsigned long * last_irq;
 269         unsigned long * irq_delta;
 270         unsigned long irq;
 271 } irq_cpu_data[NR_CPUS];
 272
 273 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 274 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 275 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 276
 277 #define IDLE_ENOUGH(cpu,now) \
 278                 (idle_cpu(cpu) && ((now) - irq_stat[(cpu)].idle_timestamp > 1))
 279
 280 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 281
 282 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 283
 284 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 285 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 286 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 287 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 288
 289 long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
 290
 291 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 292                         unsigned long now, int direction)
 293 {
 294         int search_idle = 1;
 295         int cpu = curr_cpu;
 296
 297         goto inside;
 298
 299         do {
 300                 if (unlikely(cpu == curr_cpu))
 301                         search_idle = 0;
 302 inside:
 303                 if (direction == 1) {
 304                         cpu++;
 305                         if (cpu >= NR_CPUS)
 306                                 cpu = 0;
 307                 } else {
 308                         cpu--;
 309                         if (cpu == -1)
 310                                 cpu = NR_CPUS-1;
 311                 }
 312         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 313                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 314
 315         return cpu;
 316 }
 317
 318 static inline void balance_irq(int cpu, int irq)
 319 {
 320         unsigned long now = jiffies;
 321         cpumask_t allowed_mask;
 322         unsigned int new_cpu;
 323
 324         if (irqbalance_disabled)
 325                 return;
 326
 327         cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
 328         new_cpu = move(cpu, allowed_mask, now, 1);
 329         if (cpu != new_cpu) {
 330                 irq_desc_t *desc = irq_desc + irq;
 331                 unsigned long flags;
 332
 333                 spin_lock_irqsave(&desc->lock, flags);
 334                 pending_irq_balance_cpumask[irq] = cpumask_of_cpu(new_cpu);
 335                 spin_unlock_irqrestore(&desc->lock, flags);
 336         }
 337 }
 338
 339 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 340 {
 341         int i, j;
 342         Dprintk("Rotating IRQs among CPUs.\n");
 343         for (i = 0; i < NR_CPUS; i++) {
 344                 for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
 345                         if (!irq_desc[j].action)
 346                                 continue;
 347                         /* Is it a significant load ?  */
 348                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 349                                                 useful_load_threshold)
 350                                 continue;
 351                         balance_irq(i, j);
 352                 }
 353         }
 354         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 355                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 356         return;
 357 }
 358
 359 static void do_irq_balance(void)
 360 {
 361         int i, j;
 362         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 363         unsigned long move_this_load = 0;
 364         int max_loaded = 0, min_loaded = 0;
 365         int load;
 366         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 367         int selected_irq;
 368         int tmp_loaded, first_attempt = 1;
 369         unsigned long tmp_cpu_irq;
 370         unsigned long imbalance = 0;
 371         cpumask_t allowed_mask, target_cpu_mask, tmp;
 372
 373         for (i = 0; i < NR_CPUS; i++) {
 374                 int package_index;
 375                 CPU_IRQ(i) = 0;
 376                 if (!cpu_online(i))
 377                         continue;
 378                 package_index = CPU_TO_PACKAGEINDEX(i);
 379                 for (j = 0; j < NR_IRQS; j++) {
 380                         unsigned long value_now, delta;
 381                         /* Is this an active IRQ? */
 382                         if (!irq_desc[j].action)
 383                                 continue;
 384                         if ( package_index == i )
 385                                 IRQ_DELTA(package_index,j) = 0;
 386                         /* Determine the total count per processor per IRQ */
 387                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 388
 389                         /* Determine the activity per processor per IRQ */
 390                         delta = value_now - LAST_CPU_IRQ(i,j);
 391
 392                         /* Update last_cpu_irq[][] for the next time */
 393                         LAST_CPU_IRQ(i,j) = value_now;
 394
 395                         /* Ignore IRQs whose rate is less than the clock */
 396                         if (delta < useful_load_threshold)
 397                                 continue;
 398                         /* update the load for the processor or package total */
 399                         IRQ_DELTA(package_index,j) += delta;
 400
 401                         /* Keep track of the higher numbered sibling as well */
 402                         if (i != package_index)
 403                                 CPU_IRQ(i) += delta;
 404                         /*
 405                          * We have sibling A and sibling B in the package
 406                          *
 407                          * cpu_irq[A] = load for cpu A + load for cpu B
 408                          * cpu_irq[B] = load for cpu B
 409                          */
 410                         CPU_IRQ(package_index) += delta;
 411                 }
 412         }
 413         /* Find the least loaded processor package */
 414         for (i = 0; i < NR_CPUS; i++) {
 415                 if (!cpu_online(i))
 416                         continue;
 417                 if (i != CPU_TO_PACKAGEINDEX(i))
 418                         continue;
 419                 if (min_cpu_irq > CPU_IRQ(i)) {
 420                         min_cpu_irq = CPU_IRQ(i);
 421                         min_loaded = i;
 422                 }
 423         }
 424         max_cpu_irq = ULONG_MAX;
 425
 426 tryanothercpu:
 427         /* Look for heaviest loaded processor.
 428          * We may come back to get the next heaviest loaded processor.
 429          * Skip processors with trivial loads.
 430          */
 431         tmp_cpu_irq = 0;
 432         tmp_loaded = -1;
 433         for (i = 0; i < NR_CPUS; i++) {
 434                 if (!cpu_online(i))
 435                         continue;
 436                 if (i != CPU_TO_PACKAGEINDEX(i))
 437                         continue;
 438                 if (max_cpu_irq <= CPU_IRQ(i))
 439                         continue;
 440                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 441                         tmp_cpu_irq = CPU_IRQ(i);
 442                         tmp_loaded = i;
 443                 }
 444         }
 445
 446         if (tmp_loaded == -1) {
 447          /* In the case of small number of heavy interrupt sources,
 448           * loading some of the cpus too much. We use Ingo's original
 449           * approach to rotate them around.
 450           */
 451                 if (!first_attempt && imbalance >= useful_load_threshold) {
 452                         rotate_irqs_among_cpus(useful_load_threshold);
 453                         return;
 454                 }
 455                 goto not_worth_the_effort;
 456         }
 457
 458         first_attempt = 0;              /* heaviest search */
 459         max_cpu_irq = tmp_cpu_irq;      /* load */
 460         max_loaded = tmp_loaded;        /* processor */
 461         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 462
 463         Dprintk("max_loaded cpu = %d\n", max_loaded);
 464         Dprintk("min_loaded cpu = %d\n", min_loaded);
 465         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 466         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 467         Dprintk("load imbalance = %lu\n", imbalance);
 468
 469         /* if imbalance is less than approx 10% of max load, then
 470          * observe diminishing returns action. - quit
 471          */
 472         if (imbalance < (max_cpu_irq >> 3)) {
 473                 Dprintk("Imbalance too trivial\n");
 474                 goto not_worth_the_effort;
 475         }
 476
 477 tryanotherirq:
 478         /* if we select an IRQ to move that can't go where we want, then
 479          * see if there is another one to try.
 480          */
 481         move_this_load = 0;
 482         selected_irq = -1;
 483         for (j = 0; j < NR_IRQS; j++) {
 484                 /* Is this an active IRQ? */
 485                 if (!irq_desc[j].action)
 486                         continue;
 487                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 488                         continue;
 489                 /* Try to find the IRQ that is closest to the imbalance
 490                  * without going over.
 491                  */
 492                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 493                         move_this_load = IRQ_DELTA(max_loaded,j);
 494                         selected_irq = j;
 495                 }
 496         }
 497         if (selected_irq == -1) {
 498                 goto tryanothercpu;
 499         }
 500
 501         imbalance = move_this_load;
 502
 503         /* For physical_balance case, we accumlated both load
 504          * values in the one of the siblings cpu_irq[],
 505          * to use the same code for physical and logical processors
 506          * as much as possible.
 507          *
 508          * NOTE: the cpu_irq[] array holds the sum of the load for
 509          * sibling A and sibling B in the slot for the lowest numbered
 510          * sibling (A), _AND_ the load for sibling B in the slot for
 511          * the higher numbered sibling.
 512          *
 513          * We seek the least loaded sibling by making the comparison
 514          * (A+B)/2 vs B
 515          */
 516         load = CPU_IRQ(min_loaded) >> 1;
 517         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 518                 if (load > CPU_IRQ(j)) {
 519                         /* This won't change cpu_sibling_map[min_loaded] */
 520                         load = CPU_IRQ(j);
 521                         min_loaded = j;
 522                 }
 523         }
 524
 525         cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
 526         target_cpu_mask = cpumask_of_cpu(min_loaded);
 527         cpus_and(tmp, target_cpu_mask, allowed_mask);
 528
 529         if (!cpus_empty(tmp)) {
 530                 irq_desc_t *desc = irq_desc + selected_irq;
 531                 unsigned long flags;
 532
 533                 Dprintk("irq = %d moved to cpu = %d\n",
 534                                 selected_irq, min_loaded);
 535                 /* mark for change destination */
 536                 spin_lock_irqsave(&desc->lock, flags);
 537                 pending_irq_balance_cpumask[selected_irq] =
 538                                         cpumask_of_cpu(min_loaded);
 539                 spin_unlock_irqrestore(&desc->lock, flags);
 540                 /* Since we made a change, come back sooner to
 541                  * check for more variation.
 542                  */
 543                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 544                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 545                 return;
 546         }
 547         goto tryanotherirq;
 548
 549 not_worth_the_effort:
 550         /*
 551          * if we did not find an IRQ to move, then adjust the time interval
 552          * upward
 553          */
 554         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 555                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 556         Dprintk("IRQ worth rotating not found\n");
 557         return;
 558 }
 559
 560 static int balanced_irq(void *unused)
 561 {
 562         int i;
 563         unsigned long prev_balance_time = jiffies;
 564         long time_remaining = balanced_irq_interval;
 565
 566         daemonize("kirqd");
 567
 568         /* push everything to CPU 0 to give us a starting point.  */
 569         for (i = 0 ; i < NR_IRQS ; i++) {
 570                 pending_irq_balance_cpumask[i] = cpumask_of_cpu(0);
 571         }
 572
 573         for ( ; ; ) {
 574                 set_current_state(TASK_INTERRUPTIBLE);
 575                 time_remaining = schedule_timeout(time_remaining);
 576                 if (time_after(jiffies,
 577                                 prev_balance_time+balanced_irq_interval)) {
 578                         do_irq_balance();
 579                         prev_balance_time = jiffies;
 580                         time_remaining = balanced_irq_interval;
 581                 }
 582         }
 583         return 0;
 584 }
 585
 586 static int __init balanced_irq_init(void)
 587 {
 588         int i;
 589         struct cpuinfo_x86 *c;
 590         cpumask_t tmp;
 591
 592         cpus_shift_right(tmp, cpu_online_map, 2);
 593         c = &boot_cpu_data;
 594         /* When not overwritten by the command line ask subarchitecture. */
 595         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 596                 irqbalance_disabled = NO_BALANCE_IRQ;
 597         if (irqbalance_disabled)
 598                 return 0;
 599
 600          /* disable irqbalance completely if there is only one processor online */
 601         if (num_online_cpus() < 2) {
 602                 irqbalance_disabled = 1;
 603                 return 0;
 604         }
 605         /*
 606          * Enable physical balance only if more than 1 physical processor
 607          * is present
 608          */
 609         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 610                 physical_balance = 1;
 611
 612         for (i = 0; i < NR_CPUS; i++) {
 613                 if (!cpu_online(i))
 614                         continue;
 615                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 616                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 617                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 618                         printk(KERN_ERR "balanced_irq_init: out of memory");
 619                         goto failed;
 620                 }
 621                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 622                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 623         }
 624
 625         printk(KERN_INFO "Starting balanced_irq\n");
 626         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 627                 return 0;
 628         else
 629                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 630 failed:
 631         for (i = 0; i < NR_CPUS; i++) {
 632                 if(irq_cpu_data[i].irq_delta)
 633                         kfree(irq_cpu_data[i].irq_delta);
 634                 if(irq_cpu_data[i].last_irq)
 635                         kfree(irq_cpu_data[i].last_irq);
 636         }
 637         return 0;
 638 }
 639
 640 int __init irqbalance_disable(char *str)
 641 {
 642         irqbalance_disabled = 1;
 643         return 0;
 644 }
 645
 646 __setup("noirqbalance", irqbalance_disable);
 647
 648 static inline void move_irq(int irq)
 649 {
 650         /* note - we hold the desc->lock */
 651         if (unlikely(!cpus_empty(pending_irq_balance_cpumask[irq]))) {
 652                 set_ioapic_affinity_irq(irq, pending_irq_balance_cpumask[irq]);
 653                 cpus_clear(pending_irq_balance_cpumask[irq]);
 654         }
 655 }
 656
 657 late_initcall(balanced_irq_init);
 658
 659 #else /* !CONFIG_IRQBALANCE */
 660 static inline void move_irq(int irq) { }
 661 #endif /* CONFIG_IRQBALANCE */
 662
 663 #ifndef CONFIG_SMP
 664 void fastcall send_IPI_self(int vector)
 665 {
 666         unsigned int cfg;
 667
 668         /*
 669          * Wait for idle.
 670          */
 671         apic_wait_icr_idle();
 672         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 673         /*
 674          * Send the IPI. The write to APIC_ICR fires this off.
 675          */
 676         apic_write_around(APIC_ICR, cfg);
 677 }
 678 #endif /* !CONFIG_SMP */
 679
 680
 681 /*
 682  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 683  * specific CPU-side IRQs.
 684  */
 685
 686 #define MAX_PIRQS 8
 687 int pirq_entries [MAX_PIRQS];
 688 int pirqs_enabled;
 689 int skip_ioapic_setup;
 690
 691 static int __init ioapic_setup(char *str)
 692 {
 693         skip_ioapic_setup = 1;
 694         return 1;
 695 }
 696
 697 __setup("noapic", ioapic_setup);
 698
 699 static int __init ioapic_pirq_setup(char *str)
 700 {
 701         int i, max;
 702         int ints[MAX_PIRQS+1];
 703
 704         get_options(str, ARRAY_SIZE(ints), ints);
 705
 706         for (i = 0; i < MAX_PIRQS; i++)
 707                 pirq_entries[i] = -1;
 708
 709         pirqs_enabled = 1;
 710         apic_printk(APIC_VERBOSE, KERN_INFO
 711                         "PIRQ redirection, working around broken MP-BIOS.\n");
 712         max = MAX_PIRQS;
 713         if (ints[0] < MAX_PIRQS)
 714                 max = ints[0];
 715
 716         for (i = 0; i < max; i++) {
 717                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 718                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 719                 /*
 720                  * PIRQs are mapped upside down, usually.
 721                  */
 722                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 723         }
 724         return 1;
 725 }
 726
 727 __setup("pirq=", ioapic_pirq_setup);
 728
 729 /*
 730  * Find the IRQ entry number of a certain pin.
 731  */
 732 static int find_irq_entry(int apic, int pin, int type)
 733 {
 734         int i;
 735
 736         for (i = 0; i < mp_irq_entries; i++)
 737                 if (mp_irqs[i].mpc_irqtype == type &&
 738                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 739                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 740                     mp_irqs[i].mpc_dstirq == pin)
 741                         return i;
 742
 743         return -1;
 744 }
 745
 746 /*
 747  * Find the pin to which IRQ[irq] (ISA) is connected
 748  */
 749 static int find_isa_irq_pin(int irq, int type)
 750 {
 751         int i;
 752
 753         for (i = 0; i < mp_irq_entries; i++) {
 754                 int lbus = mp_irqs[i].mpc_srcbus;
 755
 756                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 757                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 758                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 759                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 760                     ) &&
 761                     (mp_irqs[i].mpc_irqtype == type) &&
 762                     (mp_irqs[i].mpc_srcbusirq == irq))
 763
 764                         return mp_irqs[i].mpc_dstirq;
 765         }
 766         return -1;
 767 }
 768
 769 /*
 770  * Find a specific PCI IRQ entry.
 771  * Not an __init, possibly needed by modules
 772  */
 773 static int pin_2_irq(int idx, int apic, int pin);
 774
 775 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 776 {
 777         int apic, i, best_guess = -1;
 778
 779         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 780                 "slot:%d, pin:%d.\n", bus, slot, pin);
 781         if (mp_bus_id_to_pci_bus[bus] == -1) {
 782                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 783                 return -1;
 784         }
 785         for (i = 0; i < mp_irq_entries; i++) {
 786                 int lbus = mp_irqs[i].mpc_srcbus;
 787
 788                 for (apic = 0; apic < nr_ioapics; apic++)
 789                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 790                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 791                                 break;
 792
 793                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 794                     !mp_irqs[i].mpc_irqtype &&
 795                     (bus == lbus) &&
 796                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 797                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 798
 799                         if (!(apic || IO_APIC_IRQ(irq)))
 800                                 continue;
 801
 802                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 803                                 return irq;
 804                         /*
 805                          * Use the first all-but-pin matching entry as a
 806                          * best-guess fuzzy result for broken mptables.
 807                          */
 808                         if (best_guess < 0)
 809                                 best_guess = irq;
 810                 }
 811         }
 812         return best_guess;
 813 }
 814
 815 /*
 816  * This function currently is only a helper for the i386 smp boot process where
 817  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 818  * so mask in all cases should simply be TARGET_CPUS
 819  */
 820 void __init setup_ioapic_dest(void)
 821 {
 822         int pin, ioapic, irq, irq_entry;
 823
 824         if (skip_ioapic_setup == 1)
 825                 return;
 826
 827         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 828                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 829                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 830                         if (irq_entry == -1)
 831                                 continue;
 832                         irq = pin_2_irq(irq_entry, ioapic, pin);
 833                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 834                 }
 835
 836         }
 837 }
 838
 839 /*
 840  * EISA Edge/Level control register, ELCR
 841  */
 842 static int EISA_ELCR(unsigned int irq)
 843 {
 844         if (irq < 16) {
 845                 unsigned int port = 0x4d0 + (irq >> 3);
 846                 return (inb(port) >> (irq & 7)) & 1;
 847         }
 848         apic_printk(APIC_VERBOSE, KERN_INFO
 849                         "Broken MPtable reports ISA irq %d\n", irq);
 850         return 0;
 851 }
 852
 853 /* EISA interrupts are always polarity zero and can be edge or level
 854  * trigger depending on the ELCR value.  If an interrupt is listed as
 855  * EISA conforming in the MP table, that means its trigger type must
 856  * be read in from the ELCR */
 857
 858 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 859 #define default_EISA_polarity(idx)      (0)
 860
 861 /* ISA interrupts are always polarity zero edge triggered,
 862  * when listed as conforming in the MP table. */
 863
 864 #define default_ISA_trigger(idx)        (0)
 865 #define default_ISA_polarity(idx)       (0)
 866
 867 /* PCI interrupts are always polarity one level triggered,
 868  * when listed as conforming in the MP table. */
 869
 870 #define default_PCI_trigger(idx)        (1)
 871 #define default_PCI_polarity(idx)       (1)
 872
 873 /* MCA interrupts are always polarity zero level triggered,
 874  * when listed as conforming in the MP table. */
 875
 876 #define default_MCA_trigger(idx)        (1)
 877 #define default_MCA_polarity(idx)       (0)
 878
 879 /* NEC98 interrupts are always polarity zero edge triggered,
 880  * when listed as conforming in the MP table. */
 881
 882 #define default_NEC98_trigger(idx)     (0)
 883 #define default_NEC98_polarity(idx)    (0)
 884
 885 static int __init MPBIOS_polarity(int idx)
 886 {
 887         int bus = mp_irqs[idx].mpc_srcbus;
 888         int polarity;
 889
 890         /*
 891          * Determine IRQ line polarity (high active or low active):
 892          */
 893         switch (mp_irqs[idx].mpc_irqflag & 3)
 894         {
 895                 case 0: /* conforms, ie. bus-type dependent polarity */
 896                 {
 897                         switch (mp_bus_id_to_type[bus])
 898                         {
 899                                 case MP_BUS_ISA: /* ISA pin */
 900                                 {
 901                                         polarity = default_ISA_polarity(idx);
 902                                         break;
 903                                 }
 904                                 case MP_BUS_EISA: /* EISA pin */
 905                                 {
 906                                         polarity = default_EISA_polarity(idx);
 907                                         break;
 908                                 }
 909                                 case MP_BUS_PCI: /* PCI pin */
 910                                 {
 911                                         polarity = default_PCI_polarity(idx);
 912                                         break;
 913                                 }
 914                                 case MP_BUS_MCA: /* MCA pin */
 915                                 {
 916                                         polarity = default_MCA_polarity(idx);
 917                                         break;
 918                                 }
 919                                 case MP_BUS_NEC98: /* NEC 98 pin */
 920                                 {
 921                                         polarity = default_NEC98_polarity(idx);
 922                                         break;
 923                                 }
 924                                 default:
 925                                 {
 926                                         printk(KERN_WARNING "broken BIOS!!\n");
 927                                         polarity = 1;
 928                                         break;
 929                                 }
 930                         }
 931                         break;
 932                 }
 933                 case 1: /* high active */
 934                 {
 935                         polarity = 0;
 936                         break;
 937                 }
 938                 case 2: /* reserved */
 939                 {
 940                         printk(KERN_WARNING "broken BIOS!!\n");
 941                         polarity = 1;
 942                         break;
 943                 }
 944                 case 3: /* low active */
 945                 {
 946                         polarity = 1;
 947                         break;
 948                 }
 949                 default: /* invalid */
 950                 {
 951                         printk(KERN_WARNING "broken BIOS!!\n");
 952                         polarity = 1;
 953                         break;
 954                 }
 955         }
 956         return polarity;
 957 }
 958
 959 static int MPBIOS_trigger(int idx)
 960 {
 961         int bus = mp_irqs[idx].mpc_srcbus;
 962         int trigger;
 963
 964         /*
 965          * Determine IRQ trigger mode (edge or level sensitive):
 966          */
 967         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 968         {
 969                 case 0: /* conforms, ie. bus-type dependent */
 970                 {
 971                         switch (mp_bus_id_to_type[bus])
 972                         {
 973                                 case MP_BUS_ISA: /* ISA pin */
 974                                 {
 975                                         trigger = default_ISA_trigger(idx);
 976                                         break;
 977                                 }
 978                                 case MP_BUS_EISA: /* EISA pin */
 979                                 {
 980                                         trigger = default_EISA_trigger(idx);
 981                                         break;
 982                                 }
 983                                 case MP_BUS_PCI: /* PCI pin */
 984                                 {
 985                                         trigger = default_PCI_trigger(idx);
 986                                         break;
 987                                 }
 988                                 case MP_BUS_MCA: /* MCA pin */
 989                                 {
 990                                         trigger = default_MCA_trigger(idx);
 991                                         break;
 992                                 }
 993                                 case MP_BUS_NEC98: /* NEC 98 pin */
 994                                 {
 995                                         trigger = default_NEC98_trigger(idx);
 996                                         break;
 997                                 }
 998                                 default:
 999                                 {
1000                                         printk(KERN_WARNING "broken BIOS!!\n");
1001                                         trigger = 1;
1002                                         break;
1003                                 }
1004                         }
1005                         break;
1006                 }
1007                 case 1: /* edge */
1008                 {
1009                         trigger = 0;
1010                         break;
1011                 }
1012                 case 2: /* reserved */
1013                 {
1014                         printk(KERN_WARNING "broken BIOS!!\n");
1015                         trigger = 1;
1016                         break;
1017                 }
1018                 case 3: /* level */
1019                 {
1020                         trigger = 1;
1021                         break;
1022                 }
1023                 default: /* invalid */
1024                 {
1025                         printk(KERN_WARNING "broken BIOS!!\n");
1026                         trigger = 0;
1027                         break;
1028                 }
1029         }
1030         return trigger;
1031 }
1032
1033 static inline int irq_polarity(int idx)
1034 {
1035         return MPBIOS_polarity(idx);
1036 }
1037
1038 static inline int irq_trigger(int idx)
1039 {
1040         return MPBIOS_trigger(idx);
1041 }
1042
1043 static int pin_2_irq(int idx, int apic, int pin)
1044 {
1045         int irq, i;
1046         int bus = mp_irqs[idx].mpc_srcbus;
1047
1048         /*
1049          * Debugging check, we are in big trouble if this message pops up!
1050          */
1051         if (mp_irqs[idx].mpc_dstirq != pin)
1052                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1053
1054         switch (mp_bus_id_to_type[bus])
1055         {
1056                 case MP_BUS_ISA: /* ISA pin */
1057                 case MP_BUS_EISA:
1058                 case MP_BUS_MCA:
1059                 case MP_BUS_NEC98:
1060                 {
1061                         irq = mp_irqs[idx].mpc_srcbusirq;
1062                         break;
1063                 }
1064                 case MP_BUS_PCI: /* PCI pin */
1065                 {
1066                         /*
1067                          * PCI IRQs are mapped in order
1068                          */
1069                         i = irq = 0;
1070                         while (i < apic)
1071                                 irq += nr_ioapic_registers[i++];
1072                         irq += pin;
1073
1074                         /*
1075                          * For MPS mode, so far only needed by ES7000 platform
1076                          */
1077                         if (ioapic_renumber_irq)
1078                                 irq = ioapic_renumber_irq(apic, irq);
1079
1080                         break;
1081                 }
1082                 default:
1083                 {
1084                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1085                         irq = 0;
1086                         break;
1087                 }
1088         }
1089
1090         /*
1091          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1092          */
1093         if ((pin >= 16) && (pin <= 23)) {
1094                 if (pirq_entries[pin-16] != -1) {
1095                         if (!pirq_entries[pin-16]) {
1096                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1097                                                 "disabling PIRQ%d\n", pin-16);
1098                         } else {
1099                                 irq = pirq_entries[pin-16];
1100                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1101                                                 "using PIRQ%d -> IRQ %d\n",
1102                                                 pin-16, irq);
1103                         }
1104                 }
1105         }
1106         return irq;
1107 }
1108
1109 static inline int IO_APIC_irq_trigger(int irq)
1110 {
1111         int apic, idx, pin;
1112
1113         for (apic = 0; apic < nr_ioapics; apic++) {
1114                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1115                         idx = find_irq_entry(apic,pin,mp_INT);
1116                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1117                                 return irq_trigger(idx);
1118                 }
1119         }
1120         /*
1121          * nonexistent IRQs are edge default
1122          */
1123         return 0;
1124 }
1125
1126 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1127 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
1128
1129 int assign_irq_vector(int irq)
1130 {
1131         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1132
1133         BUG_ON(irq >= NR_IRQ_VECTORS);
1134         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1135                 return IO_APIC_VECTOR(irq);
1136 next:
1137         current_vector += 8;
1138         if (current_vector == SYSCALL_VECTOR)
1139                 goto next;
1140
1141         if (current_vector >= FIRST_SYSTEM_VECTOR) {
1142                 offset++;
1143                 if (!(offset%8))
1144                         return -ENOSPC;
1145                 current_vector = FIRST_DEVICE_VECTOR + offset;
1146         }
1147
1148         vector_irq[current_vector] = irq;
1149         if (irq != AUTO_ASSIGN)
1150                 IO_APIC_VECTOR(irq) = current_vector;
1151
1152         return current_vector;
1153 }
1154
1155 static struct hw_interrupt_type ioapic_level_type;
1156 static struct hw_interrupt_type ioapic_edge_type;
1157
1158 #define IOAPIC_AUTO     -1
1159 #define IOAPIC_EDGE     0
1160 #define IOAPIC_LEVEL    1
1161
1162 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1163 {
1164         if (use_pci_vector() && !platform_legacy_irq(irq)) {
1165                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1166                                 trigger == IOAPIC_LEVEL)
1167                         irq_desc[vector].handler = &ioapic_level_type;
1168                 else
1169                         irq_desc[vector].handler = &ioapic_edge_type;
1170                 set_intr_gate(vector, interrupt[vector]);
1171         } else  {
1172                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1173                                 trigger == IOAPIC_LEVEL)
1174                         irq_desc[irq].handler = &ioapic_level_type;
1175                 else
1176                         irq_desc[irq].handler = &ioapic_edge_type;
1177                 set_intr_gate(vector, interrupt[irq]);
1178         }
1179 }
1180
1181 void __init setup_IO_APIC_irqs(void)
1182 {
1183         struct IO_APIC_route_entry entry;
1184         int apic, pin, idx, irq, first_notcon = 1, vector;
1185         unsigned long flags;
1186
1187         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1188
1189         for (apic = 0; apic < nr_ioapics; apic++) {
1190         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1191
1192                 /*
1193                  * add it to the IO-APIC irq-routing table:
1194                  */
1195                 memset(&entry,0,sizeof(entry));
1196
1197                 entry.delivery_mode = INT_DELIVERY_MODE;
1198                 entry.dest_mode = INT_DEST_MODE;
1199                 entry.mask = 0;                         /* enable IRQ */
1200                 entry.dest.logical.logical_dest =
1201                                         cpu_mask_to_apicid(TARGET_CPUS);
1202
1203                 idx = find_irq_entry(apic,pin,mp_INT);
1204                 if (idx == -1) {
1205                         if (first_notcon) {
1206                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1207                                                 " IO-APIC (apicid-pin) %d-%d",
1208                                                 mp_ioapics[apic].mpc_apicid,
1209                                                 pin);
1210                                 first_notcon = 0;
1211                         } else
1212                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1213                                         mp_ioapics[apic].mpc_apicid, pin);
1214                         continue;
1215                 }
1216
1217                 entry.trigger = irq_trigger(idx);
1218                 entry.polarity = irq_polarity(idx);
1219
1220                 if (irq_trigger(idx)) {
1221                         entry.trigger = 1;
1222                         entry.mask = 1;
1223                 }
1224
1225                 irq = pin_2_irq(idx, apic, pin);
1226                 /*
1227                  * skip adding the timer int on secondary nodes, which causes
1228                  * a small but painful rift in the time-space continuum
1229                  */
1230                 if (multi_timer_check(apic, irq))
1231                         continue;
1232                 else
1233                         add_pin_to_irq(irq, apic, pin);
1234
1235                 if (!apic && !IO_APIC_IRQ(irq))
1236                         continue;
1237
1238                 if (IO_APIC_IRQ(irq)) {
1239                         vector = assign_irq_vector(irq);
1240                         entry.vector = vector;
1241                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1242
1243                         if (!apic && (irq < 16))
1244                                 disable_8259A_irq(irq);
1245                 }
1246                 spin_lock_irqsave(&ioapic_lock, flags);
1247                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1248                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1249                 spin_unlock_irqrestore(&ioapic_lock, flags);
1250         }
1251         }
1252
1253         if (!first_notcon)
1254                 apic_printk(APIC_VERBOSE, " not connected.\n");
1255 }
1256
1257 /*
1258  * Set up the 8259A-master output pin:
1259  */
1260 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
1261 {
1262         struct IO_APIC_route_entry entry;
1263         unsigned long flags;
1264
1265         memset(&entry,0,sizeof(entry));
1266
1267         disable_8259A_irq(0);
1268
1269         /* mask LVT0 */
1270         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1271
1272         /*
1273          * We use logical delivery to get the timer IRQ
1274          * to the first CPU.
1275          */
1276         entry.dest_mode = INT_DEST_MODE;
1277         entry.mask = 0;                                 /* unmask IRQ now */
1278         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1279         entry.delivery_mode = INT_DELIVERY_MODE;
1280         entry.polarity = 0;
1281         entry.trigger = 0;
1282         entry.vector = vector;
1283
1284         /*
1285          * The timer IRQ doesn't have to know that behind the
1286          * scene we have a 8259A-master in AEOI mode ...
1287          */
1288         irq_desc[0].handler = &ioapic_edge_type;
1289
1290         /*
1291          * Add it to the IO-APIC irq-routing table:
1292          */
1293         spin_lock_irqsave(&ioapic_lock, flags);
1294         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1295         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1296         spin_unlock_irqrestore(&ioapic_lock, flags);
1297
1298         enable_8259A_irq(0);
1299 }
1300
1301 static inline void UNEXPECTED_IO_APIC(void)
1302 {
1303 }
1304
1305 void __init print_IO_APIC(void)
1306 {
1307         int apic, i;
1308         union IO_APIC_reg_00 reg_00;
1309         union IO_APIC_reg_01 reg_01;
1310         union IO_APIC_reg_02 reg_02;
1311         union IO_APIC_reg_03 reg_03;
1312         unsigned long flags;
1313
1314         if (apic_verbosity == APIC_QUIET)
1315                 return;
1316
1317         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1318         for (i = 0; i < nr_ioapics; i++)
1319                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1320                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1321
1322         /*
1323          * We are a bit conservative about what we expect.  We have to
1324          * know about every hardware change ASAP.
1325          */
1326         printk(KERN_INFO "testing the IO APIC.......................\n");
1327
1328         for (apic = 0; apic < nr_ioapics; apic++) {
1329
1330         spin_lock_irqsave(&ioapic_lock, flags);
1331         reg_00.raw = io_apic_read(apic, 0);
1332         reg_01.raw = io_apic_read(apic, 1);
1333         if (reg_01.bits.version >= 0x10)
1334                 reg_02.raw = io_apic_read(apic, 2);
1335         if (reg_01.bits.version >= 0x20)
1336                 reg_03.raw = io_apic_read(apic, 3);
1337         spin_unlock_irqrestore(&ioapic_lock, flags);
1338
1339         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1340         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1341         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1342         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1343         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1344         if (reg_00.bits.ID >= get_physical_broadcast())
1345                 UNEXPECTED_IO_APIC();
1346         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1347                 UNEXPECTED_IO_APIC();
1348
1349         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1350         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1351         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1352                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1353                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1354                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1355                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1356                 (reg_01.bits.entries != 0x2E) &&
1357                 (reg_01.bits.entries != 0x3F)
1358         )
1359                 UNEXPECTED_IO_APIC();
1360
1361         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1362         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1363         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1364                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1365                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1366                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1367                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1368         )
1369                 UNEXPECTED_IO_APIC();
1370         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1371                 UNEXPECTED_IO_APIC();
1372
1373         /*
1374          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1375          * but the value of reg_02 is read as the previous read register
1376          * value, so ignore it if reg_02 == reg_01.
1377          */
1378         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1379                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1380                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1381                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1382                         UNEXPECTED_IO_APIC();
1383         }
1384
1385         /*
1386          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1387          * or reg_03, but the value of reg_0[23] is read as the previous read
1388          * register value, so ignore it if reg_03 == reg_0[12].
1389          */
1390         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1391             reg_03.raw != reg_01.raw) {
1392                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1393                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1394                 if (reg_03.bits.__reserved_1)
1395                         UNEXPECTED_IO_APIC();
1396         }
1397
1398         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1399
1400         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1401                           " Stat Dest Deli Vect:   \n");
1402
1403         for (i = 0; i <= reg_01.bits.entries; i++) {
1404                 struct IO_APIC_route_entry entry;
1405
1406                 spin_lock_irqsave(&ioapic_lock, flags);
1407                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1408                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1409                 spin_unlock_irqrestore(&ioapic_lock, flags);
1410
1411                 printk(KERN_DEBUG " %02x %03X %02X  ",
1412                         i,
1413                         entry.dest.logical.logical_dest,
1414                         entry.dest.physical.physical_dest
1415                 );
1416
1417                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1418                         entry.mask,
1419                         entry.trigger,
1420                         entry.irr,
1421                         entry.polarity,
1422                         entry.delivery_status,
1423                         entry.dest_mode,
1424                         entry.delivery_mode,
1425                         entry.vector
1426                 );
1427         }
1428         }
1429         if (use_pci_vector())
1430                 printk(KERN_INFO "Using vector-based indexing\n");
1431         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1432         for (i = 0; i < NR_IRQS; i++) {
1433                 struct irq_pin_list *entry = irq_2_pin + i;
1434                 if (entry->pin < 0)
1435                         continue;
1436                 if (use_pci_vector() && !platform_legacy_irq(i))
1437                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1438                 else
1439                         printk(KERN_DEBUG "IRQ%d ", i);
1440                 for (;;) {
1441                         printk("-> %d:%d", entry->apic, entry->pin);
1442                         if (!entry->next)
1443                                 break;
1444                         entry = irq_2_pin + entry->next;
1445                 }
1446                 printk("\n");
1447         }
1448
1449         printk(KERN_INFO ".................................... done.\n");
1450
1451         return;
1452 }
1453
1454 static void print_APIC_bitfield (int base)
1455 {
1456         unsigned int v;
1457         int i, j;
1458
1459         if (apic_verbosity == APIC_QUIET)
1460                 return;
1461
1462         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1463         for (i = 0; i < 8; i++) {
1464                 v = apic_read(base + i*0x10);
1465                 for (j = 0; j < 32; j++) {
1466                         if (v & (1<<j))
1467                                 printk("1");
1468                         else
1469                                 printk("0");
1470                 }
1471                 printk("\n");
1472         }
1473 }
1474
1475 void /*__init*/ print_local_APIC(void * dummy)
1476 {
1477         unsigned int v, ver, maxlvt;
1478
1479         if (apic_verbosity == APIC_QUIET)
1480                 return;
1481
1482         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1483                 smp_processor_id(), hard_smp_processor_id());
1484         v = apic_read(APIC_ID);
1485         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1486         v = apic_read(APIC_LVR);
1487         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1488         ver = GET_APIC_VERSION(v);
1489         maxlvt = get_maxlvt();
1490
1491         v = apic_read(APIC_TASKPRI);
1492         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1493
1494         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1495                 v = apic_read(APIC_ARBPRI);
1496                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1497                         v & APIC_ARBPRI_MASK);
1498                 v = apic_read(APIC_PROCPRI);
1499                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1500         }
1501
1502         v = apic_read(APIC_EOI);
1503         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1504         v = apic_read(APIC_RRR);
1505         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1506         v = apic_read(APIC_LDR);
1507         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1508         v = apic_read(APIC_DFR);
1509         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1510         v = apic_read(APIC_SPIV);
1511         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1512
1513         printk(KERN_DEBUG "... APIC ISR field:\n");
1514         print_APIC_bitfield(APIC_ISR);
1515         printk(KERN_DEBUG "... APIC TMR field:\n");
1516         print_APIC_bitfield(APIC_TMR);
1517         printk(KERN_DEBUG "... APIC IRR field:\n");
1518         print_APIC_bitfield(APIC_IRR);
1519
1520         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1521                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1522                         apic_write(APIC_ESR, 0);
1523                 v = apic_read(APIC_ESR);
1524                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1525         }
1526
1527         v = apic_read(APIC_ICR);
1528         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1529         v = apic_read(APIC_ICR2);
1530         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1531
1532         v = apic_read(APIC_LVTT);
1533         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1534
1535         if (maxlvt > 3) {                       /* PC is LVT#4. */
1536                 v = apic_read(APIC_LVTPC);
1537                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1538         }
1539         v = apic_read(APIC_LVT0);
1540         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1541         v = apic_read(APIC_LVT1);
1542         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1543
1544         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1545                 v = apic_read(APIC_LVTERR);
1546                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1547         }
1548
1549         v = apic_read(APIC_TMICT);
1550         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1551         v = apic_read(APIC_TMCCT);
1552         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1553         v = apic_read(APIC_TDCR);
1554         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1555         printk("\n");
1556 }
1557
1558 void print_all_local_APICs (void)
1559 {
1560         on_each_cpu(print_local_APIC, NULL, 1, 1);
1561 }
1562
1563 void /*__init*/ print_PIC(void)
1564 {
1565         extern spinlock_t i8259A_lock;
1566         unsigned int v;
1567         unsigned long flags;
1568
1569         if (apic_verbosity == APIC_QUIET)
1570                 return;
1571
1572         printk(KERN_DEBUG "\nprinting PIC contents\n");
1573
1574         spin_lock_irqsave(&i8259A_lock, flags);
1575
1576         v = inb(0xa1) << 8 | inb(0x21);
1577         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1578
1579         v = inb(0xa0) << 8 | inb(0x20);
1580         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1581
1582         outb(0x0b,0xa0);
1583         outb(0x0b,0x20);
1584         v = inb(0xa0) << 8 | inb(0x20);
1585         outb(0x0a,0xa0);
1586         outb(0x0a,0x20);
1587
1588         spin_unlock_irqrestore(&i8259A_lock, flags);
1589
1590         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1591
1592         v = inb(0x4d1) << 8 | inb(0x4d0);
1593         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1594 }
1595
1596 static void __init enable_IO_APIC(void)
1597 {
1598         union IO_APIC_reg_01 reg_01;
1599         int i;
1600         unsigned long flags;
1601
1602         for (i = 0; i < PIN_MAP_SIZE; i++) {
1603                 irq_2_pin[i].pin = -1;
1604                 irq_2_pin[i].next = 0;
1605         }
1606         if (!pirqs_enabled)
1607                 for (i = 0; i < MAX_PIRQS; i++)
1608                         pirq_entries[i] = -1;
1609
1610         /*
1611          * The number of IO-APIC IRQ registers (== #pins):
1612          */
1613         for (i = 0; i < nr_ioapics; i++) {
1614                 spin_lock_irqsave(&ioapic_lock, flags);
1615                 reg_01.raw = io_apic_read(i, 1);
1616                 spin_unlock_irqrestore(&ioapic_lock, flags);
1617                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1618         }
1619
1620         /*
1621          * Do not trust the IO-APIC being empty at bootup
1622          */
1623         clear_IO_APIC();
1624 }
1625
1626 /*
1627  * Not an __init, needed by the reboot code
1628  */
1629 void disable_IO_APIC(void)
1630 {
1631         /*
1632          * Clear the IO-APIC before rebooting:
1633          */
1634         clear_IO_APIC();
1635
1636         disconnect_bsp_APIC();
1637 }
1638
1639 /*
1640  * function to set the IO-APIC physical IDs based on the
1641  * values stored in the MPC table.
1642  *
1643  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1644  */
1645
1646 #ifndef CONFIG_X86_NUMAQ
1647 static void __init setup_ioapic_ids_from_mpc(void)
1648 {
1649         union IO_APIC_reg_00 reg_00;
1650         physid_mask_t phys_id_present_map;
1651         int apic;
1652         int i;
1653         unsigned char old_id;
1654         unsigned long flags;
1655
1656         /*
1657          * This is broken; anything with a real cpu count has to
1658          * circumvent this idiocy regardless.
1659          */
1660         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1661
1662         /*
1663          * Set the IOAPIC ID to the value stored in the MPC table.
1664          */
1665         for (apic = 0; apic < nr_ioapics; apic++) {
1666
1667                 /* Read the register 0 value */
1668                 spin_lock_irqsave(&ioapic_lock, flags);
1669                 reg_00.raw = io_apic_read(apic, 0);
1670                 spin_unlock_irqrestore(&ioapic_lock, flags);
1671
1672                 old_id = mp_ioapics[apic].mpc_apicid;
1673
1674                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1675                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1676                                 apic, mp_ioapics[apic].mpc_apicid);
1677                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1678                                 reg_00.bits.ID);
1679                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1680                 }
1681
1682                 /* Don't check I/O APIC IDs for some xAPIC systems.  They have
1683                  * no meaning without the serial APIC bus. */
1684                 if (NO_IOAPIC_CHECK)
1685                         continue;
1686                 /*
1687                  * Sanity check, is the ID really free? Every APIC in a
1688                  * system must have a unique ID or we get lots of nice
1689                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1690                  */
1691                 if (check_apicid_used(phys_id_present_map,
1692                                         mp_ioapics[apic].mpc_apicid)) {
1693                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1694                                 apic, mp_ioapics[apic].mpc_apicid);
1695                         for (i = 0; i < get_physical_broadcast(); i++)
1696                                 if (!physid_isset(i, phys_id_present_map))
1697                                         break;
1698                         if (i >= get_physical_broadcast())
1699                                 panic("Max APIC ID exceeded!\n");
1700                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1701                                 i);
1702                         physid_set(i, phys_id_present_map);
1703                         mp_ioapics[apic].mpc_apicid = i;
1704                 } else {
1705                         physid_mask_t tmp;
1706                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1707                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1708                                         "phys_id_present_map\n",
1709                                         mp_ioapics[apic].mpc_apicid);
1710                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1711                 }
1712
1713
1714                 /*
1715                  * We need to adjust the IRQ routing table
1716                  * if the ID changed.
1717                  */
1718                 if (old_id != mp_ioapics[apic].mpc_apicid)
1719                         for (i = 0; i < mp_irq_entries; i++)
1720                                 if (mp_irqs[i].mpc_dstapic == old_id)
1721                                         mp_irqs[i].mpc_dstapic
1722                                                 = mp_ioapics[apic].mpc_apicid;
1723
1724                 /*
1725                  * Read the right value from the MPC table and
1726                  * write it into the ID register.
1727                  */
1728                 apic_printk(APIC_VERBOSE, KERN_INFO
1729                         "...changing IO-APIC physical APIC ID to %d ...",
1730                         mp_ioapics[apic].mpc_apicid);
1731
1732                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1733                 spin_lock_irqsave(&ioapic_lock, flags);
1734                 io_apic_write(apic, 0, reg_00.raw);
1735                 spin_unlock_irqrestore(&ioapic_lock, flags);
1736
1737                 /*
1738                  * Sanity check
1739                  */
1740                 spin_lock_irqsave(&ioapic_lock, flags);
1741                 reg_00.raw = io_apic_read(apic, 0);
1742                 spin_unlock_irqrestore(&ioapic_lock, flags);
1743                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1744                         printk("could not set ID!\n");
1745                 else
1746                         apic_printk(APIC_VERBOSE, " ok.\n");
1747         }
1748 }
1749 #else
1750 static void __init setup_ioapic_ids_from_mpc(void) { }
1751 #endif
1752
1753 /*
1754  * There is a nasty bug in some older SMP boards, their mptable lies
1755  * about the timer IRQ. We do the following to work around the situation:
1756  *
1757  *      - timer IRQ defaults to IO-APIC IRQ
1758  *      - if this function detects that timer IRQs are defunct, then we fall
1759  *        back to ISA timer IRQs
1760  */
1761 static int __init timer_irq_works(void)
1762 {
1763         unsigned long t1 = jiffies;
1764
1765         local_irq_enable();
1766         /* Let ten ticks pass... */
1767         mdelay((10 * 1000) / HZ);
1768
1769         /*
1770          * Expect a few ticks at least, to be sure some possible
1771          * glue logic does not lock up after one or two first
1772          * ticks in a non-ExtINT mode.  Also the local APIC
1773          * might have cached one ExtINT interrupt.  Finally, at
1774          * least one tick may be lost due to delays.
1775          */
1776         if (jiffies - t1 > 4)
1777                 return 1;
1778
1779         return 0;
1780 }
1781
1782 /*
1783  * In the SMP+IOAPIC case it might happen that there are an unspecified
1784  * number of pending IRQ events unhandled. These cases are very rare,
1785  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1786  * better to do it this way as thus we do not have to be aware of
1787  * 'pending' interrupts in the IRQ path, except at this point.
1788  */
1789 /*
1790  * Edge triggered needs to resend any interrupt
1791  * that was delayed but this is now handled in the device
1792  * independent code.
1793  */
1794
1795 /*
1796  * Starting up a edge-triggered IO-APIC interrupt is
1797  * nasty - we need to make sure that we get the edge.
1798  * If it is already asserted for some reason, we need
1799  * return 1 to indicate that is was pending.
1800  *
1801  * This is not complete - we should be able to fake
1802  * an edge even if it isn't on the 8259A...
1803  */
1804 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1805 {
1806         int was_pending = 0;
1807         unsigned long flags;
1808
1809         spin_lock_irqsave(&ioapic_lock, flags);
1810         if (irq < 16) {
1811                 disable_8259A_irq(irq);
1812                 if (i8259A_irq_pending(irq))
1813                         was_pending = 1;
1814         }
1815         __unmask_IO_APIC_irq(irq);
1816         spin_unlock_irqrestore(&ioapic_lock, flags);
1817
1818         return was_pending;
1819 }
1820
1821 /*
1822  * Once we have recorded IRQ_PENDING already, we can mask the
1823  * interrupt for real. This prevents IRQ storms from unhandled
1824  * devices.
1825  */
1826 static void ack_edge_ioapic_irq(unsigned int irq)
1827 {
1828         move_irq(irq);
1829         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1830                                         == (IRQ_PENDING | IRQ_DISABLED))
1831                 mask_IO_APIC_irq(irq);
1832         ack_APIC_irq();
1833 }
1834
1835 /*
1836  * Level triggered interrupts can just be masked,
1837  * and shutting down and starting up the interrupt
1838  * is the same as enabling and disabling them -- except
1839  * with a startup need to return a "was pending" value.
1840  *
1841  * Level triggered interrupts are special because we
1842  * do not touch any IO-APIC register while handling
1843  * them. We ack the APIC in the end-IRQ handler, not
1844  * in the start-IRQ-handler. Protection against reentrance
1845  * from the same interrupt is still provided, both by the
1846  * generic IRQ layer and by the fact that an unacked local
1847  * APIC does not accept IRQs.
1848  */
1849 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1850 {
1851         unmask_IO_APIC_irq(irq);
1852
1853         return 0; /* don't check for pending */
1854 }
1855
1856 static void end_level_ioapic_irq (unsigned int irq)
1857 {
1858         unsigned long v;
1859         int i;
1860
1861         move_irq(irq);
1862 /*
1863  * It appears there is an erratum which affects at least version 0x11
1864  * of I/O APIC (that's the 82093AA and cores integrated into various
1865  * chipsets).  Under certain conditions a level-triggered interrupt is
1866  * erroneously delivered as edge-triggered one but the respective IRR
1867  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1868  * message but it will never arrive and further interrupts are blocked
1869  * from the source.  The exact reason is so far unknown, but the
1870  * phenomenon was observed when two consecutive interrupt requests
1871  * from a given source get delivered to the same CPU and the source is
1872  * temporarily disabled in between.
1873  *
1874  * A workaround is to simulate an EOI message manually.  We achieve it
1875  * by setting the trigger mode to edge and then to level when the edge
1876  * trigger mode gets detected in the TMR of a local APIC for a
1877  * level-triggered interrupt.  We mask the source for the time of the
1878  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1879  * The idea is from Manfred Spraul.  --macro
1880  */
1881         i = IO_APIC_VECTOR(irq);
1882
1883         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1884
1885         ack_APIC_irq();
1886
1887         if (!(v & (1 << (i & 0x1f)))) {
1888                 atomic_inc(&irq_mis_count);
1889                 spin_lock(&ioapic_lock);
1890                 __mask_and_edge_IO_APIC_irq(irq);
1891                 __unmask_and_level_IO_APIC_irq(irq);
1892                 spin_unlock(&ioapic_lock);
1893         }
1894 }
1895
1896 #ifdef CONFIG_PCI_MSI
1897 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1898 {
1899         int irq = vector_to_irq(vector);
1900
1901         return startup_edge_ioapic_irq(irq);
1902 }
1903
1904 static void ack_edge_ioapic_vector(unsigned int vector)
1905 {
1906         int irq = vector_to_irq(vector);
1907
1908         ack_edge_ioapic_irq(irq);
1909 }
1910
1911 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1912 {
1913         int irq = vector_to_irq(vector);
1914
1915         return startup_level_ioapic_irq (irq);
1916 }
1917
1918 static void end_level_ioapic_vector (unsigned int vector)
1919 {
1920         int irq = vector_to_irq(vector);
1921
1922         end_level_ioapic_irq(irq);
1923 }
1924
1925 static void mask_IO_APIC_vector (unsigned int vector)
1926 {
1927         int irq = vector_to_irq(vector);
1928
1929         mask_IO_APIC_irq(irq);
1930 }
1931
1932 static void unmask_IO_APIC_vector (unsigned int vector)
1933 {
1934         int irq = vector_to_irq(vector);
1935
1936         unmask_IO_APIC_irq(irq);
1937 }
1938
1939 static void set_ioapic_affinity_vector (unsigned int vector,
1940                                         cpumask_t cpu_mask)
1941 {
1942         int irq = vector_to_irq(vector);
1943
1944         set_ioapic_affinity_irq(irq, cpu_mask);
1945 }
1946 #endif
1947
1948 /*
1949  * Level and edge triggered IO-APIC interrupts need different handling,
1950  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1951  * handled with the level-triggered descriptor, but that one has slightly
1952  * more overhead. Level-triggered interrupts cannot be handled with the
1953  * edge-triggered handler, without risking IRQ storms and other ugly
1954  * races.
1955  */
1956 static struct hw_interrupt_type ioapic_edge_type = {
1957         .typename       = "IO-APIC-edge",
1958         .startup        = startup_edge_ioapic,
1959         .shutdown       = shutdown_edge_ioapic,
1960         .enable         = enable_edge_ioapic,
1961         .disable        = disable_edge_ioapic,
1962         .ack            = ack_edge_ioapic,
1963         .end            = end_edge_ioapic,
1964         .set_affinity   = set_ioapic_affinity,
1965 };
1966
1967 static struct hw_interrupt_type ioapic_level_type = {
1968         .typename       = "IO-APIC-level",
1969         .startup        = startup_level_ioapic,
1970         .shutdown       = shutdown_level_ioapic,
1971         .enable         = enable_level_ioapic,
1972         .disable        = disable_level_ioapic,
1973         .ack            = mask_and_ack_level_ioapic,
1974         .end            = end_level_ioapic,
1975         .set_affinity   = set_ioapic_affinity,
1976 };
1977
1978 static inline void init_IO_APIC_traps(void)
1979 {
1980         int irq;
1981
1982         /*
1983          * NOTE! The local APIC isn't very good at handling
1984          * multiple interrupts at the same interrupt level.
1985          * As the interrupt level is determined by taking the
1986          * vector number and shifting that right by 4, we
1987          * want to spread these out a bit so that they don't
1988          * all fall in the same interrupt level.
1989          *
1990          * Also, we've got to be careful not to trash gate
1991          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1992          */
1993         for (irq = 0; irq < NR_IRQS ; irq++) {
1994                 int tmp = irq;
1995                 if (use_pci_vector()) {
1996                         if (!platform_legacy_irq(tmp))
1997                                 if ((tmp = vector_to_irq(tmp)) == -1)
1998                                         continue;
1999                 }
2000                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2001                         /*
2002                          * Hmm.. We don't have an entry for this,
2003                          * so default to an old-fashioned 8259
2004                          * interrupt if we can..
2005                          */
2006                         if (irq < 16)
2007                                 make_8259A_irq(irq);
2008                         else
2009                                 /* Strange. Oh, well.. */
2010                                 irq_desc[irq].handler = &no_irq_type;
2011                 }
2012         }
2013 }
2014
2015 static void enable_lapic_irq (unsigned int irq)
2016 {
2017         unsigned long v;
2018
2019         v = apic_read(APIC_LVT0);
2020         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2021 }
2022
2023 static void disable_lapic_irq (unsigned int irq)
2024 {
2025         unsigned long v;
2026
2027         v = apic_read(APIC_LVT0);
2028         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2029 }
2030
2031 static void ack_lapic_irq (unsigned int irq)
2032 {
2033         ack_APIC_irq();
2034 }
2035
2036 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2037
2038 static struct hw_interrupt_type lapic_irq_type = {
2039         .typename       = "local-APIC-edge",
2040         .startup        = NULL, /* startup_irq() not used for IRQ0 */
2041         .shutdown       = NULL, /* shutdown_irq() not used for IRQ0 */
2042         .enable         = enable_lapic_irq,
2043         .disable        = disable_lapic_irq,
2044         .ack            = ack_lapic_irq,
2045         .end            = end_lapic_irq
2046 };
2047
2048 static void setup_nmi (void)
2049 {
2050         /*
2051          * Dirty trick to enable the NMI watchdog ...
2052          * We put the 8259A master into AEOI mode and
2053          * unmask on all local APICs LVT0 as NMI.
2054          *
2055          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2056          * is from Maciej W. Rozycki - so we do not have to EOI from
2057          * the NMI handler or the timer interrupt.
2058          */
2059         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2060
2061         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2062
2063         apic_printk(APIC_VERBOSE, " done.\n");
2064 }
2065
2066 /*
2067  * This looks a bit hackish but it's about the only one way of sending
2068  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2069  * not support the ExtINT mode, unfortunately.  We need to send these
2070  * cycles as some i82489DX-based boards have glue logic that keeps the
2071  * 8259A interrupt line asserted until INTA.  --macro
2072  */
2073 static inline void unlock_ExtINT_logic(void)
2074 {
2075         int pin, i;
2076         struct IO_APIC_route_entry entry0, entry1;
2077         unsigned char save_control, save_freq_select;
2078         unsigned long flags;
2079
2080         pin = find_isa_irq_pin(8, mp_INT);
2081         if (pin == -1)
2082                 return;
2083
2084         spin_lock_irqsave(&ioapic_lock, flags);
2085         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
2086         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
2087         spin_unlock_irqrestore(&ioapic_lock, flags);
2088         clear_IO_APIC_pin(0, pin);
2089
2090         memset(&entry1, 0, sizeof(entry1));
2091
2092         entry1.dest_mode = 0;                   /* physical delivery */
2093         entry1.mask = 0;                        /* unmask IRQ now */
2094         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2095         entry1.delivery_mode = dest_ExtINT;
2096         entry1.polarity = entry0.polarity;
2097         entry1.trigger = 0;
2098         entry1.vector = 0;
2099
2100         spin_lock_irqsave(&ioapic_lock, flags);
2101         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2102         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2103         spin_unlock_irqrestore(&ioapic_lock, flags);
2104
2105         save_control = CMOS_READ(RTC_CONTROL);
2106         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2107         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2108                    RTC_FREQ_SELECT);
2109         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2110
2111         i = 100;
2112         while (i-- > 0) {
2113                 mdelay(10);
2114                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2115                         i -= 10;
2116         }
2117
2118         CMOS_WRITE(save_control, RTC_CONTROL);
2119         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2120         clear_IO_APIC_pin(0, pin);
2121
2122         spin_lock_irqsave(&ioapic_lock, flags);
2123         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2124         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2125         spin_unlock_irqrestore(&ioapic_lock, flags);
2126 }
2127
2128 /*
2129  * This code may look a bit paranoid, but it's supposed to cooperate with
2130  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2131  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2132  * fanatically on his truly buggy board.
2133  */
2134 static inline void check_timer(void)
2135 {
2136         int pin1, pin2;
2137         int vector;
2138
2139         /*
2140          * get/set the timer IRQ vector:
2141          */
2142         disable_8259A_irq(0);
2143         vector = assign_irq_vector(0);
2144         set_intr_gate(vector, interrupt[0]);
2145
2146         /*
2147          * Subtle, code in do_timer_interrupt() expects an AEOI
2148          * mode for the 8259A whenever interrupts are routed
2149          * through I/O APICs.  Also IRQ0 has to be enabled in
2150          * the 8259A which implies the virtual wire has to be
2151          * disabled in the local APIC.
2152          */
2153         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2154         init_8259A(1);
2155         timer_ack = 1;
2156         enable_8259A_irq(0);
2157
2158         pin1 = find_isa_irq_pin(0, mp_INT);
2159         pin2 = find_isa_irq_pin(0, mp_ExtINT);
2160
2161         printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
2162
2163         if (pin1 != -1) {
2164                 /*
2165                  * Ok, does IRQ0 through the IOAPIC work?
2166                  */
2167                 unmask_IO_APIC_irq(0);
2168                 if (timer_irq_works()) {
2169                         if (nmi_watchdog == NMI_IO_APIC) {
2170                                 disable_8259A_irq(0);
2171                                 setup_nmi();
2172                                 enable_8259A_irq(0);
2173                                 check_nmi_watchdog();
2174                         }
2175                         return;
2176                 }
2177                 clear_IO_APIC_pin(0, pin1);
2178                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2179         }
2180
2181         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2182         if (pin2 != -1) {
2183                 printk("\n..... (found pin %d) ...", pin2);
2184                 /*
2185                  * legacy devices should be connected to IO APIC #0
2186                  */
2187                 setup_ExtINT_IRQ0_pin(pin2, vector);
2188                 if (timer_irq_works()) {
2189                         printk("works.\n");
2190                         if (pin1 != -1)
2191                                 replace_pin_at_irq(0, 0, pin1, 0, pin2);
2192                         else
2193                                 add_pin_to_irq(0, 0, pin2);
2194                         if (nmi_watchdog == NMI_IO_APIC) {
2195                                 setup_nmi();
2196                                 check_nmi_watchdog();
2197                         }
2198                         return;
2199                 }
2200                 /*
2201                  * Cleanup, just in case ...
2202                  */
2203                 clear_IO_APIC_pin(0, pin2);
2204         }
2205         printk(" failed.\n");
2206
2207         if (nmi_watchdog == NMI_IO_APIC) {
2208                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2209                 nmi_watchdog = 0;
2210         }
2211
2212         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2213
2214         disable_8259A_irq(0);
2215         irq_desc[0].handler = &lapic_irq_type;
2216         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2217         enable_8259A_irq(0);
2218
2219         if (timer_irq_works()) {
2220                 printk(" works.\n");
2221                 return;
2222         }
2223         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2224         printk(" failed.\n");
2225
2226         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2227
2228         timer_ack = 0;
2229         init_8259A(0);
2230         make_8259A_irq(0);
2231         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2232
2233         unlock_ExtINT_logic();
2234
2235         if (timer_irq_works()) {
2236                 printk(" works.\n");
2237                 return;
2238         }
2239         printk(" failed :(.\n");
2240         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2241                 "report.  Then try booting with the 'noapic' option");
2242 }
2243
2244 /*
2245  *
2246  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2247  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2248  *   Linux doesn't really care, as it's not actually used
2249  *   for any interrupt handling anyway.
2250  */
2251 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2252
2253 void __init setup_IO_APIC(void)
2254 {
2255         enable_IO_APIC();
2256
2257         if (acpi_ioapic)
2258                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2259         else
2260                 io_apic_irqs = ~PIC_IRQS;
2261
2262         printk("ENABLING IO-APIC IRQs\n");
2263
2264         /*
2265          * Set up IO-APIC IRQ routing.
2266          */
2267         if (!acpi_ioapic)
2268                 setup_ioapic_ids_from_mpc();
2269         sync_Arb_IDs();
2270         setup_IO_APIC_irqs();
2271         init_IO_APIC_traps();
2272         check_timer();
2273         if (!acpi_ioapic)
2274                 print_IO_APIC();
2275 }
2276
2277 /*
2278  *      Called after all the initialization is done. If we didnt find any
2279  *      APIC bugs then we can allow the modify fast path
2280  */
2281
2282 static int __init io_apic_bug_finalize(void)
2283 {
2284         if(sis_apic_bug == -1)
2285                 sis_apic_bug = 0;
2286         return 0;
2287 }
2288
2289 late_initcall(io_apic_bug_finalize);
2290
2291 struct sysfs_ioapic_data {
2292         struct sys_device dev;
2293         struct IO_APIC_route_entry entry[0];
2294 };
2295 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2296
2297 static int ioapic_suspend(struct sys_device *dev, u32 state)
2298 {
2299         struct IO_APIC_route_entry *entry;
2300         struct sysfs_ioapic_data *data;
2301         unsigned long flags;
2302         int i;
2303
2304         data = container_of(dev, struct sysfs_ioapic_data, dev);
2305         entry = data->entry;
2306         spin_lock_irqsave(&ioapic_lock, flags);
2307         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2308                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2309                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2310         }
2311         spin_unlock_irqrestore(&ioapic_lock, flags);
2312
2313         return 0;
2314 }
2315
2316 static int ioapic_resume(struct sys_device *dev)
2317 {
2318         struct IO_APIC_route_entry *entry;
2319         struct sysfs_ioapic_data *data;
2320         unsigned long flags;
2321         union IO_APIC_reg_00 reg_00;
2322         int i;
2323
2324         data = container_of(dev, struct sysfs_ioapic_data, dev);
2325         entry = data->entry;
2326
2327         spin_lock_irqsave(&ioapic_lock, flags);
2328         reg_00.raw = io_apic_read(dev->id, 0);
2329         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2330                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2331                 io_apic_write(dev->id, 0, reg_00.raw);
2332         }
2333         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2334                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2335                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2336         }
2337         spin_unlock_irqrestore(&ioapic_lock, flags);
2338
2339         return 0;
2340 }
2341
2342 static struct sysdev_class ioapic_sysdev_class = {
2343         set_kset_name("ioapic"),
2344         .suspend = ioapic_suspend,
2345         .resume = ioapic_resume,
2346 };
2347
2348 static int __init ioapic_init_sysfs(void)
2349 {
2350         struct sys_device * dev;
2351         int i, size, error = 0;
2352
2353         error = sysdev_class_register(&ioapic_sysdev_class);
2354         if (error)
2355                 return error;
2356
2357         for (i = 0; i < nr_ioapics; i++ ) {
2358                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2359                         * sizeof(struct IO_APIC_route_entry);
2360                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2361                 if (!mp_ioapic_data[i]) {
2362                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2363                         continue;
2364                 }
2365                 memset(mp_ioapic_data[i], 0, size);
2366                 dev = &mp_ioapic_data[i]->dev;
2367                 dev->id = i;
2368                 dev->cls = &ioapic_sysdev_class;
2369                 error = sysdev_register(dev);
2370                 if (error) {
2371                         kfree(mp_ioapic_data[i]);
2372                         mp_ioapic_data[i] = NULL;
2373                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2374                         continue;
2375                 }
2376         }
2377
2378         return 0;
2379 }
2380
2381 device_initcall(ioapic_init_sysfs);
2382
2383 /* --------------------------------------------------------------------------
2384                           ACPI-based IOAPIC Configuration
2385    -------------------------------------------------------------------------- */
2386
2387 #ifdef CONFIG_ACPI_BOOT
2388
2389 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2390 {
2391         union IO_APIC_reg_00 reg_00;
2392         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2393         physid_mask_t tmp;
2394         unsigned long flags;
2395         int i = 0;
2396
2397         /*
2398          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2399          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2400          * supports up to 16 on one shared APIC bus.
2401          *
2402          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2403          *      advantage of new APIC bus architecture.
2404          */
2405
2406         if (physids_empty(apic_id_map))
2407                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2408
2409         spin_lock_irqsave(&ioapic_lock, flags);
2410         reg_00.raw = io_apic_read(ioapic, 0);
2411         spin_unlock_irqrestore(&ioapic_lock, flags);
2412
2413         if (apic_id >= get_physical_broadcast()) {
2414                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2415                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2416                 apic_id = reg_00.bits.ID;
2417         }
2418
2419         /*
2420          * Every APIC in a system must have a unique ID or we get lots of nice
2421          * 'stuck on smp_invalidate_needed IPI wait' messages.
2422          */
2423         if (check_apicid_used(apic_id_map, apic_id)) {
2424
2425                 for (i = 0; i < get_physical_broadcast(); i++) {
2426                         if (!check_apicid_used(apic_id_map, i))
2427                                 break;
2428                 }
2429
2430                 if (i == get_physical_broadcast())
2431                         panic("Max apic_id exceeded!\n");
2432
2433                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2434                         "trying %d\n", ioapic, apic_id, i);
2435
2436                 apic_id = i;
2437         }
2438
2439         tmp = apicid_to_cpu_present(apic_id);
2440         physids_or(apic_id_map, apic_id_map, tmp);
2441
2442         if (reg_00.bits.ID != apic_id) {
2443                 reg_00.bits.ID = apic_id;
2444
2445                 spin_lock_irqsave(&ioapic_lock, flags);
2446                 io_apic_write(ioapic, 0, reg_00.raw);
2447                 reg_00.raw = io_apic_read(ioapic, 0);
2448                 spin_unlock_irqrestore(&ioapic_lock, flags);
2449
2450                 /* Sanity check */
2451                 if (reg_00.bits.ID != apic_id)
2452                         panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
2453         }
2454
2455         apic_printk(APIC_VERBOSE, KERN_INFO
2456                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2457
2458         return apic_id;
2459 }
2460
2461
2462 int __init io_apic_get_version (int ioapic)
2463 {
2464         union IO_APIC_reg_01    reg_01;
2465         unsigned long flags;
2466
2467         spin_lock_irqsave(&ioapic_lock, flags);
2468         reg_01.raw = io_apic_read(ioapic, 1);
2469         spin_unlock_irqrestore(&ioapic_lock, flags);
2470
2471         return reg_01.bits.version;
2472 }
2473
2474
2475 int __init io_apic_get_redir_entries (int ioapic)
2476 {
2477         union IO_APIC_reg_01    reg_01;
2478         unsigned long flags;
2479
2480         spin_lock_irqsave(&ioapic_lock, flags);
2481         reg_01.raw = io_apic_read(ioapic, 1);
2482         spin_unlock_irqrestore(&ioapic_lock, flags);
2483
2484         return reg_01.bits.entries;
2485 }
2486
2487
2488 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2489 {
2490         struct IO_APIC_route_entry entry;
2491         unsigned long flags;
2492
2493         if (!IO_APIC_IRQ(irq)) {
2494                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2495                         ioapic);
2496                 return -EINVAL;
2497         }
2498
2499         /*
2500          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2501          * Note that we mask (disable) IRQs now -- these get enabled when the
2502          * corresponding device driver registers for this IRQ.
2503          */
2504
2505         memset(&entry,0,sizeof(entry));
2506
2507         entry.delivery_mode = INT_DELIVERY_MODE;
2508         entry.dest_mode = INT_DEST_MODE;
2509         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2510         entry.trigger = edge_level;
2511         entry.polarity = active_high_low;
2512         entry.mask  = 1;
2513
2514         /*
2515          * IRQs < 16 are already in the irq_2_pin[] map
2516          */
2517         if (irq >= 16)
2518                 add_pin_to_irq(irq, ioapic, pin);
2519
2520         entry.vector = assign_irq_vector(irq);
2521
2522         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2523                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2524                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2525                 edge_level, active_high_low);
2526
2527         ioapic_register_intr(irq, entry.vector, edge_level);
2528
2529         if (!ioapic && (irq < 16))
2530                 disable_8259A_irq(irq);
2531
2532         spin_lock_irqsave(&ioapic_lock, flags);
2533         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2534         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2535         spin_unlock_irqrestore(&ioapic_lock, flags);
2536
2537         return 0;
2538 }
2539
2540 #endif /*CONFIG_ACPI_BOOT*/