2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/smp_lock.h>
22 #include <linux/kernel_stat.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/bitops.h>
29 #include <asm/mpspec.h>
30 #include <asm/io_apic.h>
32 #include <mach_apic.h>
33 #include <mach_mpparse.h>
34 #include <bios_ebda.h>
36 /* Have we found an MP table */
38 unsigned int __initdata maxcpus = NR_CPUS;
41 * Various Linux-internal data structures created from the
44 int apic_version [MAX_APICS];
45 int mp_bus_id_to_type [MAX_MP_BUSSES];
46 int mp_bus_id_to_node [MAX_MP_BUSSES];
47 int mp_bus_id_to_local [MAX_MP_BUSSES];
48 int quad_local_to_mp_bus_id [NR_CPUS/4][4];
49 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
50 static int mp_current_pci_id;
52 /* I/O APIC entries */
53 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
55 /* # of MP IRQ source entries */
56 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
58 /* MP IRQ source entries */
64 unsigned long mp_lapic_addr;
66 unsigned int def_to_bigsmp = 0;
68 /* Processor that is doing the boot up */
69 unsigned int boot_cpu_physical_apicid = -1U;
70 /* Internal processor count */
71 static unsigned int __devinitdata num_processors;
73 /* Bitmask of physically existing CPUs */
74 physid_mask_t phys_cpu_present_map;
76 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
79 * Intel MP BIOS table parsing routines:
84 * Checksum an MP configuration block.
87 static int __init mpf_checksum(unsigned char *mp, int len)
98 * Have to match translation table entries to main table entries by counter
99 * hence the mpc_record variable .... can't see a less disgusting way of
103 static int mpc_record;
104 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __initdata;
107 static void __devinit MP_processor_info (struct mpc_config_processor *m)
110 physid_mask_t phys_cpu;
112 if (!(m->mpc_cpuflag & CPU_ENABLED))
115 apicid = mpc_apic_id(m, translation_table[mpc_record]);
117 if (m->mpc_featureflag&(1<<0))
118 Dprintk(" Floating point unit present.\n");
119 if (m->mpc_featureflag&(1<<7))
120 Dprintk(" Machine Exception supported.\n");
121 if (m->mpc_featureflag&(1<<8))
122 Dprintk(" 64 bit compare & exchange supported.\n");
123 if (m->mpc_featureflag&(1<<9))
124 Dprintk(" Internal APIC present.\n");
125 if (m->mpc_featureflag&(1<<11))
126 Dprintk(" SEP present.\n");
127 if (m->mpc_featureflag&(1<<12))
128 Dprintk(" MTRR present.\n");
129 if (m->mpc_featureflag&(1<<13))
130 Dprintk(" PGE present.\n");
131 if (m->mpc_featureflag&(1<<14))
132 Dprintk(" MCA present.\n");
133 if (m->mpc_featureflag&(1<<15))
134 Dprintk(" CMOV present.\n");
135 if (m->mpc_featureflag&(1<<16))
136 Dprintk(" PAT present.\n");
137 if (m->mpc_featureflag&(1<<17))
138 Dprintk(" PSE present.\n");
139 if (m->mpc_featureflag&(1<<18))
140 Dprintk(" PSN present.\n");
141 if (m->mpc_featureflag&(1<<19))
142 Dprintk(" Cache Line Flush Instruction present.\n");
144 if (m->mpc_featureflag&(1<<21))
145 Dprintk(" Debug Trace and EMON Store present.\n");
146 if (m->mpc_featureflag&(1<<22))
147 Dprintk(" ACPI Thermal Throttle Registers present.\n");
148 if (m->mpc_featureflag&(1<<23))
149 Dprintk(" MMX present.\n");
150 if (m->mpc_featureflag&(1<<24))
151 Dprintk(" FXSR present.\n");
152 if (m->mpc_featureflag&(1<<25))
153 Dprintk(" XMM present.\n");
154 if (m->mpc_featureflag&(1<<26))
155 Dprintk(" Willamette New Instructions present.\n");
156 if (m->mpc_featureflag&(1<<27))
157 Dprintk(" Self Snoop present.\n");
158 if (m->mpc_featureflag&(1<<28))
159 Dprintk(" HT present.\n");
160 if (m->mpc_featureflag&(1<<29))
161 Dprintk(" Thermal Monitor present.\n");
162 /* 30, 31 Reserved */
165 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
166 Dprintk(" Bootup CPU\n");
167 boot_cpu_physical_apicid = m->mpc_apicid;
170 ver = m->mpc_apicver;
176 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
177 "fixing up to 0x10. (tell your hw vendor)\n",
181 apic_version[m->mpc_apicid] = ver;
183 phys_cpu = apicid_to_cpu_present(apicid);
184 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
186 if (num_processors >= NR_CPUS) {
187 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
188 " Processor ignored.\n", NR_CPUS);
192 if (num_processors >= maxcpus) {
193 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
194 " Processor ignored.\n", maxcpus);
198 cpu_set(num_processors, cpu_possible_map);
202 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
203 * but we need to work other dependencies like SMP_SUSPEND etc
204 * before this can be done without some confusion.
205 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
206 * - Ashok Raj <ashok.raj@intel.com>
208 if (num_processors > 8) {
209 switch (boot_cpu_data.x86_vendor) {
210 case X86_VENDOR_INTEL:
211 if (!APIC_XAPIC(ver)) {
215 /* If P4 and above fall through */
220 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
223 void __init MP_processor_info (struct mpc_config_processor *m)
227 #endif /* CONFIG_XEN */
229 static void __init MP_bus_info (struct mpc_config_bus *m)
233 memcpy(str, m->mpc_bustype, 6);
236 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
238 if (m->mpc_busid >= MAX_MP_BUSSES) {
239 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
240 " is too large, max. supported is %d\n",
241 m->mpc_busid, str, MAX_MP_BUSSES - 1);
245 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
246 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
247 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
248 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
249 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
250 mpc_oem_pci_bus(m, translation_table[mpc_record]);
251 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
252 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
254 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
255 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
256 } else if (strncmp(str, BUSTYPE_NEC98, sizeof(BUSTYPE_NEC98)-1) == 0) {
257 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_NEC98;
259 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
263 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
265 if (!(m->mpc_flags & MPC_APIC_USABLE))
268 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%lX.\n",
269 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
270 if (nr_ioapics >= MAX_IO_APICS) {
271 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
272 MAX_IO_APICS, nr_ioapics);
273 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
275 if (!m->mpc_apicaddr) {
276 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
277 " found in MP table, skipping!\n");
280 mp_ioapics[nr_ioapics] = *m;
284 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
286 mp_irqs [mp_irq_entries] = *m;
287 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
288 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
289 m->mpc_irqtype, m->mpc_irqflag & 3,
290 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
291 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
292 if (++mp_irq_entries == MAX_IRQ_SOURCES)
293 panic("Max # of irq sources exceeded!!\n");
296 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
298 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
299 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
300 m->mpc_irqtype, m->mpc_irqflag & 3,
301 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
302 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
304 * Well it seems all SMP boards in existence
305 * use ExtINT/LVT1 == LINT0 and
306 * NMI/LVT2 == LINT1 - the following check
307 * will show us if this assumptions is false.
308 * Until then we do not have to add baggage.
310 if ((m->mpc_irqtype == mp_ExtINT) &&
311 (m->mpc_destapiclint != 0))
313 if ((m->mpc_irqtype == mp_NMI) &&
314 (m->mpc_destapiclint != 1))
318 #ifdef CONFIG_X86_NUMAQ
319 static void __init MP_translation_info (struct mpc_config_translation *m)
321 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
323 if (mpc_record >= MAX_MPC_ENTRY)
324 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
326 translation_table[mpc_record] = m; /* stash this for later */
327 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
328 node_set_online(m->trans_quad);
332 * Read/parse the MPC oem tables
335 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
336 unsigned short oemsize)
338 int count = sizeof (*oemtable); /* the header size */
339 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
342 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
343 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
345 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
346 oemtable->oem_signature[0],
347 oemtable->oem_signature[1],
348 oemtable->oem_signature[2],
349 oemtable->oem_signature[3]);
352 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
354 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
357 while (count < oemtable->oem_length) {
361 struct mpc_config_translation *m=
362 (struct mpc_config_translation *)oemptr;
363 MP_translation_info(m);
364 oemptr += sizeof(*m);
371 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
378 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
381 if (strncmp(oem, "IBM NUMA", 8))
382 printk("Warning! May not be a NUMA-Q system!\n");
384 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
387 #endif /* CONFIG_X86_NUMAQ */
393 static int __init smp_read_mpc(struct mp_config_table *mpc)
397 int count=sizeof(*mpc);
398 unsigned char *mpt=((unsigned char *)mpc)+count;
400 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
401 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
402 *(u32 *)mpc->mpc_signature);
405 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
406 printk(KERN_ERR "SMP mptable: checksum error!\n");
409 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
410 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
414 if (!mpc->mpc_lapic) {
415 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
418 memcpy(oem,mpc->mpc_oem,8);
420 printk(KERN_INFO "OEM ID: %s ",oem);
422 memcpy(str,mpc->mpc_productid,12);
424 printk("Product ID: %s ",str);
426 mps_oem_check(mpc, oem, str);
428 printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
431 * Save the local APIC address (it might be non-default) -- but only
432 * if we're not using ACPI.
435 mp_lapic_addr = mpc->mpc_lapic;
438 * Now process the configuration blocks.
441 while (count < mpc->mpc_length) {
445 struct mpc_config_processor *m=
446 (struct mpc_config_processor *)mpt;
447 /* ACPI may have already provided this data */
449 MP_processor_info(m);
456 struct mpc_config_bus *m=
457 (struct mpc_config_bus *)mpt;
465 struct mpc_config_ioapic *m=
466 (struct mpc_config_ioapic *)mpt;
474 struct mpc_config_intsrc *m=
475 (struct mpc_config_intsrc *)mpt;
484 struct mpc_config_lintsrc *m=
485 (struct mpc_config_lintsrc *)mpt;
493 count = mpc->mpc_length;
499 clustered_apic_check();
501 printk(KERN_ERR "SMP mptable: no processors registered!\n");
502 return num_processors;
505 static int __init ELCR_trigger(unsigned int irq)
509 port = 0x4d0 + (irq >> 3);
510 return (inb(port) >> (irq & 7)) & 1;
513 static void __init construct_default_ioirq_mptable(int mpc_default_type)
515 struct mpc_config_intsrc intsrc;
517 int ELCR_fallback = 0;
519 intsrc.mpc_type = MP_INTSRC;
520 intsrc.mpc_irqflag = 0; /* conforming */
521 intsrc.mpc_srcbus = 0;
522 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
524 intsrc.mpc_irqtype = mp_INT;
527 * If true, we have an ISA/PCI system with no IRQ entries
528 * in the MP table. To prevent the PCI interrupts from being set up
529 * incorrectly, we try to use the ELCR. The sanity check to see if
530 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
531 * never be level sensitive, so we simply see if the ELCR agrees.
532 * If it does, we assume it's valid.
534 if (mpc_default_type == 5) {
535 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
537 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
538 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
540 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
545 for (i = 0; i < 16; i++) {
546 switch (mpc_default_type) {
548 if (i == 0 || i == 13)
549 continue; /* IRQ0 & IRQ13 not connected */
553 continue; /* IRQ2 is never connected */
558 * If the ELCR indicates a level-sensitive interrupt, we
559 * copy that information over to the MP table in the
560 * irqflag field (level sensitive, active high polarity).
563 intsrc.mpc_irqflag = 13;
565 intsrc.mpc_irqflag = 0;
568 intsrc.mpc_srcbusirq = i;
569 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
570 MP_intsrc_info(&intsrc);
573 intsrc.mpc_irqtype = mp_ExtINT;
574 intsrc.mpc_srcbusirq = 0;
575 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
576 MP_intsrc_info(&intsrc);
579 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
581 struct mpc_config_processor processor;
582 struct mpc_config_bus bus;
583 struct mpc_config_ioapic ioapic;
584 struct mpc_config_lintsrc lintsrc;
585 int linttypes[2] = { mp_ExtINT, mp_NMI };
589 * local APIC has default address
591 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
594 * 2 CPUs, numbered 0 & 1.
596 processor.mpc_type = MP_PROCESSOR;
597 /* Either an integrated APIC or a discrete 82489DX. */
598 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
599 processor.mpc_cpuflag = CPU_ENABLED;
600 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
601 (boot_cpu_data.x86_model << 4) |
602 boot_cpu_data.x86_mask;
603 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
604 processor.mpc_reserved[0] = 0;
605 processor.mpc_reserved[1] = 0;
606 for (i = 0; i < 2; i++) {
607 processor.mpc_apicid = i;
608 MP_processor_info(&processor);
611 bus.mpc_type = MP_BUS;
613 switch (mpc_default_type) {
616 printk(KERN_ERR "Unknown standard configuration %d\n",
621 memcpy(bus.mpc_bustype, "ISA ", 6);
626 memcpy(bus.mpc_bustype, "EISA ", 6);
630 memcpy(bus.mpc_bustype, "MCA ", 6);
633 if (mpc_default_type > 4) {
635 memcpy(bus.mpc_bustype, "PCI ", 6);
639 ioapic.mpc_type = MP_IOAPIC;
640 ioapic.mpc_apicid = 2;
641 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
642 ioapic.mpc_flags = MPC_APIC_USABLE;
643 ioapic.mpc_apicaddr = 0xFEC00000;
644 MP_ioapic_info(&ioapic);
647 * We set up most of the low 16 IO-APIC pins according to MPS rules.
649 construct_default_ioirq_mptable(mpc_default_type);
651 lintsrc.mpc_type = MP_LINTSRC;
652 lintsrc.mpc_irqflag = 0; /* conforming */
653 lintsrc.mpc_srcbusid = 0;
654 lintsrc.mpc_srcbusirq = 0;
655 lintsrc.mpc_destapic = MP_APIC_ALL;
656 for (i = 0; i < 2; i++) {
657 lintsrc.mpc_irqtype = linttypes[i];
658 lintsrc.mpc_destapiclint = i;
659 MP_lintsrc_info(&lintsrc);
663 static struct intel_mp_floating *mpf_found;
666 * Scan the memory blocks for an SMP configuration block.
668 void __init get_smp_config (void)
670 struct intel_mp_floating *mpf = mpf_found;
673 * ACPI supports both logical (e.g. Hyper-Threading) and physical
674 * processors, where MPS only supports physical.
676 if (acpi_lapic && acpi_ioapic) {
677 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
681 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
683 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
684 if (mpf->mpf_feature2 & (1<<7)) {
685 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
688 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
693 * Now see if we need to read further.
695 if (mpf->mpf_feature1 != 0) {
697 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
698 construct_default_ISA_mptable(mpf->mpf_feature1);
700 } else if (mpf->mpf_physptr) {
703 * Read the physical hardware table. Anything here will
704 * override the defaults.
706 if (!smp_read_mpc(isa_bus_to_virt(mpf->mpf_physptr))) {
707 smp_found_config = 0;
708 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
709 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
713 * If there are no explicit MP IRQ entries, then we are
714 * broken. We set up most of the low 16 IO-APIC pins to
715 * ISA defaults and hope it will work.
717 if (!mp_irq_entries) {
718 struct mpc_config_bus bus;
720 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
722 bus.mpc_type = MP_BUS;
724 memcpy(bus.mpc_bustype, "ISA ", 6);
727 construct_default_ioirq_mptable(0);
733 printk(KERN_INFO "Processors: %d\n", num_processors);
735 * Only use the first configuration found.
739 static int __init smp_scan_config (unsigned long base, unsigned long length)
741 unsigned long *bp = isa_bus_to_virt(base);
742 struct intel_mp_floating *mpf;
744 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
745 if (sizeof(*mpf) != 16)
746 printk("Error: MPF size\n");
749 mpf = (struct intel_mp_floating *)bp;
750 if ((*bp == SMP_MAGIC_IDENT) &&
751 (mpf->mpf_length == 1) &&
752 !mpf_checksum((unsigned char *)bp, 16) &&
753 ((mpf->mpf_specification == 1)
754 || (mpf->mpf_specification == 4)) ) {
756 smp_found_config = 1;
758 printk(KERN_INFO "found SMP MP-table at %08lx\n",
760 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE);
761 if (mpf->mpf_physptr) {
763 * We cannot access to MPC table to compute
764 * table size yet, as only few megabytes from
765 * the bottom is mapped now.
766 * PC-9800's MPC table places on the very last
767 * of physical memory; so that simply reserving
768 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
769 * in reserve_bootmem.
771 unsigned long size = PAGE_SIZE;
772 unsigned long end = max_low_pfn * PAGE_SIZE;
773 if (mpf->mpf_physptr + size > end)
774 size = end - mpf->mpf_physptr;
775 reserve_bootmem(mpf->mpf_physptr, size);
778 printk(KERN_INFO "found SMP MP-table at %08lx\n",
779 ((unsigned long)bp - (unsigned long)isa_bus_to_virt(base)) + base);
791 void __init find_smp_config (void)
794 unsigned int address;
798 * FIXME: Linux assumes you have 640K of base ram..
799 * this continues the error...
801 * 1) Scan the bottom 1K for a signature
802 * 2) Scan the top 1K of base RAM
803 * 3) Scan the 64K of bios
805 if (smp_scan_config(0x0,0x400) ||
806 smp_scan_config(639*0x400,0x400) ||
807 smp_scan_config(0xF0000,0x10000))
810 * If it is an SMP machine we should know now, unless the
811 * configuration is in an EISA/MCA bus machine with an
812 * extended bios data area.
814 * there is a real-mode segmented pointer pointing to the
815 * 4K EBDA area at 0x40E, calculate and scan it here.
817 * NOTE! There are Linux loaders that will corrupt the EBDA
818 * area, and as such this kind of SMP config may be less
819 * trustworthy, simply because the SMP table may have been
820 * stomped on during early boot. These loaders are buggy and
823 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
827 address = get_bios_ebda();
829 smp_scan_config(address, 0x400);
835 /* --------------------------------------------------------------------------
836 ACPI-based MP Configuration
837 -------------------------------------------------------------------------- */
841 void __init mp_register_lapic_address (
845 mp_lapic_addr = (unsigned long) address;
847 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
849 if (boot_cpu_physical_apicid == -1U)
850 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
852 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
857 void __devinit mp_register_lapic (
861 struct mpc_config_processor processor;
864 if (MAX_APICS - id <= 0) {
865 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
870 if (id == boot_cpu_physical_apicid)
874 processor.mpc_type = MP_PROCESSOR;
875 processor.mpc_apicid = id;
876 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
877 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
878 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
879 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
880 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
881 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
882 processor.mpc_reserved[0] = 0;
883 processor.mpc_reserved[1] = 0;
886 MP_processor_info(&processor);
889 #ifdef CONFIG_X86_IO_APIC
892 #define MP_MAX_IOAPIC_PIN 127
894 static struct mp_ioapic_routing {
898 u32 pin_programmed[4];
899 } mp_ioapic_routing[MAX_IO_APICS];
902 static int mp_find_ioapic (
907 /* Find the IOAPIC that manages this GSI. */
908 for (i = 0; i < nr_ioapics; i++) {
909 if ((gsi >= mp_ioapic_routing[i].gsi_base)
910 && (gsi <= mp_ioapic_routing[i].gsi_end))
914 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
920 void __init mp_register_ioapic (
928 if (nr_ioapics >= MAX_IO_APICS) {
929 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
930 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
931 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
934 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
935 " found in MADT table, skipping!\n");
941 mp_ioapics[idx].mpc_type = MP_IOAPIC;
942 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
943 mp_ioapics[idx].mpc_apicaddr = address;
946 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
948 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
949 && !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
950 tmpid = io_apic_get_unique_id(idx, id);
957 mp_ioapics[idx].mpc_apicid = tmpid;
958 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
961 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
962 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
964 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
965 mp_ioapic_routing[idx].gsi_base = gsi_base;
966 mp_ioapic_routing[idx].gsi_end = gsi_base +
967 io_apic_get_redir_entries(idx);
969 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, "
970 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
971 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
972 mp_ioapic_routing[idx].gsi_base,
973 mp_ioapic_routing[idx].gsi_end);
979 void __init mp_override_legacy_irq (
985 struct mpc_config_intsrc intsrc;
990 * Convert 'gsi' to 'ioapic.pin'.
992 ioapic = mp_find_ioapic(gsi);
995 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
998 * TBD: This check is for faulty timer entries, where the override
999 * erroneously sets the trigger to level, resulting in a HUGE
1000 * increase of timer interrupts!
1002 if ((bus_irq == 0) && (trigger == 3))
1005 intsrc.mpc_type = MP_INTSRC;
1006 intsrc.mpc_irqtype = mp_INT;
1007 intsrc.mpc_irqflag = (trigger << 2) | polarity;
1008 intsrc.mpc_srcbus = MP_ISA_BUS;
1009 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
1010 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
1011 intsrc.mpc_dstirq = pin; /* INTIN# */
1013 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
1014 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1015 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1016 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
1018 mp_irqs[mp_irq_entries] = intsrc;
1019 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1020 panic("Max # of irq sources exceeded!\n");
1025 void __init mp_config_acpi_legacy_irqs (void)
1027 struct mpc_config_intsrc intsrc;
1032 * Fabricate the legacy ISA bus (bus #31).
1034 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1035 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1038 * Older generations of ES7000 have no legacy identity mappings
1040 if (es7000_plat == 1)
1044 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1046 ioapic = mp_find_ioapic(0);
1050 intsrc.mpc_type = MP_INTSRC;
1051 intsrc.mpc_irqflag = 0; /* Conforming */
1052 intsrc.mpc_srcbus = MP_ISA_BUS;
1053 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1056 * Use the default configuration for the IRQs 0-15. Unless
1057 * overriden by (MADT) interrupt source override entries.
1059 for (i = 0; i < 16; i++) {
1062 for (idx = 0; idx < mp_irq_entries; idx++) {
1063 struct mpc_config_intsrc *irq = mp_irqs + idx;
1065 /* Do we already have a mapping for this ISA IRQ? */
1066 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1069 /* Do we already have a mapping for this IOAPIC pin */
1070 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1071 (irq->mpc_dstirq == i))
1075 if (idx != mp_irq_entries) {
1076 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1077 continue; /* IRQ already used */
1080 intsrc.mpc_irqtype = mp_INT;
1081 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1082 intsrc.mpc_dstirq = i;
1084 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1085 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1086 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1087 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1090 mp_irqs[mp_irq_entries] = intsrc;
1091 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1092 panic("Max # of irq sources exceeded!\n");
1096 #define MAX_GSI_NUM 4096
1098 int mp_register_gsi (u32 gsi, int triggering, int polarity)
1103 static int pci_irq = 16;
1105 * Mapping between Global System Interrups, which
1106 * represent all possible interrupts, and IRQs
1107 * assigned to actual devices.
1109 static int gsi_to_irq[MAX_GSI_NUM];
1111 /* Don't set up the ACPI SCI because it's already set up */
1112 if (acpi_fadt.sci_int == gsi)
1115 ioapic = mp_find_ioapic(gsi);
1117 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1121 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1123 if (ioapic_renumber_irq)
1124 gsi = ioapic_renumber_irq(ioapic, gsi);
1127 * Avoid pin reprogramming. PRTs typically include entries
1128 * with redundant pin->gsi mappings (but unique PCI devices);
1129 * we only program the IOAPIC on the first.
1131 bit = ioapic_pin % 32;
1132 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1134 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1135 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1139 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1140 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1141 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1142 return gsi_to_irq[gsi];
1145 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1147 if (triggering == ACPI_LEVEL_SENSITIVE) {
1149 * For PCI devices assign IRQs in order, avoiding gaps
1150 * due to unused I/O APIC pins.
1153 if (gsi < MAX_GSI_NUM) {
1155 * Retain the VIA chipset work-around (gsi > 15), but
1156 * avoid a problem where the 8254 timer (IRQ0) is setup
1157 * via an override (so it's not on pin 0 of the ioapic),
1158 * and at the same time, the pin 0 interrupt is a PCI
1159 * type. The gsi > 15 test could cause these two pins
1160 * to be shared as IRQ0, and they are not shareable.
1161 * So test for this condition, and if necessary, avoid
1162 * the pin collision.
1164 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
1167 * Don't assign IRQ used by ACPI SCI
1169 if (gsi == acpi_fadt.sci_int)
1171 gsi_to_irq[irq] = gsi;
1173 printk(KERN_ERR "GSI %u is too high\n", gsi);
1178 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1179 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1180 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1184 #endif /* CONFIG_X86_IO_APIC */
1185 #endif /* CONFIG_ACPI */