2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/config.h>
21 #include <linux/bootmem.h>
22 #include <linux/smp_lock.h>
23 #include <linux/kernel_stat.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/bitops.h>
30 #include <asm/mpspec.h>
31 #include <asm/io_apic.h>
33 #include <mach_apic.h>
34 #include <mach_mpparse.h>
35 #include <bios_ebda.h>
37 /* Have we found an MP table */
39 unsigned int __initdata maxcpus = NR_CPUS;
42 * Various Linux-internal data structures created from the
45 int apic_version [MAX_APICS];
46 int mp_bus_id_to_type [MAX_MP_BUSSES];
47 int mp_bus_id_to_node [MAX_MP_BUSSES];
48 int mp_bus_id_to_local [MAX_MP_BUSSES];
49 int quad_local_to_mp_bus_id [NR_CPUS/4][4];
50 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
51 static int mp_current_pci_id;
53 /* I/O APIC entries */
54 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
56 /* # of MP IRQ source entries */
57 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
59 /* MP IRQ source entries */
65 unsigned long mp_lapic_addr;
67 unsigned int def_to_bigsmp = 0;
69 /* Processor that is doing the boot up */
70 unsigned int boot_cpu_physical_apicid = -1U;
71 /* Internal processor count */
72 static unsigned int __devinitdata num_processors;
74 /* Bitmask of physically existing CPUs */
75 physid_mask_t phys_cpu_present_map;
77 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
80 * Intel MP BIOS table parsing routines:
85 * Checksum an MP configuration block.
88 static int __init mpf_checksum(unsigned char *mp, int len)
99 * Have to match translation table entries to main table entries by counter
100 * hence the mpc_record variable .... can't see a less disgusting way of
104 static int mpc_record;
105 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __initdata;
108 static void __devinit MP_processor_info (struct mpc_config_processor *m)
111 physid_mask_t phys_cpu;
113 if (!(m->mpc_cpuflag & CPU_ENABLED))
116 apicid = mpc_apic_id(m, translation_table[mpc_record]);
118 if (m->mpc_featureflag&(1<<0))
119 Dprintk(" Floating point unit present.\n");
120 if (m->mpc_featureflag&(1<<7))
121 Dprintk(" Machine Exception supported.\n");
122 if (m->mpc_featureflag&(1<<8))
123 Dprintk(" 64 bit compare & exchange supported.\n");
124 if (m->mpc_featureflag&(1<<9))
125 Dprintk(" Internal APIC present.\n");
126 if (m->mpc_featureflag&(1<<11))
127 Dprintk(" SEP present.\n");
128 if (m->mpc_featureflag&(1<<12))
129 Dprintk(" MTRR present.\n");
130 if (m->mpc_featureflag&(1<<13))
131 Dprintk(" PGE present.\n");
132 if (m->mpc_featureflag&(1<<14))
133 Dprintk(" MCA present.\n");
134 if (m->mpc_featureflag&(1<<15))
135 Dprintk(" CMOV present.\n");
136 if (m->mpc_featureflag&(1<<16))
137 Dprintk(" PAT present.\n");
138 if (m->mpc_featureflag&(1<<17))
139 Dprintk(" PSE present.\n");
140 if (m->mpc_featureflag&(1<<18))
141 Dprintk(" PSN present.\n");
142 if (m->mpc_featureflag&(1<<19))
143 Dprintk(" Cache Line Flush Instruction present.\n");
145 if (m->mpc_featureflag&(1<<21))
146 Dprintk(" Debug Trace and EMON Store present.\n");
147 if (m->mpc_featureflag&(1<<22))
148 Dprintk(" ACPI Thermal Throttle Registers present.\n");
149 if (m->mpc_featureflag&(1<<23))
150 Dprintk(" MMX present.\n");
151 if (m->mpc_featureflag&(1<<24))
152 Dprintk(" FXSR present.\n");
153 if (m->mpc_featureflag&(1<<25))
154 Dprintk(" XMM present.\n");
155 if (m->mpc_featureflag&(1<<26))
156 Dprintk(" Willamette New Instructions present.\n");
157 if (m->mpc_featureflag&(1<<27))
158 Dprintk(" Self Snoop present.\n");
159 if (m->mpc_featureflag&(1<<28))
160 Dprintk(" HT present.\n");
161 if (m->mpc_featureflag&(1<<29))
162 Dprintk(" Thermal Monitor present.\n");
163 /* 30, 31 Reserved */
166 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
167 Dprintk(" Bootup CPU\n");
168 boot_cpu_physical_apicid = m->mpc_apicid;
171 ver = m->mpc_apicver;
177 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
178 "fixing up to 0x10. (tell your hw vendor)\n",
182 apic_version[m->mpc_apicid] = ver;
184 phys_cpu = apicid_to_cpu_present(apicid);
185 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
187 if (num_processors >= NR_CPUS) {
188 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
189 " Processor ignored.\n", NR_CPUS);
193 if (num_processors >= maxcpus) {
194 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
195 " Processor ignored.\n", maxcpus);
199 cpu_set(num_processors, cpu_possible_map);
203 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
204 * but we need to work other dependencies like SMP_SUSPEND etc
205 * before this can be done without some confusion.
206 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
207 * - Ashok Raj <ashok.raj@intel.com>
209 if (num_processors > 8) {
210 switch (boot_cpu_data.x86_vendor) {
211 case X86_VENDOR_INTEL:
212 if (!APIC_XAPIC(ver)) {
216 /* If P4 and above fall through */
221 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
224 void __init MP_processor_info (struct mpc_config_processor *m)
228 #endif /* CONFIG_XEN */
230 static void __init MP_bus_info (struct mpc_config_bus *m)
234 memcpy(str, m->mpc_bustype, 6);
237 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
239 if (m->mpc_busid >= MAX_MP_BUSSES) {
240 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
241 " is too large, max. supported is %d\n",
242 m->mpc_busid, str, MAX_MP_BUSSES - 1);
246 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
247 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
248 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
249 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
250 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
251 mpc_oem_pci_bus(m, translation_table[mpc_record]);
252 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
253 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
255 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
256 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
257 } else if (strncmp(str, BUSTYPE_NEC98, sizeof(BUSTYPE_NEC98)-1) == 0) {
258 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_NEC98;
260 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
264 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
266 if (!(m->mpc_flags & MPC_APIC_USABLE))
269 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%lX.\n",
270 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
271 if (nr_ioapics >= MAX_IO_APICS) {
272 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
273 MAX_IO_APICS, nr_ioapics);
274 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
276 if (!m->mpc_apicaddr) {
277 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
278 " found in MP table, skipping!\n");
281 mp_ioapics[nr_ioapics] = *m;
285 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
287 mp_irqs [mp_irq_entries] = *m;
288 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
289 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
290 m->mpc_irqtype, m->mpc_irqflag & 3,
291 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
292 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
293 if (++mp_irq_entries == MAX_IRQ_SOURCES)
294 panic("Max # of irq sources exceeded!!\n");
297 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
299 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
300 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
301 m->mpc_irqtype, m->mpc_irqflag & 3,
302 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
303 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
305 * Well it seems all SMP boards in existence
306 * use ExtINT/LVT1 == LINT0 and
307 * NMI/LVT2 == LINT1 - the following check
308 * will show us if this assumptions is false.
309 * Until then we do not have to add baggage.
311 if ((m->mpc_irqtype == mp_ExtINT) &&
312 (m->mpc_destapiclint != 0))
314 if ((m->mpc_irqtype == mp_NMI) &&
315 (m->mpc_destapiclint != 1))
319 #ifdef CONFIG_X86_NUMAQ
320 static void __init MP_translation_info (struct mpc_config_translation *m)
322 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
324 if (mpc_record >= MAX_MPC_ENTRY)
325 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
327 translation_table[mpc_record] = m; /* stash this for later */
328 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
329 node_set_online(m->trans_quad);
333 * Read/parse the MPC oem tables
336 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
337 unsigned short oemsize)
339 int count = sizeof (*oemtable); /* the header size */
340 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
343 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
344 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
346 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
347 oemtable->oem_signature[0],
348 oemtable->oem_signature[1],
349 oemtable->oem_signature[2],
350 oemtable->oem_signature[3]);
353 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
355 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
358 while (count < oemtable->oem_length) {
362 struct mpc_config_translation *m=
363 (struct mpc_config_translation *)oemptr;
364 MP_translation_info(m);
365 oemptr += sizeof(*m);
372 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
379 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
382 if (strncmp(oem, "IBM NUMA", 8))
383 printk("Warning! May not be a NUMA-Q system!\n");
385 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
388 #endif /* CONFIG_X86_NUMAQ */
394 static int __init smp_read_mpc(struct mp_config_table *mpc)
398 int count=sizeof(*mpc);
399 unsigned char *mpt=((unsigned char *)mpc)+count;
401 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
402 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
403 *(u32 *)mpc->mpc_signature);
406 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
407 printk(KERN_ERR "SMP mptable: checksum error!\n");
410 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
411 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
415 if (!mpc->mpc_lapic) {
416 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
419 memcpy(oem,mpc->mpc_oem,8);
421 printk(KERN_INFO "OEM ID: %s ",oem);
423 memcpy(str,mpc->mpc_productid,12);
425 printk("Product ID: %s ",str);
427 mps_oem_check(mpc, oem, str);
429 printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
432 * Save the local APIC address (it might be non-default) -- but only
433 * if we're not using ACPI.
436 mp_lapic_addr = mpc->mpc_lapic;
439 * Now process the configuration blocks.
442 while (count < mpc->mpc_length) {
446 struct mpc_config_processor *m=
447 (struct mpc_config_processor *)mpt;
448 /* ACPI may have already provided this data */
450 MP_processor_info(m);
457 struct mpc_config_bus *m=
458 (struct mpc_config_bus *)mpt;
466 struct mpc_config_ioapic *m=
467 (struct mpc_config_ioapic *)mpt;
475 struct mpc_config_intsrc *m=
476 (struct mpc_config_intsrc *)mpt;
485 struct mpc_config_lintsrc *m=
486 (struct mpc_config_lintsrc *)mpt;
494 count = mpc->mpc_length;
500 clustered_apic_check();
502 printk(KERN_ERR "SMP mptable: no processors registered!\n");
503 return num_processors;
506 static int __init ELCR_trigger(unsigned int irq)
510 port = 0x4d0 + (irq >> 3);
511 return (inb(port) >> (irq & 7)) & 1;
514 static void __init construct_default_ioirq_mptable(int mpc_default_type)
516 struct mpc_config_intsrc intsrc;
518 int ELCR_fallback = 0;
520 intsrc.mpc_type = MP_INTSRC;
521 intsrc.mpc_irqflag = 0; /* conforming */
522 intsrc.mpc_srcbus = 0;
523 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
525 intsrc.mpc_irqtype = mp_INT;
528 * If true, we have an ISA/PCI system with no IRQ entries
529 * in the MP table. To prevent the PCI interrupts from being set up
530 * incorrectly, we try to use the ELCR. The sanity check to see if
531 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
532 * never be level sensitive, so we simply see if the ELCR agrees.
533 * If it does, we assume it's valid.
535 if (mpc_default_type == 5) {
536 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
538 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
539 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
541 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
546 for (i = 0; i < 16; i++) {
547 switch (mpc_default_type) {
549 if (i == 0 || i == 13)
550 continue; /* IRQ0 & IRQ13 not connected */
554 continue; /* IRQ2 is never connected */
559 * If the ELCR indicates a level-sensitive interrupt, we
560 * copy that information over to the MP table in the
561 * irqflag field (level sensitive, active high polarity).
564 intsrc.mpc_irqflag = 13;
566 intsrc.mpc_irqflag = 0;
569 intsrc.mpc_srcbusirq = i;
570 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
571 MP_intsrc_info(&intsrc);
574 intsrc.mpc_irqtype = mp_ExtINT;
575 intsrc.mpc_srcbusirq = 0;
576 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
577 MP_intsrc_info(&intsrc);
580 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
582 struct mpc_config_processor processor;
583 struct mpc_config_bus bus;
584 struct mpc_config_ioapic ioapic;
585 struct mpc_config_lintsrc lintsrc;
586 int linttypes[2] = { mp_ExtINT, mp_NMI };
590 * local APIC has default address
592 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
595 * 2 CPUs, numbered 0 & 1.
597 processor.mpc_type = MP_PROCESSOR;
598 /* Either an integrated APIC or a discrete 82489DX. */
599 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
600 processor.mpc_cpuflag = CPU_ENABLED;
601 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
602 (boot_cpu_data.x86_model << 4) |
603 boot_cpu_data.x86_mask;
604 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
605 processor.mpc_reserved[0] = 0;
606 processor.mpc_reserved[1] = 0;
607 for (i = 0; i < 2; i++) {
608 processor.mpc_apicid = i;
609 MP_processor_info(&processor);
612 bus.mpc_type = MP_BUS;
614 switch (mpc_default_type) {
617 printk(KERN_ERR "Unknown standard configuration %d\n",
622 memcpy(bus.mpc_bustype, "ISA ", 6);
627 memcpy(bus.mpc_bustype, "EISA ", 6);
631 memcpy(bus.mpc_bustype, "MCA ", 6);
634 if (mpc_default_type > 4) {
636 memcpy(bus.mpc_bustype, "PCI ", 6);
640 ioapic.mpc_type = MP_IOAPIC;
641 ioapic.mpc_apicid = 2;
642 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
643 ioapic.mpc_flags = MPC_APIC_USABLE;
644 ioapic.mpc_apicaddr = 0xFEC00000;
645 MP_ioapic_info(&ioapic);
648 * We set up most of the low 16 IO-APIC pins according to MPS rules.
650 construct_default_ioirq_mptable(mpc_default_type);
652 lintsrc.mpc_type = MP_LINTSRC;
653 lintsrc.mpc_irqflag = 0; /* conforming */
654 lintsrc.mpc_srcbusid = 0;
655 lintsrc.mpc_srcbusirq = 0;
656 lintsrc.mpc_destapic = MP_APIC_ALL;
657 for (i = 0; i < 2; i++) {
658 lintsrc.mpc_irqtype = linttypes[i];
659 lintsrc.mpc_destapiclint = i;
660 MP_lintsrc_info(&lintsrc);
664 static struct intel_mp_floating *mpf_found;
667 * Scan the memory blocks for an SMP configuration block.
669 void __init get_smp_config (void)
671 struct intel_mp_floating *mpf = mpf_found;
674 * ACPI supports both logical (e.g. Hyper-Threading) and physical
675 * processors, where MPS only supports physical.
677 if (acpi_lapic && acpi_ioapic) {
678 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
682 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
684 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
685 if (mpf->mpf_feature2 & (1<<7)) {
686 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
689 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
694 * Now see if we need to read further.
696 if (mpf->mpf_feature1 != 0) {
698 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
699 construct_default_ISA_mptable(mpf->mpf_feature1);
701 } else if (mpf->mpf_physptr) {
704 * Read the physical hardware table. Anything here will
705 * override the defaults.
707 if (!smp_read_mpc(isa_bus_to_virt(mpf->mpf_physptr))) {
708 smp_found_config = 0;
709 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
710 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
714 * If there are no explicit MP IRQ entries, then we are
715 * broken. We set up most of the low 16 IO-APIC pins to
716 * ISA defaults and hope it will work.
718 if (!mp_irq_entries) {
719 struct mpc_config_bus bus;
721 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
723 bus.mpc_type = MP_BUS;
725 memcpy(bus.mpc_bustype, "ISA ", 6);
728 construct_default_ioirq_mptable(0);
734 printk(KERN_INFO "Processors: %d\n", num_processors);
736 * Only use the first configuration found.
740 static int __init smp_scan_config (unsigned long base, unsigned long length)
742 unsigned long *bp = isa_bus_to_virt(base);
743 struct intel_mp_floating *mpf;
745 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
746 if (sizeof(*mpf) != 16)
747 printk("Error: MPF size\n");
750 mpf = (struct intel_mp_floating *)bp;
751 if ((*bp == SMP_MAGIC_IDENT) &&
752 (mpf->mpf_length == 1) &&
753 !mpf_checksum((unsigned char *)bp, 16) &&
754 ((mpf->mpf_specification == 1)
755 || (mpf->mpf_specification == 4)) ) {
757 smp_found_config = 1;
759 printk(KERN_INFO "found SMP MP-table at %08lx\n",
761 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE);
762 if (mpf->mpf_physptr) {
764 * We cannot access to MPC table to compute
765 * table size yet, as only few megabytes from
766 * the bottom is mapped now.
767 * PC-9800's MPC table places on the very last
768 * of physical memory; so that simply reserving
769 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
770 * in reserve_bootmem.
772 unsigned long size = PAGE_SIZE;
773 unsigned long end = max_low_pfn * PAGE_SIZE;
774 if (mpf->mpf_physptr + size > end)
775 size = end - mpf->mpf_physptr;
776 reserve_bootmem(mpf->mpf_physptr, size);
779 printk(KERN_INFO "found SMP MP-table at %08lx\n",
780 ((unsigned long)bp - (unsigned long)isa_bus_to_virt(base)) + base);
792 void __init find_smp_config (void)
795 unsigned int address;
799 * FIXME: Linux assumes you have 640K of base ram..
800 * this continues the error...
802 * 1) Scan the bottom 1K for a signature
803 * 2) Scan the top 1K of base RAM
804 * 3) Scan the 64K of bios
806 if (smp_scan_config(0x0,0x400) ||
807 smp_scan_config(639*0x400,0x400) ||
808 smp_scan_config(0xF0000,0x10000))
811 * If it is an SMP machine we should know now, unless the
812 * configuration is in an EISA/MCA bus machine with an
813 * extended bios data area.
815 * there is a real-mode segmented pointer pointing to the
816 * 4K EBDA area at 0x40E, calculate and scan it here.
818 * NOTE! There are Linux loaders that will corrupt the EBDA
819 * area, and as such this kind of SMP config may be less
820 * trustworthy, simply because the SMP table may have been
821 * stomped on during early boot. These loaders are buggy and
824 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
828 address = get_bios_ebda();
830 smp_scan_config(address, 0x400);
836 /* --------------------------------------------------------------------------
837 ACPI-based MP Configuration
838 -------------------------------------------------------------------------- */
842 void __init mp_register_lapic_address (
846 mp_lapic_addr = (unsigned long) address;
848 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
850 if (boot_cpu_physical_apicid == -1U)
851 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
853 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
858 void __devinit mp_register_lapic (
862 struct mpc_config_processor processor;
865 if (MAX_APICS - id <= 0) {
866 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
871 if (id == boot_cpu_physical_apicid)
875 processor.mpc_type = MP_PROCESSOR;
876 processor.mpc_apicid = id;
877 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
878 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
879 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
880 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
881 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
882 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
883 processor.mpc_reserved[0] = 0;
884 processor.mpc_reserved[1] = 0;
887 MP_processor_info(&processor);
890 #ifdef CONFIG_X86_IO_APIC
893 #define MP_MAX_IOAPIC_PIN 127
895 static struct mp_ioapic_routing {
899 u32 pin_programmed[4];
900 } mp_ioapic_routing[MAX_IO_APICS];
903 static int mp_find_ioapic (
908 /* Find the IOAPIC that manages this GSI. */
909 for (i = 0; i < nr_ioapics; i++) {
910 if ((gsi >= mp_ioapic_routing[i].gsi_base)
911 && (gsi <= mp_ioapic_routing[i].gsi_end))
915 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
921 void __init mp_register_ioapic (
929 if (nr_ioapics >= MAX_IO_APICS) {
930 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
931 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
932 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
935 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
936 " found in MADT table, skipping!\n");
942 mp_ioapics[idx].mpc_type = MP_IOAPIC;
943 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
944 mp_ioapics[idx].mpc_apicaddr = address;
947 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
949 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
950 && !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
951 tmpid = io_apic_get_unique_id(idx, id);
958 mp_ioapics[idx].mpc_apicid = tmpid;
959 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
962 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
963 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
965 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
966 mp_ioapic_routing[idx].gsi_base = gsi_base;
967 mp_ioapic_routing[idx].gsi_end = gsi_base +
968 io_apic_get_redir_entries(idx);
970 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, "
971 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
972 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
973 mp_ioapic_routing[idx].gsi_base,
974 mp_ioapic_routing[idx].gsi_end);
980 void __init mp_override_legacy_irq (
986 struct mpc_config_intsrc intsrc;
991 * Convert 'gsi' to 'ioapic.pin'.
993 ioapic = mp_find_ioapic(gsi);
996 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
999 * TBD: This check is for faulty timer entries, where the override
1000 * erroneously sets the trigger to level, resulting in a HUGE
1001 * increase of timer interrupts!
1003 if ((bus_irq == 0) && (trigger == 3))
1006 intsrc.mpc_type = MP_INTSRC;
1007 intsrc.mpc_irqtype = mp_INT;
1008 intsrc.mpc_irqflag = (trigger << 2) | polarity;
1009 intsrc.mpc_srcbus = MP_ISA_BUS;
1010 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
1011 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
1012 intsrc.mpc_dstirq = pin; /* INTIN# */
1014 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
1015 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1016 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1017 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
1019 mp_irqs[mp_irq_entries] = intsrc;
1020 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1021 panic("Max # of irq sources exceeded!\n");
1026 void __init mp_config_acpi_legacy_irqs (void)
1028 struct mpc_config_intsrc intsrc;
1033 * Fabricate the legacy ISA bus (bus #31).
1035 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1036 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1039 * Older generations of ES7000 have no legacy identity mappings
1041 if (es7000_plat == 1)
1045 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1047 ioapic = mp_find_ioapic(0);
1051 intsrc.mpc_type = MP_INTSRC;
1052 intsrc.mpc_irqflag = 0; /* Conforming */
1053 intsrc.mpc_srcbus = MP_ISA_BUS;
1054 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1057 * Use the default configuration for the IRQs 0-15. Unless
1058 * overriden by (MADT) interrupt source override entries.
1060 for (i = 0; i < 16; i++) {
1063 for (idx = 0; idx < mp_irq_entries; idx++) {
1064 struct mpc_config_intsrc *irq = mp_irqs + idx;
1066 /* Do we already have a mapping for this ISA IRQ? */
1067 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1070 /* Do we already have a mapping for this IOAPIC pin */
1071 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1072 (irq->mpc_dstirq == i))
1076 if (idx != mp_irq_entries) {
1077 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1078 continue; /* IRQ already used */
1081 intsrc.mpc_irqtype = mp_INT;
1082 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1083 intsrc.mpc_dstirq = i;
1085 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1086 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1087 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1088 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1091 mp_irqs[mp_irq_entries] = intsrc;
1092 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1093 panic("Max # of irq sources exceeded!\n");
1097 #define MAX_GSI_NUM 4096
1099 int mp_register_gsi (u32 gsi, int triggering, int polarity)
1104 static int pci_irq = 16;
1106 * Mapping between Global System Interrups, which
1107 * represent all possible interrupts, and IRQs
1108 * assigned to actual devices.
1110 static int gsi_to_irq[MAX_GSI_NUM];
1112 /* Don't set up the ACPI SCI because it's already set up */
1113 if (acpi_fadt.sci_int == gsi)
1116 ioapic = mp_find_ioapic(gsi);
1118 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1122 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1124 if (ioapic_renumber_irq)
1125 gsi = ioapic_renumber_irq(ioapic, gsi);
1128 * Avoid pin reprogramming. PRTs typically include entries
1129 * with redundant pin->gsi mappings (but unique PCI devices);
1130 * we only program the IOAPIC on the first.
1132 bit = ioapic_pin % 32;
1133 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1135 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1136 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1140 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1141 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1142 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1143 return gsi_to_irq[gsi];
1146 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1148 if (triggering == ACPI_LEVEL_SENSITIVE) {
1150 * For PCI devices assign IRQs in order, avoiding gaps
1151 * due to unused I/O APIC pins.
1154 if (gsi < MAX_GSI_NUM) {
1156 * Retain the VIA chipset work-around (gsi > 15), but
1157 * avoid a problem where the 8254 timer (IRQ0) is setup
1158 * via an override (so it's not on pin 0 of the ioapic),
1159 * and at the same time, the pin 0 interrupt is a PCI
1160 * type. The gsi > 15 test could cause these two pins
1161 * to be shared as IRQ0, and they are not shareable.
1162 * So test for this condition, and if necessary, avoid
1163 * the pin collision.
1165 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
1168 * Don't assign IRQ used by ACPI SCI
1170 if (gsi == acpi_fadt.sci_int)
1172 gsi_to_irq[irq] = gsi;
1174 printk(KERN_ERR "GSI %u is too high\n", gsi);
1179 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1180 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1181 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1185 #endif /* CONFIG_X86_IO_APIC */
1186 #endif /* CONFIG_ACPI */