2 * linux/arch/i386/nmi.c
4 * NMI watchdog support on APIC systems
6 * Started by Ingo Molnar <mingo@redhat.com>
9 * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog.
10 * Mikael Pettersson : Power Management for local APIC NMI watchdog.
11 * Mikael Pettersson : Pentium 4 support for local APIC NMI watchdog.
13 * Mikael Pettersson : PM converted to driver model. Disable/enable API.
16 #include <linux/config.h>
18 #include <linux/irq.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/smp_lock.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/module.h>
26 #include <linux/nmi.h>
27 #include <linux/sysdev.h>
28 #include <linux/dump.h>
29 #include <linux/sysctl.h>
33 #include <asm/mpspec.h>
36 #include "mach_traps.h"
38 unsigned int nmi_watchdog = NMI_NONE;
39 extern int unknown_nmi_panic;
40 static unsigned int nmi_hz = HZ;
41 static unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */
42 static unsigned int nmi_p4_cccr_val;
43 extern void show_registers(struct pt_regs *regs);
46 * lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
47 * - it may be reserved by some other driver, or not
48 * - when not reserved by some other driver, it may be used for
49 * the NMI watchdog, or not
51 * This is maintained separately from nmi_active because the NMI
52 * watchdog may also be driven from the I/O APIC timer.
54 static spinlock_t lapic_nmi_owner_lock = SPIN_LOCK_UNLOCKED;
55 static unsigned int lapic_nmi_owner;
56 #define LAPIC_NMI_WATCHDOG (1<<0)
57 #define LAPIC_NMI_RESERVED (1<<1)
60 * +1: the lapic NMI watchdog is active, but can be disabled
61 * 0: the lapic NMI watchdog has not been set up, and cannot
63 * -1: the lapic NMI watchdog is disabled, but can be enabled
67 #define K7_EVNTSEL_ENABLE (1 << 22)
68 #define K7_EVNTSEL_INT (1 << 20)
69 #define K7_EVNTSEL_OS (1 << 17)
70 #define K7_EVNTSEL_USR (1 << 16)
71 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
72 #define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
74 #define P6_EVNTSEL0_ENABLE (1 << 22)
75 #define P6_EVNTSEL_INT (1 << 20)
76 #define P6_EVNTSEL_OS (1 << 17)
77 #define P6_EVNTSEL_USR (1 << 16)
78 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED 0x79
79 #define P6_NMI_EVENT P6_EVENT_CPU_CLOCKS_NOT_HALTED
81 #define MSR_P4_MISC_ENABLE 0x1A0
82 #define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
83 #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
84 #define MSR_P4_PERFCTR0 0x300
85 #define MSR_P4_CCCR0 0x360
86 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
87 #define P4_ESCR_OS (1<<3)
88 #define P4_ESCR_USR (1<<2)
89 #define P4_CCCR_OVF_PMI0 (1<<26)
90 #define P4_CCCR_OVF_PMI1 (1<<27)
91 #define P4_CCCR_THRESHOLD(N) ((N)<<20)
92 #define P4_CCCR_COMPLEMENT (1<<19)
93 #define P4_CCCR_COMPARE (1<<18)
94 #define P4_CCCR_REQUIRED (3<<16)
95 #define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
96 #define P4_CCCR_ENABLE (1<<12)
97 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
98 CRU_ESCR0 (with any non-null event selector) through a complemented
99 max threshold. [IA32-Vol3, Section 14.9.9] */
100 #define MSR_P4_IQ_COUNTER0 0x30C
101 #define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
102 #define P4_NMI_IQ_CCCR0 \
103 (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \
104 P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
106 int __init check_nmi_watchdog (void)
108 unsigned int prev_nmi_count[NR_CPUS];
111 printk(KERN_INFO "testing NMI watchdog ... ");
113 for (cpu = 0; cpu < NR_CPUS; cpu++)
114 prev_nmi_count[cpu] = irq_stat[cpu].__nmi_count;
116 mdelay((10*1000)/nmi_hz); // wait 10 ticks
118 /* FIXME: Only boot CPU is online at this stage. Check CPUs
120 for (cpu = 0; cpu < NR_CPUS; cpu++) {
121 if (!cpu_online(cpu))
123 if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
124 printk("CPU#%d: NMI appears to be stuck!\n", cpu);
126 lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
132 /* now that we know it works we can reduce NMI frequency to
133 something more reasonable; makes a difference in some configs */
134 if (nmi_watchdog == NMI_LOCAL_APIC)
140 static int __init setup_nmi_watchdog(char *str)
144 get_option(&str, &nmi);
146 if (nmi >= NMI_INVALID)
151 * If any other x86 CPU has a local APIC, then
152 * please test the NMI stuff there and send me the
153 * missing bits. Right now Intel P6/P4 and AMD K7 only.
155 if ((nmi == NMI_LOCAL_APIC) &&
156 (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
157 (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
159 if ((nmi == NMI_LOCAL_APIC) &&
160 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
161 (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
164 * We can enable the IO-APIC watchdog
167 if (nmi == NMI_IO_APIC) {
174 __setup("nmi_watchdog=", setup_nmi_watchdog);
176 static void disable_lapic_nmi_watchdog(void)
180 switch (boot_cpu_data.x86_vendor) {
182 wrmsr(MSR_K7_EVNTSEL0, 0, 0);
184 case X86_VENDOR_INTEL:
185 switch (boot_cpu_data.x86) {
187 if (boot_cpu_data.x86_model > 0xd)
190 wrmsr(MSR_P6_EVNTSEL0, 0, 0);
193 if (boot_cpu_data.x86_model > 0x3)
196 wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
197 wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
203 /* tell do_nmi() and others that we're not active any more */
207 static void enable_lapic_nmi_watchdog(void)
209 if (nmi_active < 0) {
210 nmi_watchdog = NMI_LOCAL_APIC;
211 setup_apic_nmi_watchdog();
215 int reserve_lapic_nmi(void)
217 unsigned int old_owner;
219 spin_lock(&lapic_nmi_owner_lock);
220 old_owner = lapic_nmi_owner;
221 lapic_nmi_owner |= LAPIC_NMI_RESERVED;
222 spin_unlock(&lapic_nmi_owner_lock);
223 if (old_owner & LAPIC_NMI_RESERVED)
225 if (old_owner & LAPIC_NMI_WATCHDOG)
226 disable_lapic_nmi_watchdog();
230 void release_lapic_nmi(void)
232 unsigned int new_owner;
234 spin_lock(&lapic_nmi_owner_lock);
235 new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED;
236 lapic_nmi_owner = new_owner;
237 spin_unlock(&lapic_nmi_owner_lock);
238 if (new_owner & LAPIC_NMI_WATCHDOG)
239 enable_lapic_nmi_watchdog();
242 void disable_timer_nmi_watchdog(void)
244 if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0))
247 unset_nmi_callback();
249 nmi_watchdog = NMI_NONE;
252 void enable_timer_nmi_watchdog(void)
254 if (nmi_active < 0) {
255 nmi_watchdog = NMI_IO_APIC;
256 touch_nmi_watchdog();
263 static int nmi_pm_active; /* nmi_active before suspend */
265 static int lapic_nmi_suspend(struct sys_device *dev, u32 state)
267 nmi_pm_active = nmi_active;
268 disable_lapic_nmi_watchdog();
272 static int lapic_nmi_resume(struct sys_device *dev)
274 if (nmi_pm_active > 0)
275 enable_lapic_nmi_watchdog();
280 static struct sysdev_class nmi_sysclass = {
281 set_kset_name("lapic_nmi"),
282 .resume = lapic_nmi_resume,
283 .suspend = lapic_nmi_suspend,
286 static struct sys_device device_lapic_nmi = {
288 .cls = &nmi_sysclass,
291 static int __init init_lapic_nmi_sysfs(void)
295 if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC)
298 error = sysdev_class_register(&nmi_sysclass);
300 error = sysdev_register(&device_lapic_nmi);
303 /* must come after the local APIC's device_initcall() */
304 late_initcall(init_lapic_nmi_sysfs);
306 #endif /* CONFIG_PM */
309 * Activate the NMI watchdog via the local APIC.
310 * Original code written by Keith Owens.
313 static void clear_msr_range(unsigned int base, unsigned int n)
317 for(i = 0; i < n; ++i)
321 static void setup_k7_watchdog(void)
323 unsigned int evntsel;
325 nmi_perfctr_msr = MSR_K7_PERFCTR0;
327 clear_msr_range(MSR_K7_EVNTSEL0, 4);
328 clear_msr_range(MSR_K7_PERFCTR0, 4);
330 evntsel = K7_EVNTSEL_INT
335 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
336 Dprintk("setting K7_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
337 wrmsr(MSR_K7_PERFCTR0, -(cpu_khz/nmi_hz*1000), -1);
338 apic_write(APIC_LVTPC, APIC_DM_NMI);
339 evntsel |= K7_EVNTSEL_ENABLE;
340 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
343 static void setup_p6_watchdog(void)
345 unsigned int evntsel;
347 nmi_perfctr_msr = MSR_P6_PERFCTR0;
349 clear_msr_range(MSR_P6_EVNTSEL0, 2);
350 clear_msr_range(MSR_P6_PERFCTR0, 2);
352 evntsel = P6_EVNTSEL_INT
357 wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
358 Dprintk("setting P6_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
359 wrmsr(MSR_P6_PERFCTR0, -(cpu_khz/nmi_hz*1000), 0);
360 apic_write(APIC_LVTPC, APIC_DM_NMI);
361 evntsel |= P6_EVNTSEL0_ENABLE;
362 wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
365 static int setup_p4_watchdog(void)
367 unsigned int misc_enable, dummy;
369 rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
370 if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
373 nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
374 nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
376 if (smp_num_siblings == 2)
377 nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
380 if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
381 clear_msr_range(0x3F1, 2);
382 /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
383 docs doesn't fully define it, so leave it alone for now. */
384 if (boot_cpu_data.x86_model >= 0x3) {
385 /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
386 clear_msr_range(0x3A0, 26);
387 clear_msr_range(0x3BC, 3);
389 clear_msr_range(0x3A0, 31);
391 clear_msr_range(0x3C0, 6);
392 clear_msr_range(0x3C8, 6);
393 clear_msr_range(0x3E0, 2);
394 clear_msr_range(MSR_P4_CCCR0, 18);
395 clear_msr_range(MSR_P4_PERFCTR0, 18);
397 wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
398 wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
399 Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000));
400 wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1);
401 apic_write(APIC_LVTPC, APIC_DM_NMI);
402 wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
406 void setup_apic_nmi_watchdog (void)
408 switch (boot_cpu_data.x86_vendor) {
410 if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
414 case X86_VENDOR_INTEL:
415 switch (boot_cpu_data.x86) {
417 if (boot_cpu_data.x86_model > 0xd)
423 if (boot_cpu_data.x86_model > 0x3)
426 if (!setup_p4_watchdog())
436 lapic_nmi_owner = LAPIC_NMI_WATCHDOG;
441 * the best way to detect whether a CPU has a 'hard lockup' problem
442 * is to check it's local APIC timer IRQ counts. If they are not
443 * changing then that CPU has some problem.
445 * as these watchdog NMI IRQs are generated on every CPU, we only
446 * have to check the current processor.
448 * since NMIs don't listen to _any_ locks, we have to be extremely
449 * careful not to rely on unsafe variables. The printk might lock
450 * up though, so we have to break up any console locks first ...
451 * [when there will be more tty-related locks, break them up
456 last_irq_sums [NR_CPUS],
457 alert_counter [NR_CPUS];
459 void touch_nmi_watchdog (void)
464 * Just reset the alert counters, (other CPUs might be
465 * spinning on locks we hold):
467 for (i = 0; i < NR_CPUS; i++)
468 alert_counter[i] = 0;
471 extern void die_nmi(struct pt_regs *, const char *msg);
473 void nmi_watchdog_tick (struct pt_regs * regs)
477 * Since current_thread_info()-> is always on the stack, and we
478 * always switch the stack NMI-atomically, it's safe to use
479 * smp_processor_id().
481 int sum, cpu = smp_processor_id();
483 sum = irq_stat[cpu].apic_timer_irqs;
485 if (last_irq_sums[cpu] == sum) {
487 * Ayiee, looks like this CPU is stuck ...
488 * wait a few IRQs (5 seconds) before doing the oops ...
490 alert_counter[cpu]++;
491 if (alert_counter[cpu] == 30*nmi_hz)
492 die_nmi(regs, "NMI Watchdog detected LOCKUP");
494 last_irq_sums[cpu] = sum;
495 alert_counter[cpu] = 0;
497 if (nmi_perfctr_msr) {
498 if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
501 * - An overflown perfctr will assert its interrupt
502 * until the OVF flag in its CCCR is cleared.
503 * - LVTPC is masked on interrupt and must be
504 * unmasked by the LVTPC handler.
506 wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
507 apic_write(APIC_LVTPC, APIC_DM_NMI);
509 else if (nmi_perfctr_msr == MSR_P6_PERFCTR0) {
510 /* Only P6 based Pentium M need to re-unmask
511 * the apic vector but it doesn't hurt
512 * other P6 variant */
513 apic_write(APIC_LVTPC, APIC_DM_NMI);
515 wrmsr(nmi_perfctr_msr, -(cpu_khz/nmi_hz*1000), -1);
521 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
523 unsigned char reason = get_nmi_reason();
526 if (!(reason & 0xc0)) {
527 sprintf(buf, "NMI received for unknown reason %02x\n", reason);
534 * proc handler for /proc/sys/kernel/unknown_nmi_panic
536 int proc_unknown_nmi_panic(ctl_table *table, int write, struct file *file,
537 void __user *buffer, size_t *length, loff_t *ppos)
541 old_state = unknown_nmi_panic;
542 proc_dointvec(table, write, file, buffer, length, ppos);
543 if (!!old_state == !!unknown_nmi_panic)
546 if (unknown_nmi_panic) {
547 if (reserve_lapic_nmi() < 0) {
548 unknown_nmi_panic = 0;
551 set_nmi_callback(unknown_nmi_panic_callback);
555 unset_nmi_callback();
562 EXPORT_SYMBOL(nmi_active);
563 EXPORT_SYMBOL(nmi_watchdog);
564 EXPORT_SYMBOL(reserve_lapic_nmi);
565 EXPORT_SYMBOL(release_lapic_nmi);
566 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
567 EXPORT_SYMBOL(enable_timer_nmi_watchdog);