2 * linux/arch/i386/nmi.c
4 * NMI watchdog support on APIC systems
6 * Started by Ingo Molnar <mingo@redhat.com>
9 * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog.
10 * Mikael Pettersson : Power Management for local APIC NMI watchdog.
11 * Mikael Pettersson : Pentium 4 support for local APIC NMI watchdog.
13 * Mikael Pettersson : PM converted to driver model. Disable/enable API.
16 #include <linux/config.h>
18 #include <linux/irq.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/smp_lock.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/module.h>
26 #include <linux/nmi.h>
27 #include <linux/sysdev.h>
31 #include <asm/mpspec.h>
34 unsigned int nmi_watchdog = NMI_NONE;
35 static unsigned int nmi_hz = HZ;
36 static unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */
37 static unsigned int nmi_p4_cccr_val;
38 extern void show_registers(struct pt_regs *regs);
41 * lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
42 * - it may be reserved by some other driver, or not
43 * - when not reserved by some other driver, it may be used for
44 * the NMI watchdog, or not
46 * This is maintained separately from nmi_active because the NMI
47 * watchdog may also be driven from the I/O APIC timer.
49 static spinlock_t lapic_nmi_owner_lock = SPIN_LOCK_UNLOCKED;
50 static unsigned int lapic_nmi_owner;
51 #define LAPIC_NMI_WATCHDOG (1<<0)
52 #define LAPIC_NMI_RESERVED (1<<1)
55 * +1: the lapic NMI watchdog is active, but can be disabled
56 * 0: the lapic NMI watchdog has not been set up, and cannot
58 * -1: the lapic NMI watchdog is disabled, but can be enabled
62 #define K7_EVNTSEL_ENABLE (1 << 22)
63 #define K7_EVNTSEL_INT (1 << 20)
64 #define K7_EVNTSEL_OS (1 << 17)
65 #define K7_EVNTSEL_USR (1 << 16)
66 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
67 #define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
69 #define P6_EVNTSEL0_ENABLE (1 << 22)
70 #define P6_EVNTSEL_INT (1 << 20)
71 #define P6_EVNTSEL_OS (1 << 17)
72 #define P6_EVNTSEL_USR (1 << 16)
73 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED 0x79
74 #define P6_NMI_EVENT P6_EVENT_CPU_CLOCKS_NOT_HALTED
76 #define MSR_P4_MISC_ENABLE 0x1A0
77 #define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
78 #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
79 #define MSR_P4_PERFCTR0 0x300
80 #define MSR_P4_CCCR0 0x360
81 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
82 #define P4_ESCR_OS (1<<3)
83 #define P4_ESCR_USR (1<<2)
84 #define P4_CCCR_OVF_PMI0 (1<<26)
85 #define P4_CCCR_OVF_PMI1 (1<<27)
86 #define P4_CCCR_THRESHOLD(N) ((N)<<20)
87 #define P4_CCCR_COMPLEMENT (1<<19)
88 #define P4_CCCR_COMPARE (1<<18)
89 #define P4_CCCR_REQUIRED (3<<16)
90 #define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
91 #define P4_CCCR_ENABLE (1<<12)
92 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
93 CRU_ESCR0 (with any non-null event selector) through a complemented
94 max threshold. [IA32-Vol3, Section 14.9.9] */
95 #define MSR_P4_IQ_COUNTER0 0x30C
96 #define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
97 #define P4_NMI_IQ_CCCR0 \
98 (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \
99 P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
101 int __init check_nmi_watchdog (void)
103 unsigned int prev_nmi_count[NR_CPUS];
106 printk(KERN_INFO "testing NMI watchdog ... ");
108 for (cpu = 0; cpu < NR_CPUS; cpu++)
109 prev_nmi_count[cpu] = irq_stat[cpu].__nmi_count;
111 mdelay((10*1000)/nmi_hz); // wait 10 ticks
113 /* FIXME: Only boot CPU is online at this stage. Check CPUs
115 for (cpu = 0; cpu < NR_CPUS; cpu++) {
116 if (!cpu_online(cpu))
118 if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
119 printk("CPU#%d: NMI appears to be stuck!\n", cpu);
121 lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
127 /* now that we know it works we can reduce NMI frequency to
128 something more reasonable; makes a difference in some configs */
129 if (nmi_watchdog == NMI_LOCAL_APIC)
135 static int __init setup_nmi_watchdog(char *str)
139 get_option(&str, &nmi);
141 if (nmi >= NMI_INVALID)
146 * If any other x86 CPU has a local APIC, then
147 * please test the NMI stuff there and send me the
148 * missing bits. Right now Intel P6/P4 and AMD K7 only.
150 if ((nmi == NMI_LOCAL_APIC) &&
151 (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
152 (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
154 if ((nmi == NMI_LOCAL_APIC) &&
155 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
156 (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
159 * We can enable the IO-APIC watchdog
162 if (nmi == NMI_IO_APIC) {
169 __setup("nmi_watchdog=", setup_nmi_watchdog);
171 static void disable_lapic_nmi_watchdog(void)
175 switch (boot_cpu_data.x86_vendor) {
177 wrmsr(MSR_K7_EVNTSEL0, 0, 0);
179 case X86_VENDOR_INTEL:
180 switch (boot_cpu_data.x86) {
182 if (boot_cpu_data.x86_model > 0xd)
185 wrmsr(MSR_P6_EVNTSEL0, 0, 0);
188 if (boot_cpu_data.x86_model > 0x3)
191 wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
192 wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
198 /* tell do_nmi() and others that we're not active any more */
202 static void enable_lapic_nmi_watchdog(void)
204 if (nmi_active < 0) {
205 nmi_watchdog = NMI_LOCAL_APIC;
206 setup_apic_nmi_watchdog();
210 int reserve_lapic_nmi(void)
212 unsigned int old_owner;
214 spin_lock(&lapic_nmi_owner_lock);
215 old_owner = lapic_nmi_owner;
216 lapic_nmi_owner |= LAPIC_NMI_RESERVED;
217 spin_unlock(&lapic_nmi_owner_lock);
218 if (old_owner & LAPIC_NMI_RESERVED)
220 if (old_owner & LAPIC_NMI_WATCHDOG)
221 disable_lapic_nmi_watchdog();
225 void release_lapic_nmi(void)
227 unsigned int new_owner;
229 spin_lock(&lapic_nmi_owner_lock);
230 new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED;
231 lapic_nmi_owner = new_owner;
232 spin_unlock(&lapic_nmi_owner_lock);
233 if (new_owner & LAPIC_NMI_WATCHDOG)
234 enable_lapic_nmi_watchdog();
237 void disable_timer_nmi_watchdog(void)
239 if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0))
242 unset_nmi_callback();
244 nmi_watchdog = NMI_NONE;
247 void enable_timer_nmi_watchdog(void)
249 if (nmi_active < 0) {
250 nmi_watchdog = NMI_IO_APIC;
251 touch_nmi_watchdog();
258 static int nmi_pm_active; /* nmi_active before suspend */
260 static int lapic_nmi_suspend(struct sys_device *dev, u32 state)
262 nmi_pm_active = nmi_active;
263 disable_lapic_nmi_watchdog();
267 static int lapic_nmi_resume(struct sys_device *dev)
269 if (nmi_pm_active > 0)
270 enable_lapic_nmi_watchdog();
275 static struct sysdev_class nmi_sysclass = {
276 set_kset_name("lapic_nmi"),
277 .resume = lapic_nmi_resume,
278 .suspend = lapic_nmi_suspend,
281 static struct sys_device device_lapic_nmi = {
283 .cls = &nmi_sysclass,
286 static int __init init_lapic_nmi_sysfs(void)
290 if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC)
293 error = sysdev_class_register(&nmi_sysclass);
295 error = sysdev_register(&device_lapic_nmi);
298 /* must come after the local APIC's device_initcall() */
299 late_initcall(init_lapic_nmi_sysfs);
301 #endif /* CONFIG_PM */
304 * Activate the NMI watchdog via the local APIC.
305 * Original code written by Keith Owens.
308 static void clear_msr_range(unsigned int base, unsigned int n)
312 for(i = 0; i < n; ++i)
316 static void setup_k7_watchdog(void)
318 unsigned int evntsel;
320 nmi_perfctr_msr = MSR_K7_PERFCTR0;
322 clear_msr_range(MSR_K7_EVNTSEL0, 4);
323 clear_msr_range(MSR_K7_PERFCTR0, 4);
325 evntsel = K7_EVNTSEL_INT
330 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
331 Dprintk("setting K7_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
332 wrmsr(MSR_K7_PERFCTR0, -(cpu_khz/nmi_hz*1000), -1);
333 apic_write(APIC_LVTPC, APIC_DM_NMI);
334 evntsel |= K7_EVNTSEL_ENABLE;
335 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
338 static void setup_p6_watchdog(void)
340 unsigned int evntsel;
342 nmi_perfctr_msr = MSR_P6_PERFCTR0;
344 clear_msr_range(MSR_P6_EVNTSEL0, 2);
345 clear_msr_range(MSR_P6_PERFCTR0, 2);
347 evntsel = P6_EVNTSEL_INT
352 wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
353 Dprintk("setting P6_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
354 wrmsr(MSR_P6_PERFCTR0, -(cpu_khz/nmi_hz*1000), 0);
355 apic_write(APIC_LVTPC, APIC_DM_NMI);
356 evntsel |= P6_EVNTSEL0_ENABLE;
357 wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
360 static int setup_p4_watchdog(void)
362 unsigned int misc_enable, dummy;
364 rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
365 if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
368 nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
369 nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
371 if (smp_num_siblings == 2)
372 nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
375 if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
376 clear_msr_range(0x3F1, 2);
377 /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
378 docs doesn't fully define it, so leave it alone for now. */
379 clear_msr_range(0x3A0, 31);
380 clear_msr_range(0x3C0, 6);
381 clear_msr_range(0x3C8, 6);
382 clear_msr_range(0x3E0, 2);
383 clear_msr_range(MSR_P4_CCCR0, 18);
384 clear_msr_range(MSR_P4_PERFCTR0, 18);
386 wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
387 wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
388 Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000));
389 wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1);
390 apic_write(APIC_LVTPC, APIC_DM_NMI);
391 wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
395 void setup_apic_nmi_watchdog (void)
397 switch (boot_cpu_data.x86_vendor) {
399 if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
403 case X86_VENDOR_INTEL:
404 switch (boot_cpu_data.x86) {
406 if (boot_cpu_data.x86_model > 0xd)
412 if (boot_cpu_data.x86_model > 0x3)
415 if (!setup_p4_watchdog())
425 lapic_nmi_owner = LAPIC_NMI_WATCHDOG;
429 static spinlock_t nmi_print_lock = SPIN_LOCK_UNLOCKED;
432 * the best way to detect whether a CPU has a 'hard lockup' problem
433 * is to check it's local APIC timer IRQ counts. If they are not
434 * changing then that CPU has some problem.
436 * as these watchdog NMI IRQs are generated on every CPU, we only
437 * have to check the current processor.
439 * since NMIs don't listen to _any_ locks, we have to be extremely
440 * careful not to rely on unsafe variables. The printk might lock
441 * up though, so we have to break up any console locks first ...
442 * [when there will be more tty-related locks, break them up
447 last_irq_sums [NR_CPUS],
448 alert_counter [NR_CPUS];
450 void touch_nmi_watchdog (void)
455 * Just reset the alert counters, (other CPUs might be
456 * spinning on locks we hold):
458 for (i = 0; i < NR_CPUS; i++)
459 alert_counter[i] = 0;
462 void nmi_watchdog_tick (struct pt_regs * regs)
466 * Since current_thread_info()-> is always on the stack, and we
467 * always switch the stack NMI-atomically, it's safe to use
468 * smp_processor_id().
470 int sum, cpu = smp_processor_id();
472 sum = irq_stat[cpu].apic_timer_irqs;
474 if (last_irq_sums[cpu] == sum) {
476 * Ayiee, looks like this CPU is stuck ...
477 * wait a few IRQs (5 seconds) before doing the oops ...
479 alert_counter[cpu]++;
480 if (alert_counter[cpu] == 60*nmi_hz) {
481 spin_lock(&nmi_print_lock);
483 * We are in trouble anyway, lets at least try
484 * to get a message out.
487 printk("NMI Watchdog detected LOCKUP on CPU%d, eip %08lx, registers:\n", cpu, regs->eip);
488 show_registers(regs);
489 printk("console shuts up ...\n");
491 spin_unlock(&nmi_print_lock);
496 last_irq_sums[cpu] = sum;
497 alert_counter[cpu] = 0;
499 if (nmi_perfctr_msr) {
500 if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
503 * - An overflown perfctr will assert its interrupt
504 * until the OVF flag in its CCCR is cleared.
505 * - LVTPC is masked on interrupt and must be
506 * unmasked by the LVTPC handler.
508 wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
509 apic_write(APIC_LVTPC, APIC_DM_NMI);
511 else if (nmi_perfctr_msr == MSR_P6_PERFCTR0) {
512 /* Only P6 based Pentium M need to re-unmask
513 * the apic vector but it doesn't hurt
514 * other P6 variant */
515 apic_write(APIC_LVTPC, APIC_DM_NMI);
517 wrmsr(nmi_perfctr_msr, -(cpu_khz/nmi_hz*1000), -1);
521 EXPORT_SYMBOL(nmi_active);
522 EXPORT_SYMBOL(nmi_watchdog);
523 EXPORT_SYMBOL(reserve_lapic_nmi);
524 EXPORT_SYMBOL(release_lapic_nmi);
525 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
526 EXPORT_SYMBOL(enable_timer_nmi_watchdog);