2 * linux/arch/i386/nmi.c
4 * NMI watchdog support on APIC systems
6 * Started by Ingo Molnar <mingo@redhat.com>
9 * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog.
10 * Mikael Pettersson : Power Management for local APIC NMI watchdog.
11 * Mikael Pettersson : Pentium 4 support for local APIC NMI watchdog.
13 * Mikael Pettersson : PM converted to driver model. Disable/enable API.
16 #include <linux/config.h>
18 #include <linux/irq.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/smp_lock.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/module.h>
26 #include <linux/nmi.h>
27 #include <linux/sysdev.h>
28 #include <linux/dump.h>
29 #include <linux/sysctl.h>
33 #include <asm/mpspec.h>
36 #include "mach_traps.h"
38 unsigned int nmi_watchdog = NMI_NONE;
39 extern int unknown_nmi_panic;
40 static unsigned int nmi_hz = HZ;
41 static unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */
42 static unsigned int nmi_p4_cccr_val;
43 extern void show_registers(struct pt_regs *regs);
46 * lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
47 * - it may be reserved by some other driver, or not
48 * - when not reserved by some other driver, it may be used for
49 * the NMI watchdog, or not
51 * This is maintained separately from nmi_active because the NMI
52 * watchdog may also be driven from the I/O APIC timer.
54 static DEFINE_SPINLOCK(lapic_nmi_owner_lock);
55 static unsigned int lapic_nmi_owner;
56 #define LAPIC_NMI_WATCHDOG (1<<0)
57 #define LAPIC_NMI_RESERVED (1<<1)
60 * +1: the lapic NMI watchdog is active, but can be disabled
61 * 0: the lapic NMI watchdog has not been set up, and cannot
63 * -1: the lapic NMI watchdog is disabled, but can be enabled
67 #define K7_EVNTSEL_ENABLE (1 << 22)
68 #define K7_EVNTSEL_INT (1 << 20)
69 #define K7_EVNTSEL_OS (1 << 17)
70 #define K7_EVNTSEL_USR (1 << 16)
71 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
72 #define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
74 #define P6_EVNTSEL0_ENABLE (1 << 22)
75 #define P6_EVNTSEL_INT (1 << 20)
76 #define P6_EVNTSEL_OS (1 << 17)
77 #define P6_EVNTSEL_USR (1 << 16)
78 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED 0x79
79 #define P6_NMI_EVENT P6_EVENT_CPU_CLOCKS_NOT_HALTED
81 #define MSR_P4_MISC_ENABLE 0x1A0
82 #define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
83 #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
84 #define MSR_P4_PERFCTR0 0x300
85 #define MSR_P4_CCCR0 0x360
86 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
87 #define P4_ESCR_OS (1<<3)
88 #define P4_ESCR_USR (1<<2)
89 #define P4_CCCR_OVF_PMI0 (1<<26)
90 #define P4_CCCR_OVF_PMI1 (1<<27)
91 #define P4_CCCR_THRESHOLD(N) ((N)<<20)
92 #define P4_CCCR_COMPLEMENT (1<<19)
93 #define P4_CCCR_COMPARE (1<<18)
94 #define P4_CCCR_REQUIRED (3<<16)
95 #define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
96 #define P4_CCCR_ENABLE (1<<12)
97 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
98 CRU_ESCR0 (with any non-null event selector) through a complemented
99 max threshold. [IA32-Vol3, Section 14.9.9] */
100 #define MSR_P4_IQ_COUNTER0 0x30C
101 #define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
102 #define P4_NMI_IQ_CCCR0 \
103 (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \
104 P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
106 static int __init check_nmi_watchdog(void)
108 unsigned int prev_nmi_count[NR_CPUS];
111 if (nmi_watchdog == NMI_NONE)
114 printk(KERN_INFO "Testing NMI watchdog ... ");
116 for (cpu = 0; cpu < NR_CPUS; cpu++)
117 prev_nmi_count[cpu] = per_cpu(irq_stat, cpu).__nmi_count;
119 mdelay((10*1000)/nmi_hz); // wait 10 ticks
121 for (cpu = 0; cpu < NR_CPUS; cpu++) {
123 /* Check cpu_callin_map here because that is set
124 after the timer is started. */
125 if (!cpu_isset(cpu, cpu_callin_map))
128 if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
129 printk("CPU#%d: NMI appears to be stuck!\n", cpu);
131 lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
137 /* now that we know it works we can reduce NMI frequency to
138 something more reasonable; makes a difference in some configs */
139 if (nmi_watchdog == NMI_LOCAL_APIC)
144 /* This needs to happen later in boot so counters are working */
145 late_initcall(check_nmi_watchdog);
147 static int __init setup_nmi_watchdog(char *str)
151 get_option(&str, &nmi);
153 if (nmi >= NMI_INVALID)
158 * If any other x86 CPU has a local APIC, then
159 * please test the NMI stuff there and send me the
160 * missing bits. Right now Intel P6/P4 and AMD K7 only.
162 if ((nmi == NMI_LOCAL_APIC) &&
163 (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
164 (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
166 if ((nmi == NMI_LOCAL_APIC) &&
167 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
168 (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
171 * We can enable the IO-APIC watchdog
174 if (nmi == NMI_IO_APIC) {
181 __setup("nmi_watchdog=", setup_nmi_watchdog);
183 static void disable_lapic_nmi_watchdog(void)
187 switch (boot_cpu_data.x86_vendor) {
189 wrmsr(MSR_K7_EVNTSEL0, 0, 0);
191 case X86_VENDOR_INTEL:
192 switch (boot_cpu_data.x86) {
194 if (boot_cpu_data.x86_model > 0xd)
197 wrmsr(MSR_P6_EVNTSEL0, 0, 0);
200 if (boot_cpu_data.x86_model > 0x3)
203 wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
204 wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
210 /* tell do_nmi() and others that we're not active any more */
214 static void enable_lapic_nmi_watchdog(void)
216 if (nmi_active < 0) {
217 nmi_watchdog = NMI_LOCAL_APIC;
218 setup_apic_nmi_watchdog();
222 int reserve_lapic_nmi(void)
224 unsigned int old_owner;
226 spin_lock(&lapic_nmi_owner_lock);
227 old_owner = lapic_nmi_owner;
228 lapic_nmi_owner |= LAPIC_NMI_RESERVED;
229 spin_unlock(&lapic_nmi_owner_lock);
230 if (old_owner & LAPIC_NMI_RESERVED)
232 if (old_owner & LAPIC_NMI_WATCHDOG)
233 disable_lapic_nmi_watchdog();
237 void release_lapic_nmi(void)
239 unsigned int new_owner;
241 spin_lock(&lapic_nmi_owner_lock);
242 new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED;
243 lapic_nmi_owner = new_owner;
244 spin_unlock(&lapic_nmi_owner_lock);
245 if (new_owner & LAPIC_NMI_WATCHDOG)
246 enable_lapic_nmi_watchdog();
249 void disable_timer_nmi_watchdog(void)
251 if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0))
254 unset_nmi_callback();
256 nmi_watchdog = NMI_NONE;
259 void enable_timer_nmi_watchdog(void)
261 if (nmi_active < 0) {
262 nmi_watchdog = NMI_IO_APIC;
263 touch_nmi_watchdog();
270 static int nmi_pm_active; /* nmi_active before suspend */
272 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
274 nmi_pm_active = nmi_active;
275 disable_lapic_nmi_watchdog();
279 static int lapic_nmi_resume(struct sys_device *dev)
281 if (nmi_pm_active > 0)
282 enable_lapic_nmi_watchdog();
287 static struct sysdev_class nmi_sysclass = {
288 set_kset_name("lapic_nmi"),
289 .resume = lapic_nmi_resume,
290 .suspend = lapic_nmi_suspend,
293 static struct sys_device device_lapic_nmi = {
295 .cls = &nmi_sysclass,
298 static int __init init_lapic_nmi_sysfs(void)
302 if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC)
305 error = sysdev_class_register(&nmi_sysclass);
307 error = sysdev_register(&device_lapic_nmi);
310 /* must come after the local APIC's device_initcall() */
311 late_initcall(init_lapic_nmi_sysfs);
313 #endif /* CONFIG_PM */
316 * Activate the NMI watchdog via the local APIC.
317 * Original code written by Keith Owens.
320 static void clear_msr_range(unsigned int base, unsigned int n)
324 for(i = 0; i < n; ++i)
328 static void setup_k7_watchdog(void)
330 unsigned int evntsel;
332 nmi_perfctr_msr = MSR_K7_PERFCTR0;
334 clear_msr_range(MSR_K7_EVNTSEL0, 4);
335 clear_msr_range(MSR_K7_PERFCTR0, 4);
337 evntsel = K7_EVNTSEL_INT
342 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
343 Dprintk("setting K7_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
344 wrmsr(MSR_K7_PERFCTR0, -(cpu_khz/nmi_hz*1000), -1);
345 apic_write(APIC_LVTPC, APIC_DM_NMI);
346 evntsel |= K7_EVNTSEL_ENABLE;
347 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
350 static void setup_p6_watchdog(void)
352 unsigned int evntsel;
354 nmi_perfctr_msr = MSR_P6_PERFCTR0;
356 clear_msr_range(MSR_P6_EVNTSEL0, 2);
357 clear_msr_range(MSR_P6_PERFCTR0, 2);
359 evntsel = P6_EVNTSEL_INT
364 wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
365 Dprintk("setting P6_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
366 wrmsr(MSR_P6_PERFCTR0, -(cpu_khz/nmi_hz*1000), 0);
367 apic_write(APIC_LVTPC, APIC_DM_NMI);
368 evntsel |= P6_EVNTSEL0_ENABLE;
369 wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
372 static int setup_p4_watchdog(void)
374 unsigned int misc_enable, dummy;
376 rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
377 if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
380 nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
381 nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
383 if (smp_num_siblings == 2)
384 nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
387 if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
388 clear_msr_range(0x3F1, 2);
389 /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
390 docs doesn't fully define it, so leave it alone for now. */
391 if (boot_cpu_data.x86_model >= 0x3) {
392 /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
393 clear_msr_range(0x3A0, 26);
394 clear_msr_range(0x3BC, 3);
396 clear_msr_range(0x3A0, 31);
398 clear_msr_range(0x3C0, 6);
399 clear_msr_range(0x3C8, 6);
400 clear_msr_range(0x3E0, 2);
401 clear_msr_range(MSR_P4_CCCR0, 18);
402 clear_msr_range(MSR_P4_PERFCTR0, 18);
404 wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
405 wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
406 Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000));
407 wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1);
408 apic_write(APIC_LVTPC, APIC_DM_NMI);
409 wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
413 void setup_apic_nmi_watchdog (void)
415 switch (boot_cpu_data.x86_vendor) {
417 if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
421 case X86_VENDOR_INTEL:
422 switch (boot_cpu_data.x86) {
424 if (boot_cpu_data.x86_model > 0xd)
430 if (boot_cpu_data.x86_model > 0x3)
433 if (!setup_p4_watchdog())
443 lapic_nmi_owner = LAPIC_NMI_WATCHDOG;
448 * the best way to detect whether a CPU has a 'hard lockup' problem
449 * is to check it's local APIC timer IRQ counts. If they are not
450 * changing then that CPU has some problem.
452 * as these watchdog NMI IRQs are generated on every CPU, we only
453 * have to check the current processor.
455 * since NMIs don't listen to _any_ locks, we have to be extremely
456 * careful not to rely on unsafe variables. The printk might lock
457 * up though, so we have to break up any console locks first ...
458 * [when there will be more tty-related locks, break them up
463 last_irq_sums [NR_CPUS],
464 alert_counter [NR_CPUS];
466 void touch_nmi_watchdog (void)
471 * Just reset the alert counters, (other CPUs might be
472 * spinning on locks we hold):
474 for (i = 0; i < NR_CPUS; i++)
475 alert_counter[i] = 0;
478 extern void die_nmi(struct pt_regs *, const char *msg);
480 void nmi_watchdog_tick (struct pt_regs * regs)
484 * Since current_thread_info()-> is always on the stack, and we
485 * always switch the stack NMI-atomically, it's safe to use
486 * smp_processor_id().
488 int sum, cpu = smp_processor_id();
490 sum = per_cpu(irq_stat, cpu).apic_timer_irqs;
492 if (last_irq_sums[cpu] == sum) {
494 * Ayiee, looks like this CPU is stuck ...
495 * wait a few IRQs (5 seconds) before doing the oops ...
497 alert_counter[cpu]++;
498 if (alert_counter[cpu] == 30*nmi_hz)
499 die_nmi(regs, "NMI Watchdog detected LOCKUP");
501 last_irq_sums[cpu] = sum;
502 alert_counter[cpu] = 0;
504 if (nmi_perfctr_msr) {
505 if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
508 * - An overflown perfctr will assert its interrupt
509 * until the OVF flag in its CCCR is cleared.
510 * - LVTPC is masked on interrupt and must be
511 * unmasked by the LVTPC handler.
513 wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
514 apic_write(APIC_LVTPC, APIC_DM_NMI);
516 else if (nmi_perfctr_msr == MSR_P6_PERFCTR0) {
517 /* Only P6 based Pentium M need to re-unmask
518 * the apic vector but it doesn't hurt
519 * other P6 variant */
520 apic_write(APIC_LVTPC, APIC_DM_NMI);
522 wrmsr(nmi_perfctr_msr, -(cpu_khz/nmi_hz*1000), -1);
528 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
530 unsigned char reason = get_nmi_reason();
533 if (!(reason & 0xc0)) {
534 sprintf(buf, "NMI received for unknown reason %02x\n", reason);
541 * proc handler for /proc/sys/kernel/unknown_nmi_panic
543 int proc_unknown_nmi_panic(ctl_table *table, int write, struct file *file,
544 void __user *buffer, size_t *length, loff_t *ppos)
548 old_state = unknown_nmi_panic;
549 proc_dointvec(table, write, file, buffer, length, ppos);
550 if (!!old_state == !!unknown_nmi_panic)
553 if (unknown_nmi_panic) {
554 if (reserve_lapic_nmi() < 0) {
555 unknown_nmi_panic = 0;
558 set_nmi_callback(unknown_nmi_panic_callback);
562 unset_nmi_callback();
569 EXPORT_SYMBOL(nmi_active);
570 EXPORT_SYMBOL(nmi_watchdog);
571 EXPORT_SYMBOL(reserve_lapic_nmi);
572 EXPORT_SYMBOL(release_lapic_nmi);
573 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
574 EXPORT_SYMBOL(enable_timer_nmi_watchdog);
575 EXPORT_SYMBOL_GPL(touch_nmi_watchdog);