2 * Intel SMP support routines.
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
7 * This code is released under the GNU General Public License version 2 or
11 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/spinlock.h>
16 #include <linux/smp_lock.h>
17 #include <linux/kernel_stat.h>
18 #include <linux/mc146818rtc.h>
19 #include <linux/cache.h>
20 #include <linux/interrupt.h>
21 #include <linux/cpu.h>
22 #include <linux/module.h>
25 #include <asm/tlbflush.h>
28 #include <mach_apic.h>
30 #include <xen/evtchn.h>
33 * Some notes on x86 processor bugs affecting SMP operation:
35 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
36 * The Linux implications for SMP are handled as follows:
38 * Pentium III / [Xeon]
39 * None of the E1AP-E3AP errata are visible to the user.
46 * None of the A1AP-A3AP errata are visible to the user.
53 * None of 1AP-9AP errata are visible to the normal user,
54 * except occasional delivery of 'spurious interrupt' as trap #15.
55 * This is very rare and a non-problem.
57 * 1AP. Linux maps APIC as non-cacheable
58 * 2AP. worked around in hardware
59 * 3AP. fixed in C0 and above steppings microcode update.
60 * Linux does not use excessive STARTUP_IPIs.
61 * 4AP. worked around in hardware
62 * 5AP. symmetric IO mode (normal Linux operation) not affected.
63 * 'noapic' mode has vector 0xf filled out properly.
64 * 6AP. 'noapic' mode might be affected - fixed in later steppings
65 * 7AP. We do not assume writes to the LVT deassering IRQs
66 * 8AP. We do not enable low power mode (deep sleep) during MP bootup
67 * 9AP. We do not use mixed mode
70 * There is a marginal case where REP MOVS on 100MHz SMP
71 * machines with B stepping processors can fail. XXX should provide
72 * an L1cache=Writethrough or L1cache=off option.
74 * B stepping CPUs may hang. There are hardware work arounds
75 * for this. We warn about it in case your board doesn't have the work
76 * arounds. Basically thats so I can tell anyone with a B stepping
77 * CPU and SMP problems "tough".
79 * Specific items [From Pentium Processor Specification Update]
81 * 1AP. Linux doesn't use remote read
82 * 2AP. Linux doesn't trust APIC errors
83 * 3AP. We work around this
84 * 4AP. Linux never generated 3 interrupts of the same priority
85 * to cause a lost local interrupt.
86 * 5AP. Remote read is never used
87 * 6AP. not affected - worked around in hardware
88 * 7AP. not affected - worked around in hardware
89 * 8AP. worked around in hardware - we get explicit CS errors if not
90 * 9AP. only 'noapic' mode affected. Might generate spurious
91 * interrupts, we log only the first one and count the
93 * 10AP. not affected - worked around in hardware
94 * 11AP. Linux reads the APIC between writes to avoid this, as per
95 * the documentation. Make sure you preserve this as it affects
96 * the C stepping chips too.
97 * 12AP. not affected - worked around in hardware
98 * 13AP. not affected - worked around in hardware
99 * 14AP. we always deassert INIT during bootup
100 * 15AP. not affected - worked around in hardware
101 * 16AP. not affected - worked around in hardware
102 * 17AP. not affected - worked around in hardware
103 * 18AP. not affected - worked around in hardware
104 * 19AP. not affected - worked around in BIOS
106 * If this sounds worrying believe me these bugs are either ___RARE___,
107 * or are signal timing bugs worked around in hardware and there's
108 * about nothing of note with C stepping upwards.
111 DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0, };
114 * the following functions deal with sending IPIs between CPUs.
116 * We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
119 static inline int __prepare_ICR (unsigned int shortcut, int vector)
121 unsigned int icr = shortcut | APIC_DEST_LOGICAL;
125 icr |= APIC_DM_FIXED | vector;
134 static inline int __prepare_ICR2 (unsigned int mask)
136 return SET_APIC_DEST_FIELD(mask);
139 DECLARE_PER_CPU(int, ipi_to_irq[NR_IPIS]);
141 static inline void __send_IPI_one(unsigned int cpu, int vector)
143 int irq = per_cpu(ipi_to_irq, cpu)[vector];
145 notify_remote_via_irq(irq);
148 void __send_IPI_shortcut(unsigned int shortcut, int vector)
154 __send_IPI_one(smp_processor_id(), vector);
156 case APIC_DEST_ALLBUT:
157 for (cpu = 0; cpu < NR_CPUS; ++cpu) {
158 if (cpu == smp_processor_id())
160 if (cpu_isset(cpu, cpu_online_map)) {
161 __send_IPI_one(cpu, vector);
166 printk("XXXXXX __send_IPI_shortcut %08x vector %d\n", shortcut,
172 void fastcall send_IPI_self(int vector)
174 __send_IPI_shortcut(APIC_DEST_SELF, vector);
178 * This is only used on smaller machines.
180 void send_IPI_mask_bitmask(cpumask_t mask, int vector)
185 local_irq_save(flags);
186 WARN_ON(cpus_addr(mask)[0] & ~cpus_addr(cpu_online_map)[0]);
188 for (cpu = 0; cpu < NR_CPUS; ++cpu) {
189 if (cpu_isset(cpu, mask)) {
190 __send_IPI_one(cpu, vector);
194 local_irq_restore(flags);
197 void send_IPI_mask_sequence(cpumask_t mask, int vector)
200 send_IPI_mask_bitmask(mask, vector);
203 #include <mach_ipi.h> /* must come after the send_IPI functions above for inlining */
207 * Smarter SMP flushing macros.
208 * c/o Linus Torvalds.
210 * These mean you can really definitely utterly forget about
211 * writing to user space from interrupts. (Its not allowed anyway).
213 * Optimizations Manfred Spraul <manfred@colorfullife.com>
216 static cpumask_t flush_cpumask;
217 static struct mm_struct * flush_mm;
218 static unsigned long flush_va;
219 static DEFINE_SPINLOCK(tlbstate_lock);
220 #define FLUSH_ALL 0xffffffff
223 * We cannot call mmdrop() because we are in interrupt context,
224 * instead update mm->cpu_vm_mask.
226 * We need to reload %cr3 since the page tables may be going
227 * away from under us..
229 static inline void leave_mm (unsigned long cpu)
231 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
233 cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
234 load_cr3(swapper_pg_dir);
239 * The flush IPI assumes that a thread switch happens in this order:
240 * [cpu0: the cpu that switches]
241 * 1) switch_mm() either 1a) or 1b)
242 * 1a) thread switch to a different mm
243 * 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
244 * Stop ipi delivery for the old mm. This is not synchronized with
245 * the other cpus, but smp_invalidate_interrupt ignore flush ipis
246 * for the wrong mm, and in the worst case we perform a superflous
248 * 1a2) set cpu_tlbstate to TLBSTATE_OK
249 * Now the smp_invalidate_interrupt won't call leave_mm if cpu0
250 * was in lazy tlb mode.
251 * 1a3) update cpu_tlbstate[].active_mm
252 * Now cpu0 accepts tlb flushes for the new mm.
253 * 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
254 * Now the other cpus will send tlb flush ipis.
256 * 1b) thread switch without mm change
257 * cpu_tlbstate[].active_mm is correct, cpu0 already handles
259 * 1b1) set cpu_tlbstate to TLBSTATE_OK
260 * 1b2) test_and_set the cpu bit in cpu_vm_mask.
261 * Atomically set the bit [other cpus will start sending flush ipis],
263 * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
264 * 2) switch %%esp, ie current
266 * The interrupt must handle 2 special cases:
267 * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
268 * - the cpu performs speculative tlb reads, i.e. even if the cpu only
269 * runs in kernel space, the cpu could load tlb entries for user space
272 * The good news is that cpu_tlbstate is local to each cpu, no
273 * write/read ordering problems.
279 * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
280 * 2) Leave the mm if we are in the lazy tlb mode.
283 irqreturn_t smp_invalidate_interrupt(int irq, void *dev_id,
284 struct pt_regs *regs)
289 if (current->active_mm)
290 load_user_cs_desc(cpu, current->active_mm);
292 if (!cpu_isset(cpu, flush_cpumask))
295 * This was a BUG() but until someone can quote me the
296 * line from the intel manual that guarantees an IPI to
297 * multiple CPUs is retried _only_ on the erroring CPUs
298 * its staying as a return
303 if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
304 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
305 if (flush_va == FLUSH_ALL)
308 __flush_tlb_one(flush_va);
312 smp_mb__before_clear_bit();
313 cpu_clear(cpu, flush_cpumask);
314 smp_mb__after_clear_bit();
316 put_cpu_no_resched();
321 static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
325 * A couple of (to be removed) sanity checks:
327 * - current CPU must not be in mask
328 * - mask must exist :)
330 BUG_ON(cpus_empty(cpumask));
331 BUG_ON(cpu_isset(smp_processor_id(), cpumask));
334 /* If a CPU which we ran on has gone down, OK. */
335 cpus_and(cpumask, cpumask, cpu_online_map);
336 if (cpus_empty(cpumask))
340 * i'm not happy about this global shared spinlock in the
341 * MM hot path, but we'll see how contended it is.
342 * Temporarily this turns IRQs off, so that lockups are
343 * detected by the NMI watchdog.
345 spin_lock(&tlbstate_lock);
349 #if NR_CPUS <= BITS_PER_LONG
350 atomic_set_mask(cpumask, &flush_cpumask);
354 unsigned long *flush_mask = (unsigned long *)&flush_cpumask;
355 unsigned long *cpu_mask = (unsigned long *)&cpumask;
356 for (k = 0; k < BITS_TO_LONGS(NR_CPUS); ++k)
357 atomic_set_mask(cpu_mask[k], &flush_mask[k]);
361 * We have to send the IPI only to
364 send_IPI_mask(cpumask, INVALIDATE_TLB_VECTOR);
366 while (!cpus_empty(flush_cpumask))
367 /* nothing. lockup detection does not belong here */
372 spin_unlock(&tlbstate_lock);
375 void flush_tlb_current_task(void)
377 struct mm_struct *mm = current->mm;
381 cpu_mask = mm->cpu_vm_mask;
382 cpu_clear(smp_processor_id(), cpu_mask);
385 if (!cpus_empty(cpu_mask))
386 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
390 void flush_tlb_mm (struct mm_struct * mm)
395 cpu_mask = mm->cpu_vm_mask;
396 cpu_clear(smp_processor_id(), cpu_mask);
398 if (current->active_mm == mm) {
402 leave_mm(smp_processor_id());
404 if (!cpus_empty(cpu_mask))
405 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
410 void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
412 struct mm_struct *mm = vma->vm_mm;
416 cpu_mask = mm->cpu_vm_mask;
417 cpu_clear(smp_processor_id(), cpu_mask);
419 if (current->active_mm == mm) {
423 leave_mm(smp_processor_id());
426 if (!cpus_empty(cpu_mask))
427 flush_tlb_others(cpu_mask, mm, va);
431 EXPORT_SYMBOL(flush_tlb_page);
433 static void do_flush_tlb_all(void* info)
435 unsigned long cpu = smp_processor_id();
438 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
442 void flush_tlb_all(void)
444 on_each_cpu(do_flush_tlb_all, NULL, 1, 1);
449 irqreturn_t smp_invalidate_interrupt(int irq, void *dev_id,
450 struct pt_regs *regs)
452 void flush_tlb_current_task(void)
453 { xen_tlb_flush_mask(¤t->mm->cpu_vm_mask); }
454 void flush_tlb_mm(struct mm_struct * mm)
455 { xen_tlb_flush_mask(&mm->cpu_vm_mask); }
456 void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
457 { xen_invlpg_mask(&vma->vm_mm->cpu_vm_mask, va); }
458 EXPORT_SYMBOL(flush_tlb_page);
459 void flush_tlb_all(void)
460 { xen_tlb_flush_all(); }
465 * this function sends a 'reschedule' IPI to another CPU.
466 * it goes straight through and wastes no time serializing
467 * anything. Worst case is that we lose a reschedule ...
469 void smp_send_reschedule(int cpu)
471 WARN_ON(cpu_is_offline(cpu));
472 send_IPI_mask(cpumask_of_cpu(cpu), RESCHEDULE_VECTOR);
476 * Structure and data for smp_call_function(). This is designed to minimise
477 * static memory requirements. It also looks cleaner.
479 static DEFINE_SPINLOCK(call_lock);
481 struct call_data_struct {
482 void (*func) (void *info);
489 void lock_ipi_call_lock(void)
491 spin_lock_irq(&call_lock);
494 void unlock_ipi_call_lock(void)
496 spin_unlock_irq(&call_lock);
499 static struct call_data_struct *call_data;
502 * smp_call_function(): Run a function on all other CPUs.
503 * @func: The function to run. This must be fast and non-blocking.
504 * @info: An arbitrary pointer to pass to the function.
505 * @nonatomic: currently unused.
506 * @wait: If true, wait (atomically) until function has completed on other CPUs.
508 * Returns 0 on success, else a negative status code. Does not return until
509 * remote CPUs are nearly ready to execute <<func>> or are or have executed.
511 * You must not call this function with disabled interrupts or from a
512 * hardware interrupt handler or from a bottom half handler.
514 int smp_call_function (void (*func) (void *info), void *info, int nonatomic,
517 struct call_data_struct data;
520 /* Holding any lock stops cpus from going down. */
521 spin_lock(&call_lock);
522 cpus = num_online_cpus() - 1;
524 spin_unlock(&call_lock);
528 /* Can deadlock when called with interrupts disabled */
529 WARN_ON(irqs_disabled());
533 atomic_set(&data.started, 0);
536 atomic_set(&data.finished, 0);
541 /* Send a message to all other CPUs and wait for them to respond */
542 send_IPI_allbutself(CALL_FUNCTION_VECTOR);
544 /* Wait for response */
545 while (atomic_read(&data.started) != cpus)
549 while (atomic_read(&data.finished) != cpus)
551 spin_unlock(&call_lock);
555 EXPORT_SYMBOL(smp_call_function);
557 static void stop_this_cpu (void * dummy)
562 cpu_clear(smp_processor_id(), cpu_online_map);
565 disable_local_APIC();
567 if (cpu_data[smp_processor_id()].hlt_works_ok)
573 * this function calls the 'stop' function on all other CPUs in the system.
576 void smp_send_stop(void)
578 smp_call_function(stop_this_cpu, NULL, 1, 0);
582 disable_local_APIC();
588 * Reschedule call back. Nothing to do,
589 * all the work is done automatically when
590 * we return from the interrupt.
592 irqreturn_t smp_reschedule_interrupt(int irq, void *dev_id,
593 struct pt_regs *regs)
599 #include <linux/kallsyms.h>
600 irqreturn_t smp_call_function_interrupt(int irq, void *dev_id,
601 struct pt_regs *regs)
603 void (*func) (void *info) = call_data->func;
604 void *info = call_data->info;
605 int wait = call_data->wait;
608 * Notify initiating CPU that I've grabbed the data and am
609 * about to execute the function
612 atomic_inc(&call_data->started);
614 * At this point the info structure may be out of scope unless wait==1
622 atomic_inc(&call_data->finished);