2 * Intel SMP support routines.
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
7 * This code is released under the GNU General Public License version 2 or
11 #include <linux/init.h>
14 #include <linux/irq.h>
15 #include <linux/delay.h>
16 #include <linux/spinlock.h>
17 #include <linux/smp_lock.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/cache.h>
21 #include <linux/interrupt.h>
22 #include <linux/dump.h>
25 #include <asm/tlbflush.h>
26 #include <mach_apic.h>
29 * Some notes on x86 processor bugs affecting SMP operation:
31 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
32 * The Linux implications for SMP are handled as follows:
34 * Pentium III / [Xeon]
35 * None of the E1AP-E3AP errata are visible to the user.
42 * None of the A1AP-A3AP errata are visible to the user.
49 * None of 1AP-9AP errata are visible to the normal user,
50 * except occasional delivery of 'spurious interrupt' as trap #15.
51 * This is very rare and a non-problem.
53 * 1AP. Linux maps APIC as non-cacheable
54 * 2AP. worked around in hardware
55 * 3AP. fixed in C0 and above steppings microcode update.
56 * Linux does not use excessive STARTUP_IPIs.
57 * 4AP. worked around in hardware
58 * 5AP. symmetric IO mode (normal Linux operation) not affected.
59 * 'noapic' mode has vector 0xf filled out properly.
60 * 6AP. 'noapic' mode might be affected - fixed in later steppings
61 * 7AP. We do not assume writes to the LVT deassering IRQs
62 * 8AP. We do not enable low power mode (deep sleep) during MP bootup
63 * 9AP. We do not use mixed mode
66 * There is a marginal case where REP MOVS on 100MHz SMP
67 * machines with B stepping processors can fail. XXX should provide
68 * an L1cache=Writethrough or L1cache=off option.
70 * B stepping CPUs may hang. There are hardware work arounds
71 * for this. We warn about it in case your board doesn't have the work
72 * arounds. Basically thats so I can tell anyone with a B stepping
73 * CPU and SMP problems "tough".
75 * Specific items [From Pentium Processor Specification Update]
77 * 1AP. Linux doesn't use remote read
78 * 2AP. Linux doesn't trust APIC errors
79 * 3AP. We work around this
80 * 4AP. Linux never generated 3 interrupts of the same priority
81 * to cause a lost local interrupt.
82 * 5AP. Remote read is never used
83 * 6AP. not affected - worked around in hardware
84 * 7AP. not affected - worked around in hardware
85 * 8AP. worked around in hardware - we get explicit CS errors if not
86 * 9AP. only 'noapic' mode affected. Might generate spurious
87 * interrupts, we log only the first one and count the
89 * 10AP. not affected - worked around in hardware
90 * 11AP. Linux reads the APIC between writes to avoid this, as per
91 * the documentation. Make sure you preserve this as it affects
92 * the C stepping chips too.
93 * 12AP. not affected - worked around in hardware
94 * 13AP. not affected - worked around in hardware
95 * 14AP. we always deassert INIT during bootup
96 * 15AP. not affected - worked around in hardware
97 * 16AP. not affected - worked around in hardware
98 * 17AP. not affected - worked around in hardware
99 * 18AP. not affected - worked around in hardware
100 * 19AP. not affected - worked around in BIOS
102 * If this sounds worrying believe me these bugs are either ___RARE___,
103 * or are signal timing bugs worked around in hardware and there's
104 * about nothing of note with C stepping upwards.
107 DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0, };
110 * the following functions deal with sending IPIs between CPUs.
112 * We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
115 static inline int __prepare_ICR (unsigned int shortcut, int vector)
117 return APIC_DM_FIXED | shortcut | vector | APIC_DEST_LOGICAL;
120 static inline int __prepare_ICR2 (unsigned int mask)
122 return SET_APIC_DEST_FIELD(mask);
125 void __send_IPI_shortcut(unsigned int shortcut, int vector)
128 * Subtle. In the case of the 'never do double writes' workaround
129 * we have to lock out interrupts to be safe. As we don't care
130 * of the value read we use an atomic rmw access to avoid costly
131 * cli/sti. Otherwise we use an even cheaper single atomic write
139 apic_wait_icr_idle();
142 * No need to touch the target chip field
144 cfg = __prepare_ICR(shortcut, vector);
146 if (vector == DUMP_VECTOR) {
148 * Setup DUMP IPI to be delivered as an NMI
150 cfg = (cfg&~APIC_VECTOR_MASK)|APIC_DM_NMI;
154 * Send the IPI. The write to APIC_ICR fires this off.
156 apic_write_around(APIC_ICR, cfg);
159 void fastcall send_IPI_self(int vector)
161 __send_IPI_shortcut(APIC_DEST_SELF, vector);
165 * This is only used on smaller machines.
167 void send_IPI_mask_bitmask(cpumask_t cpumask, int vector)
169 unsigned long mask = cpus_addr(cpumask)[0];
173 local_irq_save(flags);
178 apic_wait_icr_idle();
181 * prepare target chip field
183 cfg = __prepare_ICR2(mask);
184 apic_write_around(APIC_ICR2, cfg);
189 cfg = __prepare_ICR(0, vector);
192 * Send the IPI. The write to APIC_ICR fires this off.
194 apic_write_around(APIC_ICR, cfg);
196 local_irq_restore(flags);
199 inline void send_IPI_mask_sequence(cpumask_t mask, int vector)
201 unsigned long cfg, flags;
202 unsigned int query_cpu;
205 * Hack. The clustered APIC addressing mode doesn't allow us to send
206 * to an arbitrary mask, so I do a unicasts to each CPU instead. This
207 * should be modified to do 1 message per cluster ID - mbligh
210 local_irq_save(flags);
212 for (query_cpu = 0; query_cpu < NR_CPUS; ++query_cpu) {
213 if (cpu_isset(query_cpu, mask)) {
218 apic_wait_icr_idle();
221 * prepare target chip field
223 cfg = __prepare_ICR2(cpu_to_logical_apicid(query_cpu));
224 apic_write_around(APIC_ICR2, cfg);
229 cfg = __prepare_ICR(0, vector);
231 if (vector == DUMP_VECTOR) {
233 * Setup DUMP IPI to be delivered as an NMI
235 cfg = (cfg&~APIC_VECTOR_MASK)|APIC_DM_NMI;
238 * Send the IPI. The write to APIC_ICR fires this off.
240 apic_write_around(APIC_ICR, cfg);
243 local_irq_restore(flags);
246 #include <mach_ipi.h> /* must come after the send_IPI functions above for inlining */
249 * Smarter SMP flushing macros.
250 * c/o Linus Torvalds.
252 * These mean you can really definitely utterly forget about
253 * writing to user space from interrupts. (Its not allowed anyway).
255 * Optimizations Manfred Spraul <manfred@colorfullife.com>
258 static cpumask_t flush_cpumask;
259 static struct mm_struct * flush_mm;
260 static unsigned long flush_va;
261 static spinlock_t tlbstate_lock = SPIN_LOCK_UNLOCKED;
262 #define FLUSH_ALL 0xffffffff
265 * We cannot call mmdrop() because we are in interrupt context,
266 * instead update mm->cpu_vm_mask.
268 * We need to reload %cr3 since the page tables may be going
269 * away from under us..
271 static inline void leave_mm (unsigned long cpu)
273 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
275 cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
276 load_cr3(swapper_pg_dir);
281 * The flush IPI assumes that a thread switch happens in this order:
282 * [cpu0: the cpu that switches]
283 * 1) switch_mm() either 1a) or 1b)
284 * 1a) thread switch to a different mm
285 * 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
286 * Stop ipi delivery for the old mm. This is not synchronized with
287 * the other cpus, but smp_invalidate_interrupt ignore flush ipis
288 * for the wrong mm, and in the worst case we perform a superflous
290 * 1a2) set cpu_tlbstate to TLBSTATE_OK
291 * Now the smp_invalidate_interrupt won't call leave_mm if cpu0
292 * was in lazy tlb mode.
293 * 1a3) update cpu_tlbstate[].active_mm
294 * Now cpu0 accepts tlb flushes for the new mm.
295 * 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
296 * Now the other cpus will send tlb flush ipis.
298 * 1b) thread switch without mm change
299 * cpu_tlbstate[].active_mm is correct, cpu0 already handles
301 * 1b1) set cpu_tlbstate to TLBSTATE_OK
302 * 1b2) test_and_set the cpu bit in cpu_vm_mask.
303 * Atomically set the bit [other cpus will start sending flush ipis],
305 * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
306 * 2) switch %%esp, ie current
308 * The interrupt must handle 2 special cases:
309 * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
310 * - the cpu performs speculative tlb reads, i.e. even if the cpu only
311 * runs in kernel space, the cpu could load tlb entries for user space
314 * The good news is that cpu_tlbstate is local to each cpu, no
315 * write/read ordering problems.
321 * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
322 * 2) Leave the mm if we are in the lazy tlb mode.
325 fastcall void smp_invalidate_interrupt(struct pt_regs *regs)
331 if (!cpu_isset(cpu, flush_cpumask))
334 * This was a BUG() but until someone can quote me the
335 * line from the intel manual that guarantees an IPI to
336 * multiple CPUs is retried _only_ on the erroring CPUs
337 * its staying as a return
342 if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
343 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
344 if (flush_va == FLUSH_ALL)
347 __flush_tlb_one(flush_va);
352 smp_mb__before_clear_bit();
353 cpu_clear(cpu, flush_cpumask);
354 smp_mb__after_clear_bit();
356 put_cpu_no_resched();
359 static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
364 * A couple of (to be removed) sanity checks:
366 * - we do not send IPIs to not-yet booted CPUs.
367 * - current CPU must not be in mask
368 * - mask must exist :)
370 BUG_ON(cpus_empty(cpumask));
372 cpus_and(tmp, cpumask, cpu_online_map);
373 BUG_ON(!cpus_equal(cpumask, tmp));
374 BUG_ON(cpu_isset(smp_processor_id(), cpumask));
378 * i'm not happy about this global shared spinlock in the
379 * MM hot path, but we'll see how contended it is.
380 * Temporarily this turns IRQs off, so that lockups are
381 * detected by the NMI watchdog.
383 spin_lock(&tlbstate_lock);
387 #if NR_CPUS <= BITS_PER_LONG
388 atomic_set_mask(cpumask, &flush_cpumask);
392 unsigned long *flush_mask = (unsigned long *)&flush_cpumask;
393 unsigned long *cpu_mask = (unsigned long *)&cpumask;
394 for (k = 0; k < BITS_TO_LONGS(NR_CPUS); ++k)
395 atomic_set_mask(cpu_mask[k], &flush_mask[k]);
399 * We have to send the IPI only to
402 send_IPI_mask(cpumask, INVALIDATE_TLB_VECTOR);
404 while (!cpus_empty(flush_cpumask))
405 /* nothing. lockup detection does not belong here */
410 spin_unlock(&tlbstate_lock);
413 void flush_tlb_current_task(void)
415 struct mm_struct *mm = current->mm;
419 cpu_mask = mm->cpu_vm_mask;
420 cpu_clear(smp_processor_id(), cpu_mask);
423 if (!cpus_empty(cpu_mask))
424 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
428 void flush_tlb_mm (struct mm_struct * mm)
433 cpu_mask = mm->cpu_vm_mask;
434 cpu_clear(smp_processor_id(), cpu_mask);
436 if (current->active_mm == mm) {
440 leave_mm(smp_processor_id());
442 if (!cpus_empty(cpu_mask))
443 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
448 void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
450 struct mm_struct *mm = vma->vm_mm;
454 cpu_mask = mm->cpu_vm_mask;
455 cpu_clear(smp_processor_id(), cpu_mask);
457 if (current->active_mm == mm) {
461 leave_mm(smp_processor_id());
464 if (!cpus_empty(cpu_mask))
465 flush_tlb_others(cpu_mask, mm, va);
470 static void do_flush_tlb_all(void* info)
472 unsigned long cpu = smp_processor_id();
475 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
479 void flush_tlb_all(void)
481 on_each_cpu(do_flush_tlb_all, NULL, 1, 1);
484 void dump_send_ipi(void)
486 send_IPI_allbutself(DUMP_VECTOR);
490 * this function sends a 'reschedule' IPI to another CPU.
491 * it goes straight through and wastes no time serializing
492 * anything. Worst case is that we lose a reschedule ...
494 void smp_send_reschedule(int cpu)
496 send_IPI_mask(cpumask_of_cpu(cpu), RESCHEDULE_VECTOR);
500 * Structure and data for smp_call_function(). This is designed to minimise
501 * static memory requirements. It also looks cleaner.
503 static spinlock_t call_lock = SPIN_LOCK_UNLOCKED;
505 struct call_data_struct {
506 void (*func) (void *info);
513 static struct call_data_struct * call_data;
516 * this function sends a 'generic call function' IPI to all other CPUs
520 int smp_call_function (void (*func) (void *info), void *info, int nonatomic,
523 * [SUMMARY] Run a function on all other CPUs.
524 * <func> The function to run. This must be fast and non-blocking.
525 * <info> An arbitrary pointer to pass to the function.
526 * <nonatomic> currently unused.
527 * <wait> If 1, wait (atomically) until function has completed on other CPUs.
528 * If 0, wait for the IPI to be received by other CPUs, but do not wait
529 * for the completion of the function on each CPU.
530 * If -1, do not wait for other CPUs to receive IPI.
531 * [RETURNS] 0 on success, else a negative status code. Does not return until
532 * remote CPUs are nearly ready to execute <<func>> or are or have executed.
534 * You must not call this function with disabled interrupts or from a
535 * hardware interrupt handler or from a bottom half handler.
538 static struct call_data_struct dumpdata;
539 struct call_data_struct normaldata;
540 struct call_data_struct *data;
541 int cpus = num_online_cpus()-1;
546 /* Can deadlock when called with interrupts disabled */
547 /* Only if we are waiting for other CPU to ack */
548 WARN_ON(irqs_disabled() && wait >= 0);
550 spin_lock(&call_lock);
552 /* if another cpu beat us, they win! */
554 spin_unlock(&call_lock);
563 atomic_set(&data->started, 0);
564 data->wait = wait > 0 ? wait : 0;
566 atomic_set(&data->finished, 0);
571 /* Send a message to all other CPUs and wait for them to respond */
572 send_IPI_allbutself(CALL_FUNCTION_VECTOR);
574 /* Wait for response */
576 while (atomic_read(&data->started) != cpus)
580 while (atomic_read(&data->finished) != cpus)
582 spin_unlock(&call_lock);
587 void stop_this_cpu (void * dummy)
592 cpu_clear(smp_processor_id(), cpu_online_map);
594 disable_local_APIC();
595 if (cpu_data[smp_processor_id()].hlt_works_ok)
596 for(;;) __asm__("hlt");
601 * this function calls the 'stop' function on all other CPUs in the system.
604 void smp_send_stop(void)
606 smp_call_function(stop_this_cpu, NULL, 1, 0);
609 disable_local_APIC();
613 EXPORT_SYMBOL(smp_send_stop);
616 * Reschedule call back. Nothing to do,
617 * all the work is done automatically when
618 * we return from the interrupt.
620 fastcall void smp_reschedule_interrupt(struct pt_regs *regs)
625 fastcall void smp_call_function_interrupt(struct pt_regs *regs)
627 void (*func) (void *info) = call_data->func;
628 void *info = call_data->info;
629 int wait = call_data->wait;
633 * Notify initiating CPU that I've grabbed the data and am
634 * about to execute the function
637 atomic_inc(&call_data->started);
639 * At this point the info structure may be out of scope unless wait==1
647 atomic_inc(&call_data->finished);