1 /* -*- mode: c; c-basic-offset: 8 -*- */
3 /* Copyright (C) 1999,2001
5 * Author: J.E.J.Bottomley@HansenPartnership.com
7 * linux/arch/i386/kernel/voyager_smp.c
9 * This file provides all the same external entries as smp.c but uses
10 * the voyager hal to provide the functionality
12 #include <linux/config.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/mc146818rtc.h>
17 #include <linux/cache.h>
18 #include <linux/interrupt.h>
19 #include <linux/smp_lock.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/bootmem.h>
23 #include <linux/completion.h>
25 #include <asm/voyager.h>
28 #include <asm/pgalloc.h>
29 #include <asm/tlbflush.h>
31 #include <asm/arch_hooks.h>
33 #include <linux/irq.h>
37 /* TLB state -- visible externally, indexed physically */
38 struct tlb_state cpu_tlbstate[NR_CPUS] __cacheline_aligned = {[0 ... NR_CPUS-1] = { &init_mm, 0 }};
40 /* CPU IRQ affinity -- set to all ones initially */
41 static unsigned long cpu_irq_affinity[NR_CPUS] __cacheline_aligned = { [0 ... NR_CPUS-1] = ~0UL };
43 /* Set when the idlers are all forked - Set in main.c but not actually
44 * used by any other parts of the kernel */
45 int smp_threads_ready = 0;
47 /* per CPU data structure (for /proc/cpuinfo et al), visible externally
48 * indexed physically */
49 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
51 /* physical ID of the CPU used to boot the system */
52 unsigned char boot_cpu_id;
54 /* The memory line addresses for the Quad CPIs */
55 struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS] __cacheline_aligned;
57 /* The masks for the Extended VIC processors, filled in by cat_init */
58 __u32 voyager_extended_vic_processors = 0;
60 /* Masks for the extended Quad processors which cannot be VIC booted */
61 __u32 voyager_allowed_boot_processors = 0;
63 /* The mask for the Quad Processors (both extended and non-extended) */
64 __u32 voyager_quad_processors = 0;
66 /* Total count of live CPUs, used in process.c to display
67 * the CPU information and in irq.c for the per CPU irq
68 * activity count. Finally exported by i386_ksyms.c */
69 static int voyager_extended_cpus = 1;
71 /* Have we found an SMP box - used by time.c to do the profiling
72 interrupt for timeslicing; do not set to 1 until the per CPU timer
73 interrupt is active */
74 int smp_found_config = 0;
76 /* Used for the invalidate map that's also checked in the spinlock */
77 static volatile unsigned long smp_invalidate_needed;
79 /* Bitmask of currently online CPUs - used by setup.c for
80 /proc/cpuinfo, visible externally but still physical */
81 cpumask_t cpu_online_map = CPU_MASK_NONE;
83 /* Bitmask of CPUs present in the system - exported by i386_syms.c, used
84 * by scheduler but indexed physically */
85 cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
87 /* estimate of time used to flush the SMP-local cache - used in
88 * processor affinity calculations */
89 cycles_t cacheflush_time = 0;
91 /* cache decay ticks for scheduler---a fairly useless quantity for the
92 voyager system with its odd affinity and huge L3 cache */
93 unsigned long cache_decay_ticks = 20;
96 /* The internal functions */
97 static void send_CPI(__u32 cpuset, __u8 cpi);
98 static void ack_CPI(__u8 cpi);
99 static int ack_QIC_CPI(__u8 cpi);
100 static void ack_special_QIC_CPI(__u8 cpi);
101 static void ack_VIC_CPI(__u8 cpi);
102 static void send_CPI_allbutself(__u8 cpi);
103 static void enable_vic_irq(unsigned int irq);
104 static void disable_vic_irq(unsigned int irq);
105 static unsigned int startup_vic_irq(unsigned int irq);
106 static void enable_local_vic_irq(unsigned int irq);
107 static void disable_local_vic_irq(unsigned int irq);
108 static void before_handle_vic_irq(unsigned int irq);
109 static void after_handle_vic_irq(unsigned int irq);
110 static void set_vic_irq_affinity(unsigned int irq, cpumask_t mask);
111 static void ack_vic_irq(unsigned int irq);
112 static void vic_enable_cpi(void);
113 static void do_boot_cpu(__u8 cpuid);
114 static void do_quad_bootstrap(void);
115 static inline void wrapper_smp_local_timer_interrupt(struct pt_regs *);
117 int hard_smp_processor_id(void);
119 /* Inline functions */
121 send_one_QIC_CPI(__u8 cpu, __u8 cpi)
123 voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi =
124 (smp_processor_id() << 16) + cpi;
128 send_QIC_CPI(__u32 cpuset, __u8 cpi)
132 for_each_online_cpu(cpu) {
133 if(cpuset & (1<<cpu)) {
135 if(!cpu_isset(cpu, cpu_online_map))
136 VDEBUG(("CPU%d sending cpi %d to CPU%d not in cpu_online_map\n", hard_smp_processor_id(), cpi, cpu));
138 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
144 send_one_CPI(__u8 cpu, __u8 cpi)
146 if(voyager_quad_processors & (1<<cpu))
147 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
149 send_CPI(1<<cpu, cpi);
153 send_CPI_allbutself(__u8 cpi)
155 __u8 cpu = smp_processor_id();
156 __u32 mask = cpus_addr(cpu_online_map)[0] & ~(1 << cpu);
163 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
164 return ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER);
168 is_cpu_extended(void)
170 __u8 cpu = hard_smp_processor_id();
172 return(voyager_extended_vic_processors & (1<<cpu));
176 is_cpu_vic_boot(void)
178 __u8 cpu = hard_smp_processor_id();
180 return(voyager_extended_vic_processors
181 & voyager_allowed_boot_processors & (1<<cpu));
189 case VIC_CPU_BOOT_CPI:
190 if(is_cpu_quad() && !is_cpu_vic_boot())
197 /* These are slightly strange. Even on the Quad card,
198 * They are vectored as VIC CPIs */
200 ack_special_QIC_CPI(cpi);
205 printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi);
210 /* local variables */
212 /* The VIC IRQ descriptors -- these look almost identical to the
213 * 8259 IRQs except that masks and things must be kept per processor
215 static struct hw_interrupt_type vic_irq_type = {
217 startup_vic_irq, /* startup */
218 disable_vic_irq, /* shutdown */
219 enable_vic_irq, /* enable */
220 disable_vic_irq, /* disable */
221 before_handle_vic_irq, /* ack */
222 after_handle_vic_irq, /* end */
223 set_vic_irq_affinity, /* affinity */
226 /* used to count up as CPUs are brought on line (starts at 0) */
227 static int cpucount = 0;
229 /* steal a page from the bottom of memory for the trampoline and
230 * squirrel its address away here. This will be in kernel virtual
232 static __u32 trampoline_base;
234 /* The per cpu profile stuff - used in smp_local_timer_interrupt */
235 static DEFINE_PER_CPU(int, prof_multiplier) = 1;
236 static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
237 static DEFINE_PER_CPU(int, prof_counter) = 1;
239 /* the map used to check if a CPU has booted */
240 static __u32 cpu_booted_map;
242 /* the synchronize flag used to hold all secondary CPUs spinning in
243 * a tight loop until the boot sequence is ready for them */
244 static cpumask_t smp_commenced_mask = CPU_MASK_NONE;
246 /* This is for the new dynamic CPU boot code */
247 cpumask_t cpu_callin_map = CPU_MASK_NONE;
248 cpumask_t cpu_callout_map = CPU_MASK_NONE;
250 /* The per processor IRQ masks (these are usually kept in sync) */
251 static __u16 vic_irq_mask[NR_CPUS] __cacheline_aligned;
253 /* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
254 static __u16 vic_irq_enable_mask[NR_CPUS] __cacheline_aligned = { 0 };
256 /* Lock for enable/disable of VIC interrupts */
257 static spinlock_t vic_irq_lock __cacheline_aligned = SPIN_LOCK_UNLOCKED;
259 /* The boot processor is correctly set up in PC mode when it
260 * comes up, but the secondaries need their master/slave 8259
261 * pairs initializing correctly */
263 /* Interrupt counters (per cpu) and total - used to try to
264 * even up the interrupt handling routines */
265 static long vic_intr_total = 0;
266 static long vic_intr_count[NR_CPUS] __cacheline_aligned = { 0 };
267 static unsigned long vic_tick[NR_CPUS] __cacheline_aligned = { 0 };
269 /* Since we can only use CPI0, we fake all the other CPIs */
270 static unsigned long vic_cpi_mailbox[NR_CPUS] __cacheline_aligned;
272 /* debugging routine to read the isr of the cpu's pic */
279 isr = inb(0xa0) << 8;
290 /* not a quad, no setup */
293 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
294 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
296 if(is_cpu_extended()) {
297 /* the QIC duplicate of the VIC base register */
298 outb(VIC_DEFAULT_CPI_BASE, QIC_VIC_CPI_BASE_REGISTER);
299 outb(QIC_DEFAULT_CPI_BASE, QIC_CPI_BASE_REGISTER);
301 /* FIXME: should set up the QIC timer and memory parity
302 * error vectors here */
309 outb(1, VIC_REDIRECT_REGISTER_1);
310 /* clear the claim registers for dynamic routing */
311 outb(0, VIC_CLAIM_REGISTER_0);
312 outb(0, VIC_CLAIM_REGISTER_1);
314 outb(0, VIC_PRIORITY_REGISTER);
315 /* Set the Primary and Secondary Microchannel vector
316 * bases to be the same as the ordinary interrupts
318 * FIXME: This would be more efficient using separate
320 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
321 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
322 /* Now initiallise the master PIC belonging to this CPU by
323 * sending the four ICWs */
325 /* ICW1: level triggered, ICW4 needed */
328 /* ICW2: vector base */
329 outb(FIRST_EXTERNAL_VECTOR, 0x21);
331 /* ICW3: slave at line 2 */
334 /* ICW4: 8086 mode */
337 /* now the same for the slave PIC */
339 /* ICW1: level trigger, ICW4 needed */
342 /* ICW2: slave vector base */
343 outb(FIRST_EXTERNAL_VECTOR + 8, 0xA1);
348 /* ICW4: 8086 mode */
353 do_quad_bootstrap(void)
355 if(is_cpu_quad() && is_cpu_vic_boot()) {
358 __u8 cpuid = hard_smp_processor_id();
360 local_irq_save(flags);
362 for(i = 0; i<4; i++) {
363 /* FIXME: this would be >>3 &0x7 on the 32 way */
364 if(((cpuid >> 2) & 0x03) == i)
365 /* don't lower our own mask! */
368 /* masquerade as local Quad CPU */
369 outb(QIC_CPUID_ENABLE | i, QIC_PROCESSOR_ID);
370 /* enable the startup CPI */
371 outb(QIC_BOOT_CPI_MASK, QIC_MASK_REGISTER1);
373 outb(0, QIC_PROCESSOR_ID);
375 local_irq_restore(flags);
380 /* Set up all the basic stuff: read the SMP config and make all the
381 * SMP information reflect only the boot cpu. All others will be
382 * brought on-line later. */
384 find_smp_config(void)
388 boot_cpu_id = hard_smp_processor_id();
390 printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id);
392 /* initialize the CPU structures (moved from smp_boot_cpus) */
393 for(i=0; i<NR_CPUS; i++) {
394 cpu_irq_affinity[i] = ~0;
396 cpu_online_map = cpumask_of_cpu(boot_cpu_id);
398 /* The boot CPU must be extended */
399 voyager_extended_vic_processors = 1<<boot_cpu_id;
400 /* initially, all of the first 8 cpu's can boot */
401 voyager_allowed_boot_processors = 0xff;
402 /* set up everything for just this CPU, we can alter
403 * this as we start the other CPUs later */
404 /* now get the CPU disposition from the extended CMOS */
405 cpus_addr(phys_cpu_present_map)[0] = voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK);
406 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8;
407 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 2) << 16;
408 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 3) << 24;
409 printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n", cpus_addr(phys_cpu_present_map)[0]);
410 /* Here we set up the VIC to enable SMP */
411 /* enable the CPIs by writing the base vector to their register */
412 outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER);
413 outb(1, VIC_REDIRECT_REGISTER_1);
414 /* set the claim registers for static routing --- Boot CPU gets
415 * all interrupts untill all other CPUs started */
416 outb(0xff, VIC_CLAIM_REGISTER_0);
417 outb(0xff, VIC_CLAIM_REGISTER_1);
418 /* Set the Primary and Secondary Microchannel vector
419 * bases to be the same as the ordinary interrupts
421 * FIXME: This would be more efficient using separate
423 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
424 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
426 /* Finally tell the firmware that we're driving */
427 outb(inb(VOYAGER_SUS_IN_CONTROL_PORT) | VOYAGER_IN_CONTROL_FLAG,
428 VOYAGER_SUS_IN_CONTROL_PORT);
430 current_thread_info()->cpu = boot_cpu_id;
434 * The bootstrap kernel entry code has set these up. Save them
435 * for a given CPU, id is physical */
437 smp_store_cpu_info(int id)
439 struct cpuinfo_x86 *c=&cpu_data[id];
446 /* set up the trampoline and return the physical address of the code */
448 setup_trampoline(void)
450 /* these two are global symbols in trampoline.S */
451 extern __u8 trampoline_end[];
452 extern __u8 trampoline_data[];
454 memcpy((__u8 *)trampoline_base, trampoline_data,
455 trampoline_end - trampoline_data);
456 return virt_to_phys((__u8 *)trampoline_base);
459 /* Routine initially called when a non-boot CPU is brought online */
461 start_secondary(void *unused)
463 __u8 cpuid = hard_smp_processor_id();
464 /* external functions not defined in the headers */
465 extern void calibrate_delay(void);
466 extern int cpu_idle(void);
470 /* OK, we're in the routine */
471 ack_CPI(VIC_CPU_BOOT_CPI);
473 /* setup the 8259 master slave pair belonging to this CPU ---
474 * we won't actually receive any until the boot CPU
475 * relinquishes it's static routing mask */
480 if(is_cpu_quad() && !is_cpu_vic_boot()) {
481 /* clear the boot CPI */
484 dummy = voyager_quad_cpi_addr[cpuid]->qic_cpi[VIC_CPU_BOOT_CPI].cpi;
485 printk("read dummy %d\n", dummy);
488 /* lower the mask to receive CPIs */
491 VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid));
493 /* enable interrupts */
496 /* get our bogomips */
499 /* save our processor parameters */
500 smp_store_cpu_info(cpuid);
502 /* if we're a quad, we may need to bootstrap other CPUs */
505 /* FIXME: this is rather a poor hack to prevent the CPU
506 * activating softirqs while it's supposed to be waiting for
507 * permission to proceed. Without this, the new per CPU stuff
508 * in the softirqs will fail */
510 cpu_set(cpuid, cpu_callin_map);
512 /* signal that we're done */
515 while (!cpu_isset(cpuid, smp_commenced_mask))
521 cpu_set(cpuid, cpu_online_map);
526 static struct task_struct * __init
530 /* don't care about the eip and regs settings since we'll
531 * never reschedule the forked task. */
532 return copy_process(CLONE_VM|CLONE_IDLETASK, 0, ®s, 0, NULL, NULL);
536 /* Routine to kick start the given CPU and wait for it to report ready
537 * (or timeout in startup). When this routine returns, the requested
538 * CPU is either fully running and configured or known to be dead.
540 * We call this routine sequentially 1 CPU at a time, so no need for
544 do_boot_cpu(__u8 cpu)
546 struct task_struct *idle;
549 int quad_boot = (1<<cpu) & voyager_quad_processors
550 & ~( voyager_extended_vic_processors
551 & voyager_allowed_boot_processors);
553 /* For the 486, we can't use the 4Mb page table trick, so
554 * must map a region of memory */
557 unsigned long *page_table_copies = (unsigned long *)
558 __get_free_page(GFP_KERNEL);
560 pgd_t orig_swapper_pg_dir0;
562 /* This is an area in head.S which was used to set up the
563 * initial kernel stack. We need to alter this to give the
564 * booting CPU a new stack (taken from its idle process) */
569 /* This is the format of the CPI IDT gate (in real mode) which
570 * we're hijacking to boot the CPU */
579 __u32 *hijack_vector;
580 __u32 start_phys_address = setup_trampoline();
582 /* There's a clever trick to this: The linux trampoline is
583 * compiled to begin at absolute location zero, so make the
584 * address zero but have the data segment selector compensate
585 * for the actual address */
586 hijack_source.idt.Offset = start_phys_address & 0x000F;
587 hijack_source.idt.Segment = (start_phys_address >> 4) & 0xFFFF;
590 idle = fork_by_hand();
592 panic("failed fork for CPU%d", cpu);
594 wake_up_forked_process(idle);
596 init_idle(idle, cpu);
598 idle->thread.eip = (unsigned long) start_secondary;
599 unhash_process(idle);
600 /* init_tasks (in sched.c) is indexed logically */
601 stack_start.esp = (void *) idle->thread.esp;
605 /* Note: Don't modify initial ss override */
606 VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu,
607 (unsigned long)hijack_source.val, hijack_source.idt.Segment,
608 hijack_source.idt.Offset, stack_start.esp));
609 /* set the original swapper_pg_dir[0] to map 0 to 4Mb transparently
610 * (so that the booting CPU can find start_32 */
611 orig_swapper_pg_dir0 = swapper_pg_dir[0];
613 if(page_table_copies == NULL)
614 panic("No free memory for 486 page tables\n");
615 for(i = 0; i < PAGE_SIZE/sizeof(unsigned long); i++)
616 page_table_copies[i] = (i * PAGE_SIZE)
617 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
619 ((unsigned long *)swapper_pg_dir)[0] =
620 ((virt_to_phys(page_table_copies)) & PAGE_MASK)
621 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
623 ((unsigned long *)swapper_pg_dir)[0] =
624 (virt_to_phys(pg0) & PAGE_MASK)
625 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
629 printk("CPU %d: non extended Quad boot\n", cpu);
630 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + QIC_DEFAULT_CPI_BASE)*4);
631 *hijack_vector = hijack_source.val;
633 printk("CPU%d: extended VIC boot\n", cpu);
634 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE)*4);
635 *hijack_vector = hijack_source.val;
636 /* VIC errata, may also receive interrupt at this address */
637 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI + VIC_DEFAULT_CPI_BASE)*4);
638 *hijack_vector = hijack_source.val;
640 /* All non-boot CPUs start with interrupts fully masked. Need
641 * to lower the mask of the CPI we're about to send. We do
642 * this in the VIC by masquerading as the processor we're
643 * about to boot and lowering its interrupt mask */
644 local_irq_save(flags);
646 send_one_QIC_CPI(cpu, VIC_CPU_BOOT_CPI);
648 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
649 /* here we're altering registers belonging to `cpu' */
651 outb(VIC_BOOT_INTERRUPT_MASK, 0x21);
652 /* now go back to our original identity */
653 outb(boot_cpu_id, VIC_PROCESSOR_ID);
655 /* and boot the CPU */
657 send_CPI((1<<cpu), VIC_CPU_BOOT_CPI);
660 local_irq_restore(flags);
662 /* now wait for it to become ready (or timeout) */
663 for(timeout = 0; timeout < 50000; timeout++) {
668 /* reset the page table */
669 swapper_pg_dir[0] = orig_swapper_pg_dir0;
672 free_page((unsigned long)page_table_copies);
675 if (cpu_booted_map) {
676 VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
677 cpu, smp_processor_id()));
679 printk("CPU%d: ", cpu);
680 print_cpu_info(&cpu_data[cpu]);
682 cpu_set(cpu, cpu_callout_map);
685 printk("CPU%d FAILED TO BOOT: ", cpu);
686 if (*((volatile unsigned char *)phys_to_virt(start_phys_address))==0xA5)
689 printk("Not responding.\n");
700 /* CAT BUS initialisation must be done after the memory */
701 /* FIXME: The L4 has a catbus too, it just needs to be
702 * accessed in a totally different way */
703 if(voyager_level == 5) {
706 /* now that the cat has probed the Voyager System Bus, sanity
707 * check the cpu map */
708 if( ((voyager_quad_processors | voyager_extended_vic_processors)
709 & cpus_addr(phys_cpu_present_map)[0]) != cpus_addr(phys_cpu_present_map)[0]) {
711 printk("\n\n***WARNING*** Sanity check of CPU present map FAILED\n");
713 } else if(voyager_level == 4)
714 voyager_extended_vic_processors = cpus_addr(phys_cpu_present_map)[0];
716 /* this sets up the idle task to run on the current cpu */
717 voyager_extended_cpus = 1;
718 /* Remove the global_irq_holder setting, it triggers a BUG() on
719 * schedule at the moment */
720 //global_irq_holder = boot_cpu_id;
722 /* FIXME: Need to do something about this but currently only works
723 * on CPUs with a tsc which none of mine have.
724 smp_tune_scheduling();
726 smp_store_cpu_info(boot_cpu_id);
727 printk("CPU%d: ", boot_cpu_id);
728 print_cpu_info(&cpu_data[boot_cpu_id]);
731 /* booting on a Quad CPU */
732 printk("VOYAGER SMP: Boot CPU is Quad\n");
737 /* enable our own CPIs */
740 cpu_set(boot_cpu_id, cpu_online_map);
741 cpu_set(boot_cpu_id, cpu_callout_map);
743 /* loop over all the extended VIC CPUs and boot them. The
744 * Quad CPUs must be bootstrapped by their extended VIC cpu */
745 for(i = 0; i < NR_CPUS; i++) {
746 if(i == boot_cpu_id || !cpu_isset(i, phys_cpu_present_map))
749 /* This udelay seems to be needed for the Quad boots
750 * don't remove unless you know what you're doing */
753 /* we could compute the total bogomips here, but why bother?,
754 * Code added from smpboot.c */
756 unsigned long bogosum = 0;
757 for (i = 0; i < NR_CPUS; i++)
758 if (cpu_isset(i, cpu_online_map))
759 bogosum += cpu_data[i].loops_per_jiffy;
760 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
763 (bogosum/(5000/HZ))%100);
765 voyager_extended_cpus = hweight32(voyager_extended_vic_processors);
766 printk("VOYAGER: Extended (interrupt handling CPUs): %d, non-extended: %d\n", voyager_extended_cpus, num_booting_cpus() - voyager_extended_cpus);
767 /* that's it, switch to symmetric mode */
768 outb(0, VIC_PRIORITY_REGISTER);
769 outb(0, VIC_CLAIM_REGISTER_0);
770 outb(0, VIC_CLAIM_REGISTER_1);
772 VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
775 /* Reload the secondary CPUs task structure (this function does not
778 initialize_secondary(void)
782 set_current(hard_get_current());
786 * We don't actually need to load the full TSS,
787 * basically just the stack pointer and the eip.
794 :"r" (current->thread.esp),"r" (current->thread.eip));
797 /* handle a Voyager SYS_INT -- If we don't, the base board will
800 * System interrupts occur because some problem was detected on the
801 * various busses. To find out what you have to probe all the
802 * hardware via the CAT bus. FIXME: At the moment we do nothing. */
804 smp_vic_sys_interrupt(void)
806 ack_CPI(VIC_SYS_INT);
807 printk("Voyager SYSTEM INTERRUPT\n");
810 /* Handle a voyager CMN_INT; These interrupts occur either because of
811 * a system status change or because a single bit memory error
812 * occurred. FIXME: At the moment, ignore all this. */
814 smp_vic_cmn_interrupt(void)
816 static __u8 in_cmn_int = 0;
817 static spinlock_t cmn_int_lock = SPIN_LOCK_UNLOCKED;
819 /* common ints are broadcast, so make sure we only do this once */
820 _raw_spin_lock(&cmn_int_lock);
825 _raw_spin_unlock(&cmn_int_lock);
827 VDEBUG(("Voyager COMMON INTERRUPT\n"));
829 if(voyager_level == 5)
830 voyager_cat_do_common_interrupt();
832 _raw_spin_lock(&cmn_int_lock);
835 _raw_spin_unlock(&cmn_int_lock);
836 ack_CPI(VIC_CMN_INT);
840 * Reschedule call back. Nothing to do, all the work is done
841 * automatically when we return from the interrupt. */
843 smp_reschedule_interrupt(void)
848 static struct mm_struct * flush_mm;
849 static unsigned long flush_va;
850 static spinlock_t tlbstate_lock = SPIN_LOCK_UNLOCKED;
851 #define FLUSH_ALL 0xffffffff
854 * We cannot call mmdrop() because we are in interrupt context,
855 * instead update mm->cpu_vm_mask.
857 * We need to reload %cr3 since the page tables may be going
858 * away from under us..
861 leave_mm (unsigned long cpu)
863 if (cpu_tlbstate[cpu].state == TLBSTATE_OK)
865 cpu_clear(cpu, cpu_tlbstate[cpu].active_mm->cpu_vm_mask);
866 load_cr3(swapper_pg_dir);
871 * Invalidate call-back
874 smp_invalidate_interrupt(void)
876 __u8 cpu = smp_processor_id();
878 if (!test_bit(cpu, &smp_invalidate_needed))
880 /* This will flood messages. Don't uncomment unless you see
881 * Problems with cross cpu invalidation
882 VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
883 smp_processor_id()));
886 if (flush_mm == cpu_tlbstate[cpu].active_mm) {
887 if (cpu_tlbstate[cpu].state == TLBSTATE_OK) {
888 if (flush_va == FLUSH_ALL)
891 __flush_tlb_one(flush_va);
895 smp_mb__before_clear_bit();
896 clear_bit(cpu, &smp_invalidate_needed);
897 smp_mb__after_clear_bit();
900 /* All the new flush operations for 2.4 */
903 /* This routine is called with a physical cpu mask */
905 flush_tlb_others (unsigned long cpumask, struct mm_struct *mm,
912 if ((cpumask & cpus_addr(cpu_online_map)[0]) != cpumask)
914 if (cpumask & (1 << smp_processor_id()))
919 spin_lock(&tlbstate_lock);
923 atomic_set_mask(cpumask, &smp_invalidate_needed);
925 * We have to send the CPI only to
928 send_CPI(cpumask, VIC_INVALIDATE_CPI);
930 while (smp_invalidate_needed) {
933 printk("***WARNING*** Stuck doing invalidate CPI (CPU%d)\n", smp_processor_id());
938 /* Uncomment only to debug invalidation problems
939 VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
944 spin_unlock(&tlbstate_lock);
948 flush_tlb_current_task(void)
950 struct mm_struct *mm = current->mm;
951 unsigned long cpu_mask;
955 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
958 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
965 flush_tlb_mm (struct mm_struct * mm)
967 unsigned long cpu_mask;
971 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
973 if (current->active_mm == mm) {
977 leave_mm(smp_processor_id());
980 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
985 void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
987 struct mm_struct *mm = vma->vm_mm;
988 unsigned long cpu_mask;
992 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
993 if (current->active_mm == mm) {
997 leave_mm(smp_processor_id());
1001 flush_tlb_others(cpu_mask, mm, va);
1006 /* enable the requested IRQs */
1008 smp_enable_irq_interrupt(void)
1011 __u8 cpu = get_cpu();
1013 VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu,
1014 vic_irq_enable_mask[cpu]));
1016 spin_lock(&vic_irq_lock);
1017 for(irq = 0; irq < 16; irq++) {
1018 if(vic_irq_enable_mask[cpu] & (1<<irq))
1019 enable_local_vic_irq(irq);
1021 vic_irq_enable_mask[cpu] = 0;
1022 spin_unlock(&vic_irq_lock);
1024 put_cpu_no_resched();
1028 * CPU halt call-back
1031 smp_stop_cpu_function(void *dummy)
1033 VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
1034 cpu_clear(smp_processor_id(), cpu_online_map);
1035 local_irq_disable();
1040 static spinlock_t call_lock = SPIN_LOCK_UNLOCKED;
1042 struct call_data_struct {
1043 void (*func) (void *info);
1045 volatile unsigned long started;
1046 volatile unsigned long finished;
1050 static struct call_data_struct * call_data;
1052 /* execute a thread on a new CPU. The function to be called must be
1053 * previously set up. This is used to schedule a function for
1054 * execution on all CPU's - set up the function then broadcast a
1055 * function_interrupt CPI to come here on each CPU */
1057 smp_call_function_interrupt(void)
1059 void (*func) (void *info) = call_data->func;
1060 void *info = call_data->info;
1061 /* must take copy of wait because call_data may be replaced
1062 * unless the function is waiting for us to finish */
1063 int wait = call_data->wait;
1064 __u8 cpu = smp_processor_id();
1067 * Notify initiating CPU that I've grabbed the data and am
1068 * about to execute the function
1071 if(!test_and_clear_bit(cpu, &call_data->started)) {
1072 /* If the bit wasn't set, this could be a replay */
1073 printk(KERN_WARNING "VOYAGER SMP: CPU %d received call funtion with no call pending\n", cpu);
1077 * At this point the info structure may be out of scope unless wait==1
1084 clear_bit(cpu, &call_data->finished);
1088 /* Call this function on all CPUs using the function_interrupt above
1089 <func> The function to run. This must be fast and non-blocking.
1090 <info> An arbitrary pointer to pass to the function.
1091 <retry> If true, keep retrying until ready.
1092 <wait> If true, wait until function has completed on other CPUs.
1093 [RETURNS] 0 on success, else a negative status code. Does not return until
1094 remote CPUs are nearly ready to execute <<func>> or are or have executed.
1097 smp_call_function (void (*func) (void *info), void *info, int retry,
1100 struct call_data_struct data;
1101 __u32 mask = cpus_addr(cpu_online_map)[0];
1103 mask &= ~(1<<smp_processor_id());
1108 /* Can deadlock when called with interrupts disabled */
1109 WARN_ON(irqs_disabled());
1113 data.started = mask;
1116 data.finished = mask;
1118 spin_lock(&call_lock);
1121 /* Send a message to all other CPUs and wait for them to respond */
1122 send_CPI_allbutself(VIC_CALL_FUNCTION_CPI);
1124 /* Wait for response */
1125 while (data.started)
1129 while (data.finished)
1132 spin_unlock(&call_lock);
1137 /* Sorry about the name. In an APIC based system, the APICs
1138 * themselves are programmed to send a timer interrupt. This is used
1139 * by linux to reschedule the processor. Voyager doesn't have this,
1140 * so we use the system clock to interrupt one processor, which in
1141 * turn, broadcasts a timer CPI to all the others --- we receive that
1142 * CPI here. We don't use this actually for counting so losing
1143 * ticks doesn't matter
1145 * FIXME: For those CPU's which actually have a local APIC, we could
1146 * try to use it to trigger this interrupt instead of having to
1147 * broadcast the timer tick. Unfortunately, all my pentium DYADs have
1148 * no local APIC, so I can't do this
1150 * This function is currently a placeholder and is unused in the code */
1152 smp_apic_timer_interrupt(struct pt_regs regs)
1154 wrapper_smp_local_timer_interrupt(®s);
1157 /* All of the QUAD interrupt GATES */
1159 smp_qic_timer_interrupt(struct pt_regs regs)
1161 ack_QIC_CPI(QIC_TIMER_CPI);
1162 wrapper_smp_local_timer_interrupt(®s);
1166 smp_qic_invalidate_interrupt(void)
1168 ack_QIC_CPI(QIC_INVALIDATE_CPI);
1169 smp_invalidate_interrupt();
1173 smp_qic_reschedule_interrupt(void)
1175 ack_QIC_CPI(QIC_RESCHEDULE_CPI);
1176 smp_reschedule_interrupt();
1180 smp_qic_enable_irq_interrupt(void)
1182 ack_QIC_CPI(QIC_ENABLE_IRQ_CPI);
1183 smp_enable_irq_interrupt();
1187 smp_qic_call_function_interrupt(void)
1189 ack_QIC_CPI(QIC_CALL_FUNCTION_CPI);
1190 smp_call_function_interrupt();
1194 smp_vic_cpi_interrupt(struct pt_regs regs)
1196 __u8 cpu = smp_processor_id();
1199 ack_QIC_CPI(VIC_CPI_LEVEL0);
1201 ack_VIC_CPI(VIC_CPI_LEVEL0);
1203 if(test_and_clear_bit(VIC_TIMER_CPI, &vic_cpi_mailbox[cpu]))
1204 wrapper_smp_local_timer_interrupt(®s);
1205 if(test_and_clear_bit(VIC_INVALIDATE_CPI, &vic_cpi_mailbox[cpu]))
1206 smp_invalidate_interrupt();
1207 if(test_and_clear_bit(VIC_RESCHEDULE_CPI, &vic_cpi_mailbox[cpu]))
1208 smp_reschedule_interrupt();
1209 if(test_and_clear_bit(VIC_ENABLE_IRQ_CPI, &vic_cpi_mailbox[cpu]))
1210 smp_enable_irq_interrupt();
1211 if(test_and_clear_bit(VIC_CALL_FUNCTION_CPI, &vic_cpi_mailbox[cpu]))
1212 smp_call_function_interrupt();
1216 do_flush_tlb_all(void* info)
1218 unsigned long cpu = smp_processor_id();
1221 if (cpu_tlbstate[cpu].state == TLBSTATE_LAZY)
1226 /* flush the TLB of every active CPU in the system */
1230 on_each_cpu(do_flush_tlb_all, 0, 1, 1);
1233 /* used to set up the trampoline for other CPUs when the memory manager
1236 smp_alloc_memory(void)
1238 trampoline_base = (__u32)alloc_bootmem_low_pages(PAGE_SIZE);
1239 if(__pa(trampoline_base) >= 0x93000)
1243 /* send a reschedule CPI to one CPU by physical CPU number*/
1245 smp_send_reschedule(int cpu)
1247 send_one_CPI(cpu, VIC_RESCHEDULE_CPI);
1252 hard_smp_processor_id(void)
1255 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
1256 if((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER)
1257 return cpumask & 0x1F;
1259 for(i = 0; i < 8; i++) {
1260 if(cpumask & (1<<i))
1263 printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask);
1267 /* broadcast a halt to all other CPUs */
1271 smp_call_function(smp_stop_cpu_function, NULL, 1, 1);
1274 /* this function is triggered in time.c when a clock tick fires
1275 * we need to re-broadcast the tick to all CPUs */
1277 smp_vic_timer_interrupt(struct pt_regs *regs)
1279 send_CPI_allbutself(VIC_TIMER_CPI);
1280 smp_local_timer_interrupt(regs);
1284 wrapper_smp_local_timer_interrupt(struct pt_regs *regs)
1287 smp_local_timer_interrupt(regs);
1291 /* local (per CPU) timer interrupt. It does both profiling and
1292 * process statistics/rescheduling.
1294 * We do profiling in every local tick, statistics/rescheduling
1295 * happen only every 'profiling multiplier' ticks. The default
1296 * multiplier is 1 and it can be changed by writing the new multiplier
1297 * value into /proc/profile.
1300 smp_local_timer_interrupt(struct pt_regs * regs)
1302 int cpu = smp_processor_id();
1305 x86_do_profile(regs);
1307 if (--per_cpu(prof_counter, cpu) <= 0) {
1309 * The multiplier may have changed since the last time we got
1310 * to this point as a result of the user writing to
1311 * /proc/profile. In this case we need to adjust the APIC
1312 * timer accordingly.
1314 * Interrupts are already masked off at this point.
1316 per_cpu(prof_counter,cpu) = per_cpu(prof_multiplier, cpu);
1317 if (per_cpu(prof_counter, cpu) !=
1318 per_cpu(prof_old_multiplier, cpu)) {
1319 /* FIXME: need to update the vic timer tick here */
1320 per_cpu(prof_old_multiplier, cpu) =
1321 per_cpu(prof_counter, cpu);
1324 update_process_times(user_mode(regs));
1327 if( ((1<<cpu) & voyager_extended_vic_processors) == 0)
1328 /* only extended VIC processors participate in
1329 * interrupt distribution */
1333 * We take the 'long' return path, and there every subsystem
1334 * grabs the apropriate locks (kernel lock/ irq lock).
1336 * we might want to decouple profiling from the 'long path',
1337 * and do the profiling totally in assembly.
1339 * Currently this isn't too much of an issue (performance wise),
1340 * we can take more than 100K local irqs per second on a 100 MHz P5.
1343 if((++vic_tick[cpu] & 0x7) != 0)
1345 /* get here every 16 ticks (about every 1/6 of a second) */
1347 /* Change our priority to give someone else a chance at getting
1348 * the IRQ. The algorithm goes like this:
1350 * In the VIC, the dynamically routed interrupt is always
1351 * handled by the lowest priority eligible (i.e. receiving
1352 * interrupts) CPU. If >1 eligible CPUs are equal lowest, the
1353 * lowest processor number gets it.
1355 * The priority of a CPU is controlled by a special per-CPU
1356 * VIC priority register which is 3 bits wide 0 being lowest
1357 * and 7 highest priority..
1359 * Therefore we subtract the average number of interrupts from
1360 * the number we've fielded. If this number is negative, we
1361 * lower the activity count and if it is positive, we raise
1364 * I'm afraid this still leads to odd looking interrupt counts:
1365 * the totals are all roughly equal, but the individual ones
1366 * look rather skewed.
1368 * FIXME: This algorithm is total crap when mixed with SMP
1369 * affinity code since we now try to even up the interrupt
1370 * counts when an affinity binding is keeping them on a
1372 weight = (vic_intr_count[cpu]*voyager_extended_cpus
1373 - vic_intr_total) >> 4;
1380 outb((__u8)weight, VIC_PRIORITY_REGISTER);
1382 #ifdef VOYAGER_DEBUG
1383 if((vic_tick[cpu] & 0xFFF) == 0) {
1384 /* print this message roughly every 25 secs */
1385 printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
1386 cpu, vic_tick[cpu], weight);
1391 /* setup the profiling timer */
1393 setup_profiling_timer(unsigned int multiplier)
1401 * Set the new multiplier for each CPU. CPUs don't start using the
1402 * new values until the next timer interrupt in which they do process
1405 for (i = 0; i < NR_CPUS; ++i)
1406 per_cpu(prof_multiplier, i) = multiplier;
1412 /* The CPIs are handled in the per cpu 8259s, so they must be
1413 * enabled to be received: FIX: enabling the CPIs in the early
1414 * boot sequence interferes with bug checking; enable them later
1416 #define VIC_SET_GATE(cpi, vector) \
1417 set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
1418 #define QIC_SET_GATE(cpi, vector) \
1419 set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
1426 /* initialize the per cpu irq mask to all disabled */
1427 for(i = 0; i < NR_CPUS; i++)
1428 vic_irq_mask[i] = 0xFFFF;
1430 VIC_SET_GATE(VIC_CPI_LEVEL0, vic_cpi_interrupt);
1432 VIC_SET_GATE(VIC_SYS_INT, vic_sys_interrupt);
1433 VIC_SET_GATE(VIC_CMN_INT, vic_cmn_interrupt);
1435 QIC_SET_GATE(QIC_TIMER_CPI, qic_timer_interrupt);
1436 QIC_SET_GATE(QIC_INVALIDATE_CPI, qic_invalidate_interrupt);
1437 QIC_SET_GATE(QIC_RESCHEDULE_CPI, qic_reschedule_interrupt);
1438 QIC_SET_GATE(QIC_ENABLE_IRQ_CPI, qic_enable_irq_interrupt);
1439 QIC_SET_GATE(QIC_CALL_FUNCTION_CPI, qic_call_function_interrupt);
1442 /* now put the VIC descriptor into the first 48 IRQs
1444 * This is for later: first 16 correspond to PC IRQs; next 16
1445 * are Primary MC IRQs and final 16 are Secondary MC IRQs */
1446 for(i = 0; i < 48; i++)
1447 irq_desc[i].handler = &vic_irq_type;
1450 /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
1451 * processor to receive CPI */
1453 send_CPI(__u32 cpuset, __u8 cpi)
1456 __u32 quad_cpuset = (cpuset & voyager_quad_processors);
1458 if(cpi < VIC_START_FAKE_CPI) {
1459 /* fake CPI are only used for booting, so send to the
1460 * extended quads as well---Quads must be VIC booted */
1461 outb((__u8)(cpuset), VIC_CPI_Registers[cpi]);
1465 send_QIC_CPI(quad_cpuset, cpi);
1466 cpuset &= ~quad_cpuset;
1467 cpuset &= 0xff; /* only first 8 CPUs vaild for VIC CPI */
1470 for_each_online_cpu(cpu) {
1471 if(cpuset & (1<<cpu))
1472 set_bit(cpi, &vic_cpi_mailbox[cpu]);
1475 outb((__u8)cpuset, VIC_CPI_Registers[VIC_CPI_LEVEL0]);
1478 /* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
1479 * set the cache line to shared by reading it.
1481 * DON'T make this inline otherwise the cache line read will be
1485 ack_QIC_CPI(__u8 cpi) {
1486 __u8 cpu = hard_smp_processor_id();
1490 outb(1<<cpi, QIC_INTERRUPT_CLEAR1);
1491 return voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi;
1495 ack_special_QIC_CPI(__u8 cpi)
1499 outb(QIC_CMN_INT, QIC_INTERRUPT_CLEAR0);
1502 outb(QIC_SYS_INT, QIC_INTERRUPT_CLEAR0);
1505 /* also clear at the VIC, just in case (nop for non-extended proc) */
1509 /* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
1511 ack_VIC_CPI(__u8 cpi)
1513 #ifdef VOYAGER_DEBUG
1514 unsigned long flags;
1516 __u8 cpu = smp_processor_id();
1518 local_irq_save(flags);
1519 isr = vic_read_isr();
1520 if((isr & (1<<(cpi &7))) == 0) {
1521 printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu, cpi);
1524 /* send specific EOI; the two system interrupts have
1525 * bit 4 set for a separate vector but behave as the
1526 * corresponding 3 bit intr */
1527 outb_p(0x60|(cpi & 7),0x20);
1529 #ifdef VOYAGER_DEBUG
1530 if((vic_read_isr() & (1<<(cpi &7))) != 0) {
1531 printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu, cpi);
1533 local_irq_restore(flags);
1537 /* cribbed with thanks from irq.c */
1538 #define __byte(x,y) (((unsigned char *)&(y))[x])
1539 #define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
1540 #define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
1543 startup_vic_irq(unsigned int irq)
1545 enable_vic_irq(irq);
1550 /* The enable and disable routines. This is where we run into
1551 * conflicting architectural philosophy. Fundamentally, the voyager
1552 * architecture does not expect to have to disable interrupts globally
1553 * (the IRQ controllers belong to each CPU). The processor masquerade
1554 * which is used to start the system shouldn't be used in a running OS
1555 * since it will cause great confusion if two separate CPUs drive to
1556 * the same IRQ controller (I know, I've tried it).
1558 * The solution is a variant on the NCR lazy SPL design:
1560 * 1) To disable an interrupt, do nothing (other than set the
1561 * IRQ_DISABLED flag). This dares the interrupt actually to arrive.
1563 * 2) If the interrupt dares to come in, raise the local mask against
1564 * it (this will result in all the CPU masks being raised
1567 * 3) To enable the interrupt, lower the mask on the local CPU and
1568 * broadcast an Interrupt enable CPI which causes all other CPUs to
1569 * adjust their masks accordingly. */
1572 enable_vic_irq(unsigned int irq)
1574 /* linux doesn't to processor-irq affinity, so enable on
1575 * all CPUs we know about */
1576 int cpu = smp_processor_id(), real_cpu;
1577 __u16 mask = (1<<irq);
1578 __u32 processorList = 0;
1579 unsigned long flags;
1581 VDEBUG(("VOYAGER: enable_vic_irq(%d) CPU%d affinity 0x%lx\n",
1582 irq, cpu, cpu_irq_affinity[cpu]));
1583 spin_lock_irqsave(&vic_irq_lock, flags);
1584 for_each_online_cpu(real_cpu) {
1585 if(!(voyager_extended_vic_processors & (1<<real_cpu)))
1587 if(!(cpu_irq_affinity[real_cpu] & mask)) {
1588 /* irq has no affinity for this CPU, ignore */
1591 if(real_cpu == cpu) {
1592 enable_local_vic_irq(irq);
1594 else if(vic_irq_mask[real_cpu] & mask) {
1595 vic_irq_enable_mask[real_cpu] |= mask;
1596 processorList |= (1<<real_cpu);
1599 spin_unlock_irqrestore(&vic_irq_lock, flags);
1601 send_CPI(processorList, VIC_ENABLE_IRQ_CPI);
1605 disable_vic_irq(unsigned int irq)
1607 /* lazy disable, do nothing */
1611 enable_local_vic_irq(unsigned int irq)
1613 __u8 cpu = smp_processor_id();
1614 __u16 mask = ~(1 << irq);
1615 __u16 old_mask = vic_irq_mask[cpu];
1617 vic_irq_mask[cpu] &= mask;
1618 if(vic_irq_mask[cpu] == old_mask)
1621 VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
1625 outb_p(cached_A1(cpu),0xA1);
1629 outb_p(cached_21(cpu),0x21);
1635 disable_local_vic_irq(unsigned int irq)
1637 __u8 cpu = smp_processor_id();
1638 __u16 mask = (1 << irq);
1639 __u16 old_mask = vic_irq_mask[cpu];
1644 vic_irq_mask[cpu] |= mask;
1645 if(old_mask == vic_irq_mask[cpu])
1648 VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
1652 outb_p(cached_A1(cpu),0xA1);
1656 outb_p(cached_21(cpu),0x21);
1661 /* The VIC is level triggered, so the ack can only be issued after the
1662 * interrupt completes. However, we do Voyager lazy interrupt
1663 * handling here: It is an extremely expensive operation to mask an
1664 * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
1665 * this interrupt actually comes in, then we mask and ack here to push
1666 * the interrupt off to another CPU */
1668 before_handle_vic_irq(unsigned int irq)
1670 irq_desc_t *desc = irq_desc + irq;
1671 __u8 cpu = smp_processor_id();
1673 _raw_spin_lock(&vic_irq_lock);
1675 vic_intr_count[cpu]++;
1677 if(!(cpu_irq_affinity[cpu] & (1<<irq))) {
1678 /* The irq is not in our affinity mask, push it off
1679 * onto another CPU */
1680 VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d on cpu %d\n",
1682 disable_local_vic_irq(irq);
1683 /* set IRQ_INPROGRESS to prevent the handler in irq.c from
1684 * actually calling the interrupt routine */
1685 desc->status |= IRQ_REPLAY | IRQ_INPROGRESS;
1686 } else if(desc->status & IRQ_DISABLED) {
1687 /* Damn, the interrupt actually arrived, do the lazy
1688 * disable thing. The interrupt routine in irq.c will
1689 * not handle a IRQ_DISABLED interrupt, so nothing more
1690 * need be done here */
1691 VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
1693 disable_local_vic_irq(irq);
1694 desc->status |= IRQ_REPLAY;
1696 desc->status &= ~IRQ_REPLAY;
1699 _raw_spin_unlock(&vic_irq_lock);
1702 /* Finish the VIC interrupt: basically mask */
1704 after_handle_vic_irq(unsigned int irq)
1706 irq_desc_t *desc = irq_desc + irq;
1708 _raw_spin_lock(&vic_irq_lock);
1710 unsigned int status = desc->status & ~IRQ_INPROGRESS;
1711 #ifdef VOYAGER_DEBUG
1715 desc->status = status;
1716 if ((status & IRQ_DISABLED))
1717 disable_local_vic_irq(irq);
1718 #ifdef VOYAGER_DEBUG
1719 /* DEBUG: before we ack, check what's in progress */
1720 isr = vic_read_isr();
1721 if((isr & (1<<irq) && !(status & IRQ_REPLAY)) == 0) {
1723 __u8 cpu = smp_processor_id();
1725 int mask; /* Um... initialize me??? --RR */
1727 printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
1729 for_each_cpu(real_cpu, mask) {
1731 outb(VIC_CPU_MASQUERADE_ENABLE | real_cpu,
1733 isr = vic_read_isr();
1734 if(isr & (1<<irq)) {
1735 printk("VOYAGER SMP: CPU%d ack irq %d\n",
1739 outb(cpu, VIC_PROCESSOR_ID);
1742 #endif /* VOYAGER_DEBUG */
1743 /* as soon as we ack, the interrupt is eligible for
1744 * receipt by another CPU so everything must be in
1747 if(status & IRQ_REPLAY) {
1748 /* replay is set if we disable the interrupt
1749 * in the before_handle_vic_irq() routine, so
1750 * clear the in progress bit here to allow the
1751 * next CPU to handle this correctly */
1752 desc->status &= ~(IRQ_REPLAY | IRQ_INPROGRESS);
1754 #ifdef VOYAGER_DEBUG
1755 isr = vic_read_isr();
1756 if((isr & (1<<irq)) != 0)
1757 printk("VOYAGER SMP: after_handle_vic_irq() after ack irq=%d, isr=0x%x\n",
1759 #endif /* VOYAGER_DEBUG */
1761 _raw_spin_unlock(&vic_irq_lock);
1763 /* All code after this point is out of the main path - the IRQ
1764 * may be intercepted by another CPU if reasserted */
1768 /* Linux processor - interrupt affinity manipulations.
1770 * For each processor, we maintain a 32 bit irq affinity mask.
1771 * Initially it is set to all 1's so every processor accepts every
1772 * interrupt. In this call, we change the processor's affinity mask:
1774 * Change from enable to disable:
1776 * If the interrupt ever comes in to the processor, we will disable it
1777 * and ack it to push it off to another CPU, so just accept the mask here.
1779 * Change from disable to enable:
1781 * change the mask and then do an interrupt enable CPI to re-enable on
1782 * the selected processors */
1785 set_vic_irq_affinity(unsigned int irq, cpumask_t mask)
1787 /* Only extended processors handle interrupts */
1788 unsigned long real_mask;
1789 unsigned long irq_mask = 1 << irq;
1792 real_mask = cpus_addr(mask)[0] & voyager_extended_vic_processors;
1794 if(cpus_addr(mask)[0] == 0)
1795 /* can't have no cpu's to accept the interrupt -- extremely
1796 * bad things will happen */
1800 /* can't change the affinity of the timer IRQ. This
1801 * is due to the constraint in the voyager
1802 * architecture that the CPI also comes in on and IRQ
1803 * line and we have chosen IRQ0 for this. If you
1804 * raise the mask on this interrupt, the processor
1805 * will no-longer be able to accept VIC CPIs */
1809 /* You can only have 32 interrupts in a voyager system
1810 * (and 32 only if you have a secondary microchannel
1814 for_each_online_cpu(cpu) {
1815 unsigned long cpu_mask = 1 << cpu;
1817 if(cpu_mask & real_mask) {
1818 /* enable the interrupt for this cpu */
1819 cpu_irq_affinity[cpu] |= irq_mask;
1821 /* disable the interrupt for this cpu */
1822 cpu_irq_affinity[cpu] &= ~irq_mask;
1825 /* this is magic, we now have the correct affinity maps, so
1826 * enable the interrupt. This will send an enable CPI to
1827 * those cpu's who need to enable it in their local masks,
1828 * causing them to correct for the new affinity . If the
1829 * interrupt is currently globally disabled, it will simply be
1830 * disabled again as it comes in (voyager lazy disable). If
1831 * the affinity map is tightened to disable the interrupt on a
1832 * cpu, it will be pushed off when it comes in */
1833 enable_vic_irq(irq);
1837 ack_vic_irq(unsigned int irq)
1840 outb(0x62,0x20); /* Specific EOI to cascade */
1841 outb(0x60|(irq & 7),0xA0);
1843 outb(0x60 | (irq & 7),0x20);
1847 /* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
1848 * but are not vectored by it. This means that the 8259 mask must be
1849 * lowered to receive them */
1851 vic_enable_cpi(void)
1853 __u8 cpu = smp_processor_id();
1855 /* just take a copy of the current mask (nop for boot cpu) */
1856 vic_irq_mask[cpu] = vic_irq_mask[boot_cpu_id];
1858 enable_local_vic_irq(VIC_CPI_LEVEL0);
1859 enable_local_vic_irq(VIC_CPI_LEVEL1);
1860 /* for sys int and cmn int */
1861 enable_local_vic_irq(7);
1864 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
1865 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
1866 VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
1867 cpu, QIC_CPI_ENABLE));
1870 VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
1871 cpu, vic_irq_mask[cpu]));
1877 int old_cpu = smp_processor_id(), cpu;
1879 /* dump the interrupt masks of each processor */
1880 for_each_online_cpu(cpu) {
1881 __u16 imr, isr, irr;
1882 unsigned long flags;
1884 local_irq_save(flags);
1885 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
1886 imr = (inb(0xa1) << 8) | inb(0x21);
1888 irr = inb(0xa0) << 8;
1892 isr = inb(0xa0) << 8;
1895 outb(old_cpu, VIC_PROCESSOR_ID);
1896 local_irq_restore(flags);
1897 printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
1898 cpu, vic_irq_mask[cpu], imr, irr, isr);
1900 /* These lines are put in to try to unstick an un ack'd irq */
1903 for(irq=0; irq<16; irq++) {
1904 if(isr & (1<<irq)) {
1905 printk("\tCPU%d: ack irq %d\n",
1907 local_irq_save(flags);
1908 outb(VIC_CPU_MASQUERADE_ENABLE | cpu,
1911 outb(old_cpu, VIC_PROCESSOR_ID);
1912 local_irq_restore(flags);
1921 smp_voyager_power_off(void *dummy)
1923 if(smp_processor_id() == boot_cpu_id)
1924 voyager_power_off();
1926 smp_stop_cpu_function(NULL);
1930 smp_prepare_cpus(unsigned int max_cpus)
1932 /* FIXME: ignore max_cpus for now */
1936 void __devinit smp_prepare_boot_cpu(void)
1938 cpu_set(smp_processor_id(), cpu_online_map);
1939 cpu_set(smp_processor_id(), cpu_callout_map);
1943 __cpu_up(unsigned int cpu)
1945 /* This only works at boot for x86. See "rewrite" above. */
1946 if (cpu_isset(cpu, smp_commenced_mask))
1949 /* In case one didn't come up */
1950 if (!cpu_isset(cpu, cpu_callin_map))
1952 /* Unleash the CPU! */
1953 cpu_set(cpu, smp_commenced_mask);
1954 while (!cpu_isset(cpu, cpu_online_map))
1960 smp_cpus_done(unsigned int max_cpus)