1 /* -*- mode: c; c-basic-offset: 8 -*- */
3 /* Copyright (C) 1999,2001
5 * Author: J.E.J.Bottomley@HansenPartnership.com
7 * linux/arch/i386/kernel/voyager_smp.c
9 * This file provides all the same external entries as smp.c but uses
10 * the voyager hal to provide the functionality
12 #include <linux/config.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/mc146818rtc.h>
17 #include <linux/cache.h>
18 #include <linux/interrupt.h>
19 #include <linux/smp_lock.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/bootmem.h>
23 #include <linux/completion.h>
25 #include <asm/voyager.h>
28 #include <asm/pgalloc.h>
29 #include <asm/tlbflush.h>
31 #include <asm/arch_hooks.h>
33 #include <linux/irq.h>
37 /* TLB state -- visible externally, indexed physically */
38 DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0 };
40 /* CPU IRQ affinity -- set to all ones initially */
41 static unsigned long cpu_irq_affinity[NR_CPUS] __cacheline_aligned = { [0 ... NR_CPUS-1] = ~0UL };
43 /* Set when the idlers are all forked - Set in main.c but not actually
44 * used by any other parts of the kernel */
45 int smp_threads_ready = 0;
47 /* per CPU data structure (for /proc/cpuinfo et al), visible externally
48 * indexed physically */
49 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
51 /* physical ID of the CPU used to boot the system */
52 unsigned char boot_cpu_id;
54 /* The memory line addresses for the Quad CPIs */
55 struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS] __cacheline_aligned;
57 /* The masks for the Extended VIC processors, filled in by cat_init */
58 __u32 voyager_extended_vic_processors = 0;
60 /* Masks for the extended Quad processors which cannot be VIC booted */
61 __u32 voyager_allowed_boot_processors = 0;
63 /* The mask for the Quad Processors (both extended and non-extended) */
64 __u32 voyager_quad_processors = 0;
66 /* Total count of live CPUs, used in process.c to display
67 * the CPU information and in irq.c for the per CPU irq
68 * activity count. Finally exported by i386_ksyms.c */
69 static int voyager_extended_cpus = 1;
71 /* Have we found an SMP box - used by time.c to do the profiling
72 interrupt for timeslicing; do not set to 1 until the per CPU timer
73 interrupt is active */
74 int smp_found_config = 0;
76 /* Used for the invalidate map that's also checked in the spinlock */
77 static volatile unsigned long smp_invalidate_needed;
79 /* Bitmask of currently online CPUs - used by setup.c for
80 /proc/cpuinfo, visible externally but still physical */
81 cpumask_t cpu_online_map = CPU_MASK_NONE;
83 /* Bitmask of CPUs present in the system - exported by i386_syms.c, used
84 * by scheduler but indexed physically */
85 cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
87 /* estimate of time used to flush the SMP-local cache - used in
88 * processor affinity calculations */
89 cycles_t cacheflush_time = 0;
91 /* cache decay ticks for scheduler---a fairly useless quantity for the
92 voyager system with its odd affinity and huge L3 cache */
93 unsigned long cache_decay_ticks = 20;
96 /* The internal functions */
97 static void send_CPI(__u32 cpuset, __u8 cpi);
98 static void ack_CPI(__u8 cpi);
99 static int ack_QIC_CPI(__u8 cpi);
100 static void ack_special_QIC_CPI(__u8 cpi);
101 static void ack_VIC_CPI(__u8 cpi);
102 static void send_CPI_allbutself(__u8 cpi);
103 static void enable_vic_irq(unsigned int irq);
104 static void disable_vic_irq(unsigned int irq);
105 static unsigned int startup_vic_irq(unsigned int irq);
106 static void enable_local_vic_irq(unsigned int irq);
107 static void disable_local_vic_irq(unsigned int irq);
108 static void before_handle_vic_irq(unsigned int irq);
109 static void after_handle_vic_irq(unsigned int irq);
110 static void set_vic_irq_affinity(unsigned int irq, cpumask_t mask);
111 static void ack_vic_irq(unsigned int irq);
112 static void vic_enable_cpi(void);
113 static void do_boot_cpu(__u8 cpuid);
114 static void do_quad_bootstrap(void);
115 static inline void wrapper_smp_local_timer_interrupt(struct pt_regs *);
117 int hard_smp_processor_id(void);
119 /* Inline functions */
121 send_one_QIC_CPI(__u8 cpu, __u8 cpi)
123 voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi =
124 (smp_processor_id() << 16) + cpi;
128 send_QIC_CPI(__u32 cpuset, __u8 cpi)
132 for_each_online_cpu(cpu) {
133 if(cpuset & (1<<cpu)) {
135 if(!cpu_isset(cpu, cpu_online_map))
136 VDEBUG(("CPU%d sending cpi %d to CPU%d not in cpu_online_map\n", hard_smp_processor_id(), cpi, cpu));
138 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
144 send_one_CPI(__u8 cpu, __u8 cpi)
146 if(voyager_quad_processors & (1<<cpu))
147 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
149 send_CPI(1<<cpu, cpi);
153 send_CPI_allbutself(__u8 cpi)
155 __u8 cpu = smp_processor_id();
156 __u32 mask = cpus_addr(cpu_online_map)[0] & ~(1 << cpu);
163 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
164 return ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER);
168 is_cpu_extended(void)
170 __u8 cpu = hard_smp_processor_id();
172 return(voyager_extended_vic_processors & (1<<cpu));
176 is_cpu_vic_boot(void)
178 __u8 cpu = hard_smp_processor_id();
180 return(voyager_extended_vic_processors
181 & voyager_allowed_boot_processors & (1<<cpu));
189 case VIC_CPU_BOOT_CPI:
190 if(is_cpu_quad() && !is_cpu_vic_boot())
197 /* These are slightly strange. Even on the Quad card,
198 * They are vectored as VIC CPIs */
200 ack_special_QIC_CPI(cpi);
205 printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi);
210 /* local variables */
212 /* The VIC IRQ descriptors -- these look almost identical to the
213 * 8259 IRQs except that masks and things must be kept per processor
215 static struct hw_interrupt_type vic_irq_type = {
217 startup_vic_irq, /* startup */
218 disable_vic_irq, /* shutdown */
219 enable_vic_irq, /* enable */
220 disable_vic_irq, /* disable */
221 before_handle_vic_irq, /* ack */
222 after_handle_vic_irq, /* end */
223 set_vic_irq_affinity, /* affinity */
226 /* used to count up as CPUs are brought on line (starts at 0) */
227 static int cpucount = 0;
229 /* steal a page from the bottom of memory for the trampoline and
230 * squirrel its address away here. This will be in kernel virtual
232 static __u32 trampoline_base;
234 /* The per cpu profile stuff - used in smp_local_timer_interrupt */
235 static DEFINE_PER_CPU(int, prof_multiplier) = 1;
236 static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
237 static DEFINE_PER_CPU(int, prof_counter) = 1;
239 /* the map used to check if a CPU has booted */
240 static __u32 cpu_booted_map;
242 /* the synchronize flag used to hold all secondary CPUs spinning in
243 * a tight loop until the boot sequence is ready for them */
244 static cpumask_t smp_commenced_mask = CPU_MASK_NONE;
246 /* This is for the new dynamic CPU boot code */
247 cpumask_t cpu_callin_map = CPU_MASK_NONE;
248 cpumask_t cpu_callout_map = CPU_MASK_NONE;
250 /* The per processor IRQ masks (these are usually kept in sync) */
251 static __u16 vic_irq_mask[NR_CPUS] __cacheline_aligned;
253 /* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
254 static __u16 vic_irq_enable_mask[NR_CPUS] __cacheline_aligned = { 0 };
256 /* Lock for enable/disable of VIC interrupts */
257 static spinlock_t vic_irq_lock __cacheline_aligned = SPIN_LOCK_UNLOCKED;
259 /* The boot processor is correctly set up in PC mode when it
260 * comes up, but the secondaries need their master/slave 8259
261 * pairs initializing correctly */
263 /* Interrupt counters (per cpu) and total - used to try to
264 * even up the interrupt handling routines */
265 static long vic_intr_total = 0;
266 static long vic_intr_count[NR_CPUS] __cacheline_aligned = { 0 };
267 static unsigned long vic_tick[NR_CPUS] __cacheline_aligned = { 0 };
269 /* Since we can only use CPI0, we fake all the other CPIs */
270 static unsigned long vic_cpi_mailbox[NR_CPUS] __cacheline_aligned;
272 /* debugging routine to read the isr of the cpu's pic */
279 isr = inb(0xa0) << 8;
290 /* not a quad, no setup */
293 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
294 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
296 if(is_cpu_extended()) {
297 /* the QIC duplicate of the VIC base register */
298 outb(VIC_DEFAULT_CPI_BASE, QIC_VIC_CPI_BASE_REGISTER);
299 outb(QIC_DEFAULT_CPI_BASE, QIC_CPI_BASE_REGISTER);
301 /* FIXME: should set up the QIC timer and memory parity
302 * error vectors here */
309 outb(1, VIC_REDIRECT_REGISTER_1);
310 /* clear the claim registers for dynamic routing */
311 outb(0, VIC_CLAIM_REGISTER_0);
312 outb(0, VIC_CLAIM_REGISTER_1);
314 outb(0, VIC_PRIORITY_REGISTER);
315 /* Set the Primary and Secondary Microchannel vector
316 * bases to be the same as the ordinary interrupts
318 * FIXME: This would be more efficient using separate
320 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
321 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
322 /* Now initiallise the master PIC belonging to this CPU by
323 * sending the four ICWs */
325 /* ICW1: level triggered, ICW4 needed */
328 /* ICW2: vector base */
329 outb(FIRST_EXTERNAL_VECTOR, 0x21);
331 /* ICW3: slave at line 2 */
334 /* ICW4: 8086 mode */
337 /* now the same for the slave PIC */
339 /* ICW1: level trigger, ICW4 needed */
342 /* ICW2: slave vector base */
343 outb(FIRST_EXTERNAL_VECTOR + 8, 0xA1);
348 /* ICW4: 8086 mode */
353 do_quad_bootstrap(void)
355 if(is_cpu_quad() && is_cpu_vic_boot()) {
358 __u8 cpuid = hard_smp_processor_id();
360 local_irq_save(flags);
362 for(i = 0; i<4; i++) {
363 /* FIXME: this would be >>3 &0x7 on the 32 way */
364 if(((cpuid >> 2) & 0x03) == i)
365 /* don't lower our own mask! */
368 /* masquerade as local Quad CPU */
369 outb(QIC_CPUID_ENABLE | i, QIC_PROCESSOR_ID);
370 /* enable the startup CPI */
371 outb(QIC_BOOT_CPI_MASK, QIC_MASK_REGISTER1);
373 outb(0, QIC_PROCESSOR_ID);
375 local_irq_restore(flags);
380 /* Set up all the basic stuff: read the SMP config and make all the
381 * SMP information reflect only the boot cpu. All others will be
382 * brought on-line later. */
384 find_smp_config(void)
388 boot_cpu_id = hard_smp_processor_id();
390 printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id);
392 /* initialize the CPU structures (moved from smp_boot_cpus) */
393 for(i=0; i<NR_CPUS; i++) {
394 cpu_irq_affinity[i] = ~0;
396 cpu_online_map = cpumask_of_cpu(boot_cpu_id);
398 /* The boot CPU must be extended */
399 voyager_extended_vic_processors = 1<<boot_cpu_id;
400 /* initially, all of the first 8 cpu's can boot */
401 voyager_allowed_boot_processors = 0xff;
402 /* set up everything for just this CPU, we can alter
403 * this as we start the other CPUs later */
404 /* now get the CPU disposition from the extended CMOS */
405 cpus_addr(phys_cpu_present_map)[0] = voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK);
406 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8;
407 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 2) << 16;
408 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 3) << 24;
409 printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n", cpus_addr(phys_cpu_present_map)[0]);
410 /* Here we set up the VIC to enable SMP */
411 /* enable the CPIs by writing the base vector to their register */
412 outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER);
413 outb(1, VIC_REDIRECT_REGISTER_1);
414 /* set the claim registers for static routing --- Boot CPU gets
415 * all interrupts untill all other CPUs started */
416 outb(0xff, VIC_CLAIM_REGISTER_0);
417 outb(0xff, VIC_CLAIM_REGISTER_1);
418 /* Set the Primary and Secondary Microchannel vector
419 * bases to be the same as the ordinary interrupts
421 * FIXME: This would be more efficient using separate
423 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
424 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
426 /* Finally tell the firmware that we're driving */
427 outb(inb(VOYAGER_SUS_IN_CONTROL_PORT) | VOYAGER_IN_CONTROL_FLAG,
428 VOYAGER_SUS_IN_CONTROL_PORT);
430 current_thread_info()->cpu = boot_cpu_id;
434 * The bootstrap kernel entry code has set these up. Save them
435 * for a given CPU, id is physical */
437 smp_store_cpu_info(int id)
439 struct cpuinfo_x86 *c=&cpu_data[id];
446 /* set up the trampoline and return the physical address of the code */
448 setup_trampoline(void)
450 /* these two are global symbols in trampoline.S */
451 extern __u8 trampoline_end[];
452 extern __u8 trampoline_data[];
454 memcpy((__u8 *)trampoline_base, trampoline_data,
455 trampoline_end - trampoline_data);
456 return virt_to_phys((__u8 *)trampoline_base);
459 /* Routine initially called when a non-boot CPU is brought online */
461 start_secondary(void *unused)
463 __u8 cpuid = hard_smp_processor_id();
464 /* external functions not defined in the headers */
465 extern void calibrate_delay(void);
466 extern int cpu_idle(void);
470 /* OK, we're in the routine */
471 ack_CPI(VIC_CPU_BOOT_CPI);
473 /* setup the 8259 master slave pair belonging to this CPU ---
474 * we won't actually receive any until the boot CPU
475 * relinquishes it's static routing mask */
480 if(is_cpu_quad() && !is_cpu_vic_boot()) {
481 /* clear the boot CPI */
484 dummy = voyager_quad_cpi_addr[cpuid]->qic_cpi[VIC_CPU_BOOT_CPI].cpi;
485 printk("read dummy %d\n", dummy);
488 /* lower the mask to receive CPIs */
491 VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid));
493 /* enable interrupts */
496 /* get our bogomips */
499 /* save our processor parameters */
500 smp_store_cpu_info(cpuid);
502 /* if we're a quad, we may need to bootstrap other CPUs */
505 /* FIXME: this is rather a poor hack to prevent the CPU
506 * activating softirqs while it's supposed to be waiting for
507 * permission to proceed. Without this, the new per CPU stuff
508 * in the softirqs will fail */
510 cpu_set(cpuid, cpu_callin_map);
512 /* signal that we're done */
515 while (!cpu_isset(cpuid, smp_commenced_mask))
521 cpu_set(cpuid, cpu_online_map);
527 /* Routine to kick start the given CPU and wait for it to report ready
528 * (or timeout in startup). When this routine returns, the requested
529 * CPU is either fully running and configured or known to be dead.
531 * We call this routine sequentially 1 CPU at a time, so no need for
535 do_boot_cpu(__u8 cpu)
537 struct task_struct *idle;
540 int quad_boot = (1<<cpu) & voyager_quad_processors
541 & ~( voyager_extended_vic_processors
542 & voyager_allowed_boot_processors);
544 /* For the 486, we can't use the 4Mb page table trick, so
545 * must map a region of memory */
548 unsigned long *page_table_copies = (unsigned long *)
549 __get_free_page(GFP_KERNEL);
551 pgd_t orig_swapper_pg_dir0;
553 /* This is an area in head.S which was used to set up the
554 * initial kernel stack. We need to alter this to give the
555 * booting CPU a new stack (taken from its idle process) */
560 /* This is the format of the CPI IDT gate (in real mode) which
561 * we're hijacking to boot the CPU */
570 __u32 *hijack_vector;
571 __u32 start_phys_address = setup_trampoline();
573 /* There's a clever trick to this: The linux trampoline is
574 * compiled to begin at absolute location zero, so make the
575 * address zero but have the data segment selector compensate
576 * for the actual address */
577 hijack_source.idt.Offset = start_phys_address & 0x000F;
578 hijack_source.idt.Segment = (start_phys_address >> 4) & 0xFFFF;
581 idle = fork_idle(cpu);
583 panic("failed fork for CPU%d", cpu);
584 idle->thread.eip = (unsigned long) start_secondary;
585 /* init_tasks (in sched.c) is indexed logically */
586 stack_start.esp = (void *) idle->thread.esp;
590 /* Note: Don't modify initial ss override */
591 VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu,
592 (unsigned long)hijack_source.val, hijack_source.idt.Segment,
593 hijack_source.idt.Offset, stack_start.esp));
594 /* set the original swapper_pg_dir[0] to map 0 to 4Mb transparently
595 * (so that the booting CPU can find start_32 */
596 orig_swapper_pg_dir0 = swapper_pg_dir[0];
598 if(page_table_copies == NULL)
599 panic("No free memory for 486 page tables\n");
600 for(i = 0; i < PAGE_SIZE/sizeof(unsigned long); i++)
601 page_table_copies[i] = (i * PAGE_SIZE)
602 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
604 ((unsigned long *)swapper_pg_dir)[0] =
605 ((virt_to_phys(page_table_copies)) & PAGE_MASK)
606 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
608 ((unsigned long *)swapper_pg_dir)[0] =
609 (virt_to_phys(pg0) & PAGE_MASK)
610 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
614 printk("CPU %d: non extended Quad boot\n", cpu);
615 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + QIC_DEFAULT_CPI_BASE)*4);
616 *hijack_vector = hijack_source.val;
618 printk("CPU%d: extended VIC boot\n", cpu);
619 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE)*4);
620 *hijack_vector = hijack_source.val;
621 /* VIC errata, may also receive interrupt at this address */
622 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI + VIC_DEFAULT_CPI_BASE)*4);
623 *hijack_vector = hijack_source.val;
625 /* All non-boot CPUs start with interrupts fully masked. Need
626 * to lower the mask of the CPI we're about to send. We do
627 * this in the VIC by masquerading as the processor we're
628 * about to boot and lowering its interrupt mask */
629 local_irq_save(flags);
631 send_one_QIC_CPI(cpu, VIC_CPU_BOOT_CPI);
633 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
634 /* here we're altering registers belonging to `cpu' */
636 outb(VIC_BOOT_INTERRUPT_MASK, 0x21);
637 /* now go back to our original identity */
638 outb(boot_cpu_id, VIC_PROCESSOR_ID);
640 /* and boot the CPU */
642 send_CPI((1<<cpu), VIC_CPU_BOOT_CPI);
645 local_irq_restore(flags);
647 /* now wait for it to become ready (or timeout) */
648 for(timeout = 0; timeout < 50000; timeout++) {
653 /* reset the page table */
654 swapper_pg_dir[0] = orig_swapper_pg_dir0;
657 free_page((unsigned long)page_table_copies);
660 if (cpu_booted_map) {
661 VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
662 cpu, smp_processor_id()));
664 printk("CPU%d: ", cpu);
665 print_cpu_info(&cpu_data[cpu]);
667 cpu_set(cpu, cpu_callout_map);
670 printk("CPU%d FAILED TO BOOT: ", cpu);
671 if (*((volatile unsigned char *)phys_to_virt(start_phys_address))==0xA5)
674 printk("Not responding.\n");
685 /* CAT BUS initialisation must be done after the memory */
686 /* FIXME: The L4 has a catbus too, it just needs to be
687 * accessed in a totally different way */
688 if(voyager_level == 5) {
691 /* now that the cat has probed the Voyager System Bus, sanity
692 * check the cpu map */
693 if( ((voyager_quad_processors | voyager_extended_vic_processors)
694 & cpus_addr(phys_cpu_present_map)[0]) != cpus_addr(phys_cpu_present_map)[0]) {
696 printk("\n\n***WARNING*** Sanity check of CPU present map FAILED\n");
698 } else if(voyager_level == 4)
699 voyager_extended_vic_processors = cpus_addr(phys_cpu_present_map)[0];
701 /* this sets up the idle task to run on the current cpu */
702 voyager_extended_cpus = 1;
703 /* Remove the global_irq_holder setting, it triggers a BUG() on
704 * schedule at the moment */
705 //global_irq_holder = boot_cpu_id;
707 /* FIXME: Need to do something about this but currently only works
708 * on CPUs with a tsc which none of mine have.
709 smp_tune_scheduling();
711 smp_store_cpu_info(boot_cpu_id);
712 printk("CPU%d: ", boot_cpu_id);
713 print_cpu_info(&cpu_data[boot_cpu_id]);
716 /* booting on a Quad CPU */
717 printk("VOYAGER SMP: Boot CPU is Quad\n");
722 /* enable our own CPIs */
725 cpu_set(boot_cpu_id, cpu_online_map);
726 cpu_set(boot_cpu_id, cpu_callout_map);
728 /* loop over all the extended VIC CPUs and boot them. The
729 * Quad CPUs must be bootstrapped by their extended VIC cpu */
730 for(i = 0; i < NR_CPUS; i++) {
731 if(i == boot_cpu_id || !cpu_isset(i, phys_cpu_present_map))
734 /* This udelay seems to be needed for the Quad boots
735 * don't remove unless you know what you're doing */
738 /* we could compute the total bogomips here, but why bother?,
739 * Code added from smpboot.c */
741 unsigned long bogosum = 0;
742 for (i = 0; i < NR_CPUS; i++)
743 if (cpu_isset(i, cpu_online_map))
744 bogosum += cpu_data[i].loops_per_jiffy;
745 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
748 (bogosum/(5000/HZ))%100);
750 voyager_extended_cpus = hweight32(voyager_extended_vic_processors);
751 printk("VOYAGER: Extended (interrupt handling CPUs): %d, non-extended: %d\n", voyager_extended_cpus, num_booting_cpus() - voyager_extended_cpus);
752 /* that's it, switch to symmetric mode */
753 outb(0, VIC_PRIORITY_REGISTER);
754 outb(0, VIC_CLAIM_REGISTER_0);
755 outb(0, VIC_CLAIM_REGISTER_1);
757 VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
760 /* Reload the secondary CPUs task structure (this function does not
763 initialize_secondary(void)
767 set_current(hard_get_current());
771 * We don't actually need to load the full TSS,
772 * basically just the stack pointer and the eip.
779 :"r" (current->thread.esp),"r" (current->thread.eip));
782 /* handle a Voyager SYS_INT -- If we don't, the base board will
785 * System interrupts occur because some problem was detected on the
786 * various busses. To find out what you have to probe all the
787 * hardware via the CAT bus. FIXME: At the moment we do nothing. */
789 smp_vic_sys_interrupt(void)
791 ack_CPI(VIC_SYS_INT);
792 printk("Voyager SYSTEM INTERRUPT\n");
795 /* Handle a voyager CMN_INT; These interrupts occur either because of
796 * a system status change or because a single bit memory error
797 * occurred. FIXME: At the moment, ignore all this. */
799 smp_vic_cmn_interrupt(void)
801 static __u8 in_cmn_int = 0;
802 static spinlock_t cmn_int_lock = SPIN_LOCK_UNLOCKED;
804 /* common ints are broadcast, so make sure we only do this once */
805 _raw_spin_lock(&cmn_int_lock);
810 _raw_spin_unlock(&cmn_int_lock);
812 VDEBUG(("Voyager COMMON INTERRUPT\n"));
814 if(voyager_level == 5)
815 voyager_cat_do_common_interrupt();
817 _raw_spin_lock(&cmn_int_lock);
820 _raw_spin_unlock(&cmn_int_lock);
821 ack_CPI(VIC_CMN_INT);
825 * Reschedule call back. Nothing to do, all the work is done
826 * automatically when we return from the interrupt. */
828 smp_reschedule_interrupt(void)
833 static struct mm_struct * flush_mm;
834 static unsigned long flush_va;
835 static spinlock_t tlbstate_lock = SPIN_LOCK_UNLOCKED;
836 #define FLUSH_ALL 0xffffffff
839 * We cannot call mmdrop() because we are in interrupt context,
840 * instead update mm->cpu_vm_mask.
842 * We need to reload %cr3 since the page tables may be going
843 * away from under us..
846 leave_mm (unsigned long cpu)
848 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
850 cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
851 load_cr3(swapper_pg_dir);
856 * Invalidate call-back
859 smp_invalidate_interrupt(void)
861 __u8 cpu = smp_processor_id();
863 if (!test_bit(cpu, &smp_invalidate_needed))
865 /* This will flood messages. Don't uncomment unless you see
866 * Problems with cross cpu invalidation
867 VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
868 smp_processor_id()));
871 if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
872 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
873 if (flush_va == FLUSH_ALL)
876 __flush_tlb_one(flush_va);
880 smp_mb__before_clear_bit();
881 clear_bit(cpu, &smp_invalidate_needed);
882 smp_mb__after_clear_bit();
885 /* All the new flush operations for 2.4 */
888 /* This routine is called with a physical cpu mask */
890 flush_tlb_others (unsigned long cpumask, struct mm_struct *mm,
897 if ((cpumask & cpus_addr(cpu_online_map)[0]) != cpumask)
899 if (cpumask & (1 << smp_processor_id()))
904 spin_lock(&tlbstate_lock);
908 atomic_set_mask(cpumask, &smp_invalidate_needed);
910 * We have to send the CPI only to
913 send_CPI(cpumask, VIC_INVALIDATE_CPI);
915 while (smp_invalidate_needed) {
918 printk("***WARNING*** Stuck doing invalidate CPI (CPU%d)\n", smp_processor_id());
923 /* Uncomment only to debug invalidation problems
924 VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
929 spin_unlock(&tlbstate_lock);
933 flush_tlb_current_task(void)
935 struct mm_struct *mm = current->mm;
936 unsigned long cpu_mask;
940 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
943 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
950 flush_tlb_mm (struct mm_struct * mm)
952 unsigned long cpu_mask;
956 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
958 if (current->active_mm == mm) {
962 leave_mm(smp_processor_id());
965 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
970 void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
972 struct mm_struct *mm = vma->vm_mm;
973 unsigned long cpu_mask;
977 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
978 if (current->active_mm == mm) {
982 leave_mm(smp_processor_id());
986 flush_tlb_others(cpu_mask, mm, va);
991 /* enable the requested IRQs */
993 smp_enable_irq_interrupt(void)
996 __u8 cpu = get_cpu();
998 VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu,
999 vic_irq_enable_mask[cpu]));
1001 spin_lock(&vic_irq_lock);
1002 for(irq = 0; irq < 16; irq++) {
1003 if(vic_irq_enable_mask[cpu] & (1<<irq))
1004 enable_local_vic_irq(irq);
1006 vic_irq_enable_mask[cpu] = 0;
1007 spin_unlock(&vic_irq_lock);
1009 put_cpu_no_resched();
1013 * CPU halt call-back
1016 smp_stop_cpu_function(void *dummy)
1018 VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
1019 cpu_clear(smp_processor_id(), cpu_online_map);
1020 local_irq_disable();
1025 static spinlock_t call_lock = SPIN_LOCK_UNLOCKED;
1027 struct call_data_struct {
1028 void (*func) (void *info);
1030 volatile unsigned long started;
1031 volatile unsigned long finished;
1035 static struct call_data_struct * call_data;
1037 /* execute a thread on a new CPU. The function to be called must be
1038 * previously set up. This is used to schedule a function for
1039 * execution on all CPU's - set up the function then broadcast a
1040 * function_interrupt CPI to come here on each CPU */
1042 smp_call_function_interrupt(void)
1044 void (*func) (void *info) = call_data->func;
1045 void *info = call_data->info;
1046 /* must take copy of wait because call_data may be replaced
1047 * unless the function is waiting for us to finish */
1048 int wait = call_data->wait;
1049 __u8 cpu = smp_processor_id();
1052 * Notify initiating CPU that I've grabbed the data and am
1053 * about to execute the function
1056 if(!test_and_clear_bit(cpu, &call_data->started)) {
1057 /* If the bit wasn't set, this could be a replay */
1058 printk(KERN_WARNING "VOYAGER SMP: CPU %d received call funtion with no call pending\n", cpu);
1062 * At this point the info structure may be out of scope unless wait==1
1069 clear_bit(cpu, &call_data->finished);
1073 /* Call this function on all CPUs using the function_interrupt above
1074 <func> The function to run. This must be fast and non-blocking.
1075 <info> An arbitrary pointer to pass to the function.
1076 <retry> If true, keep retrying until ready.
1077 <wait> If true, wait until function has completed on other CPUs.
1078 [RETURNS] 0 on success, else a negative status code. Does not return until
1079 remote CPUs are nearly ready to execute <<func>> or are or have executed.
1082 smp_call_function (void (*func) (void *info), void *info, int retry,
1085 struct call_data_struct data;
1086 __u32 mask = cpus_addr(cpu_online_map)[0];
1088 mask &= ~(1<<smp_processor_id());
1093 /* Can deadlock when called with interrupts disabled */
1094 WARN_ON(irqs_disabled());
1098 data.started = mask;
1101 data.finished = mask;
1103 spin_lock(&call_lock);
1106 /* Send a message to all other CPUs and wait for them to respond */
1107 send_CPI_allbutself(VIC_CALL_FUNCTION_CPI);
1109 /* Wait for response */
1110 while (data.started)
1114 while (data.finished)
1117 spin_unlock(&call_lock);
1122 /* Sorry about the name. In an APIC based system, the APICs
1123 * themselves are programmed to send a timer interrupt. This is used
1124 * by linux to reschedule the processor. Voyager doesn't have this,
1125 * so we use the system clock to interrupt one processor, which in
1126 * turn, broadcasts a timer CPI to all the others --- we receive that
1127 * CPI here. We don't use this actually for counting so losing
1128 * ticks doesn't matter
1130 * FIXME: For those CPU's which actually have a local APIC, we could
1131 * try to use it to trigger this interrupt instead of having to
1132 * broadcast the timer tick. Unfortunately, all my pentium DYADs have
1133 * no local APIC, so I can't do this
1135 * This function is currently a placeholder and is unused in the code */
1137 smp_apic_timer_interrupt(struct pt_regs regs)
1139 wrapper_smp_local_timer_interrupt(®s);
1142 /* All of the QUAD interrupt GATES */
1144 smp_qic_timer_interrupt(struct pt_regs regs)
1146 ack_QIC_CPI(QIC_TIMER_CPI);
1147 wrapper_smp_local_timer_interrupt(®s);
1151 smp_qic_invalidate_interrupt(void)
1153 ack_QIC_CPI(QIC_INVALIDATE_CPI);
1154 smp_invalidate_interrupt();
1158 smp_qic_reschedule_interrupt(void)
1160 ack_QIC_CPI(QIC_RESCHEDULE_CPI);
1161 smp_reschedule_interrupt();
1165 smp_qic_enable_irq_interrupt(void)
1167 ack_QIC_CPI(QIC_ENABLE_IRQ_CPI);
1168 smp_enable_irq_interrupt();
1172 smp_qic_call_function_interrupt(void)
1174 ack_QIC_CPI(QIC_CALL_FUNCTION_CPI);
1175 smp_call_function_interrupt();
1179 smp_vic_cpi_interrupt(struct pt_regs regs)
1181 __u8 cpu = smp_processor_id();
1184 ack_QIC_CPI(VIC_CPI_LEVEL0);
1186 ack_VIC_CPI(VIC_CPI_LEVEL0);
1188 if(test_and_clear_bit(VIC_TIMER_CPI, &vic_cpi_mailbox[cpu]))
1189 wrapper_smp_local_timer_interrupt(®s);
1190 if(test_and_clear_bit(VIC_INVALIDATE_CPI, &vic_cpi_mailbox[cpu]))
1191 smp_invalidate_interrupt();
1192 if(test_and_clear_bit(VIC_RESCHEDULE_CPI, &vic_cpi_mailbox[cpu]))
1193 smp_reschedule_interrupt();
1194 if(test_and_clear_bit(VIC_ENABLE_IRQ_CPI, &vic_cpi_mailbox[cpu]))
1195 smp_enable_irq_interrupt();
1196 if(test_and_clear_bit(VIC_CALL_FUNCTION_CPI, &vic_cpi_mailbox[cpu]))
1197 smp_call_function_interrupt();
1201 do_flush_tlb_all(void* info)
1203 unsigned long cpu = smp_processor_id();
1206 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
1211 /* flush the TLB of every active CPU in the system */
1215 on_each_cpu(do_flush_tlb_all, 0, 1, 1);
1218 /* used to set up the trampoline for other CPUs when the memory manager
1221 smp_alloc_memory(void)
1223 trampoline_base = (__u32)alloc_bootmem_low_pages(PAGE_SIZE);
1224 if(__pa(trampoline_base) >= 0x93000)
1228 /* send a reschedule CPI to one CPU by physical CPU number*/
1230 smp_send_reschedule(int cpu)
1232 send_one_CPI(cpu, VIC_RESCHEDULE_CPI);
1237 hard_smp_processor_id(void)
1240 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
1241 if((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER)
1242 return cpumask & 0x1F;
1244 for(i = 0; i < 8; i++) {
1245 if(cpumask & (1<<i))
1248 printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask);
1252 /* broadcast a halt to all other CPUs */
1256 smp_call_function(smp_stop_cpu_function, NULL, 1, 1);
1259 /* this function is triggered in time.c when a clock tick fires
1260 * we need to re-broadcast the tick to all CPUs */
1262 smp_vic_timer_interrupt(struct pt_regs *regs)
1264 send_CPI_allbutself(VIC_TIMER_CPI);
1265 smp_local_timer_interrupt(regs);
1269 wrapper_smp_local_timer_interrupt(struct pt_regs *regs)
1272 smp_local_timer_interrupt(regs);
1276 /* local (per CPU) timer interrupt. It does both profiling and
1277 * process statistics/rescheduling.
1279 * We do profiling in every local tick, statistics/rescheduling
1280 * happen only every 'profiling multiplier' ticks. The default
1281 * multiplier is 1 and it can be changed by writing the new multiplier
1282 * value into /proc/profile.
1285 smp_local_timer_interrupt(struct pt_regs * regs)
1287 int cpu = smp_processor_id();
1290 profile_tick(CPU_PROFILING, regs);
1291 if (--per_cpu(prof_counter, cpu) <= 0) {
1293 * The multiplier may have changed since the last time we got
1294 * to this point as a result of the user writing to
1295 * /proc/profile. In this case we need to adjust the APIC
1296 * timer accordingly.
1298 * Interrupts are already masked off at this point.
1300 per_cpu(prof_counter,cpu) = per_cpu(prof_multiplier, cpu);
1301 if (per_cpu(prof_counter, cpu) !=
1302 per_cpu(prof_old_multiplier, cpu)) {
1303 /* FIXME: need to update the vic timer tick here */
1304 per_cpu(prof_old_multiplier, cpu) =
1305 per_cpu(prof_counter, cpu);
1308 update_process_times(user_mode(regs));
1311 if( ((1<<cpu) & voyager_extended_vic_processors) == 0)
1312 /* only extended VIC processors participate in
1313 * interrupt distribution */
1317 * We take the 'long' return path, and there every subsystem
1318 * grabs the apropriate locks (kernel lock/ irq lock).
1320 * we might want to decouple profiling from the 'long path',
1321 * and do the profiling totally in assembly.
1323 * Currently this isn't too much of an issue (performance wise),
1324 * we can take more than 100K local irqs per second on a 100 MHz P5.
1327 if((++vic_tick[cpu] & 0x7) != 0)
1329 /* get here every 16 ticks (about every 1/6 of a second) */
1331 /* Change our priority to give someone else a chance at getting
1332 * the IRQ. The algorithm goes like this:
1334 * In the VIC, the dynamically routed interrupt is always
1335 * handled by the lowest priority eligible (i.e. receiving
1336 * interrupts) CPU. If >1 eligible CPUs are equal lowest, the
1337 * lowest processor number gets it.
1339 * The priority of a CPU is controlled by a special per-CPU
1340 * VIC priority register which is 3 bits wide 0 being lowest
1341 * and 7 highest priority..
1343 * Therefore we subtract the average number of interrupts from
1344 * the number we've fielded. If this number is negative, we
1345 * lower the activity count and if it is positive, we raise
1348 * I'm afraid this still leads to odd looking interrupt counts:
1349 * the totals are all roughly equal, but the individual ones
1350 * look rather skewed.
1352 * FIXME: This algorithm is total crap when mixed with SMP
1353 * affinity code since we now try to even up the interrupt
1354 * counts when an affinity binding is keeping them on a
1356 weight = (vic_intr_count[cpu]*voyager_extended_cpus
1357 - vic_intr_total) >> 4;
1364 outb((__u8)weight, VIC_PRIORITY_REGISTER);
1366 #ifdef VOYAGER_DEBUG
1367 if((vic_tick[cpu] & 0xFFF) == 0) {
1368 /* print this message roughly every 25 secs */
1369 printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
1370 cpu, vic_tick[cpu], weight);
1375 /* setup the profiling timer */
1377 setup_profiling_timer(unsigned int multiplier)
1385 * Set the new multiplier for each CPU. CPUs don't start using the
1386 * new values until the next timer interrupt in which they do process
1389 for (i = 0; i < NR_CPUS; ++i)
1390 per_cpu(prof_multiplier, i) = multiplier;
1396 /* The CPIs are handled in the per cpu 8259s, so they must be
1397 * enabled to be received: FIX: enabling the CPIs in the early
1398 * boot sequence interferes with bug checking; enable them later
1400 #define VIC_SET_GATE(cpi, vector) \
1401 set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
1402 #define QIC_SET_GATE(cpi, vector) \
1403 set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
1410 /* initialize the per cpu irq mask to all disabled */
1411 for(i = 0; i < NR_CPUS; i++)
1412 vic_irq_mask[i] = 0xFFFF;
1414 VIC_SET_GATE(VIC_CPI_LEVEL0, vic_cpi_interrupt);
1416 VIC_SET_GATE(VIC_SYS_INT, vic_sys_interrupt);
1417 VIC_SET_GATE(VIC_CMN_INT, vic_cmn_interrupt);
1419 QIC_SET_GATE(QIC_TIMER_CPI, qic_timer_interrupt);
1420 QIC_SET_GATE(QIC_INVALIDATE_CPI, qic_invalidate_interrupt);
1421 QIC_SET_GATE(QIC_RESCHEDULE_CPI, qic_reschedule_interrupt);
1422 QIC_SET_GATE(QIC_ENABLE_IRQ_CPI, qic_enable_irq_interrupt);
1423 QIC_SET_GATE(QIC_CALL_FUNCTION_CPI, qic_call_function_interrupt);
1426 /* now put the VIC descriptor into the first 48 IRQs
1428 * This is for later: first 16 correspond to PC IRQs; next 16
1429 * are Primary MC IRQs and final 16 are Secondary MC IRQs */
1430 for(i = 0; i < 48; i++)
1431 irq_desc[i].handler = &vic_irq_type;
1434 /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
1435 * processor to receive CPI */
1437 send_CPI(__u32 cpuset, __u8 cpi)
1440 __u32 quad_cpuset = (cpuset & voyager_quad_processors);
1442 if(cpi < VIC_START_FAKE_CPI) {
1443 /* fake CPI are only used for booting, so send to the
1444 * extended quads as well---Quads must be VIC booted */
1445 outb((__u8)(cpuset), VIC_CPI_Registers[cpi]);
1449 send_QIC_CPI(quad_cpuset, cpi);
1450 cpuset &= ~quad_cpuset;
1451 cpuset &= 0xff; /* only first 8 CPUs vaild for VIC CPI */
1454 for_each_online_cpu(cpu) {
1455 if(cpuset & (1<<cpu))
1456 set_bit(cpi, &vic_cpi_mailbox[cpu]);
1459 outb((__u8)cpuset, VIC_CPI_Registers[VIC_CPI_LEVEL0]);
1462 /* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
1463 * set the cache line to shared by reading it.
1465 * DON'T make this inline otherwise the cache line read will be
1469 ack_QIC_CPI(__u8 cpi) {
1470 __u8 cpu = hard_smp_processor_id();
1474 outb(1<<cpi, QIC_INTERRUPT_CLEAR1);
1475 return voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi;
1479 ack_special_QIC_CPI(__u8 cpi)
1483 outb(QIC_CMN_INT, QIC_INTERRUPT_CLEAR0);
1486 outb(QIC_SYS_INT, QIC_INTERRUPT_CLEAR0);
1489 /* also clear at the VIC, just in case (nop for non-extended proc) */
1493 /* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
1495 ack_VIC_CPI(__u8 cpi)
1497 #ifdef VOYAGER_DEBUG
1498 unsigned long flags;
1500 __u8 cpu = smp_processor_id();
1502 local_irq_save(flags);
1503 isr = vic_read_isr();
1504 if((isr & (1<<(cpi &7))) == 0) {
1505 printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu, cpi);
1508 /* send specific EOI; the two system interrupts have
1509 * bit 4 set for a separate vector but behave as the
1510 * corresponding 3 bit intr */
1511 outb_p(0x60|(cpi & 7),0x20);
1513 #ifdef VOYAGER_DEBUG
1514 if((vic_read_isr() & (1<<(cpi &7))) != 0) {
1515 printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu, cpi);
1517 local_irq_restore(flags);
1521 /* cribbed with thanks from irq.c */
1522 #define __byte(x,y) (((unsigned char *)&(y))[x])
1523 #define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
1524 #define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
1527 startup_vic_irq(unsigned int irq)
1529 enable_vic_irq(irq);
1534 /* The enable and disable routines. This is where we run into
1535 * conflicting architectural philosophy. Fundamentally, the voyager
1536 * architecture does not expect to have to disable interrupts globally
1537 * (the IRQ controllers belong to each CPU). The processor masquerade
1538 * which is used to start the system shouldn't be used in a running OS
1539 * since it will cause great confusion if two separate CPUs drive to
1540 * the same IRQ controller (I know, I've tried it).
1542 * The solution is a variant on the NCR lazy SPL design:
1544 * 1) To disable an interrupt, do nothing (other than set the
1545 * IRQ_DISABLED flag). This dares the interrupt actually to arrive.
1547 * 2) If the interrupt dares to come in, raise the local mask against
1548 * it (this will result in all the CPU masks being raised
1551 * 3) To enable the interrupt, lower the mask on the local CPU and
1552 * broadcast an Interrupt enable CPI which causes all other CPUs to
1553 * adjust their masks accordingly. */
1556 enable_vic_irq(unsigned int irq)
1558 /* linux doesn't to processor-irq affinity, so enable on
1559 * all CPUs we know about */
1560 int cpu = smp_processor_id(), real_cpu;
1561 __u16 mask = (1<<irq);
1562 __u32 processorList = 0;
1563 unsigned long flags;
1565 VDEBUG(("VOYAGER: enable_vic_irq(%d) CPU%d affinity 0x%lx\n",
1566 irq, cpu, cpu_irq_affinity[cpu]));
1567 spin_lock_irqsave(&vic_irq_lock, flags);
1568 for_each_online_cpu(real_cpu) {
1569 if(!(voyager_extended_vic_processors & (1<<real_cpu)))
1571 if(!(cpu_irq_affinity[real_cpu] & mask)) {
1572 /* irq has no affinity for this CPU, ignore */
1575 if(real_cpu == cpu) {
1576 enable_local_vic_irq(irq);
1578 else if(vic_irq_mask[real_cpu] & mask) {
1579 vic_irq_enable_mask[real_cpu] |= mask;
1580 processorList |= (1<<real_cpu);
1583 spin_unlock_irqrestore(&vic_irq_lock, flags);
1585 send_CPI(processorList, VIC_ENABLE_IRQ_CPI);
1589 disable_vic_irq(unsigned int irq)
1591 /* lazy disable, do nothing */
1595 enable_local_vic_irq(unsigned int irq)
1597 __u8 cpu = smp_processor_id();
1598 __u16 mask = ~(1 << irq);
1599 __u16 old_mask = vic_irq_mask[cpu];
1601 vic_irq_mask[cpu] &= mask;
1602 if(vic_irq_mask[cpu] == old_mask)
1605 VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
1609 outb_p(cached_A1(cpu),0xA1);
1613 outb_p(cached_21(cpu),0x21);
1619 disable_local_vic_irq(unsigned int irq)
1621 __u8 cpu = smp_processor_id();
1622 __u16 mask = (1 << irq);
1623 __u16 old_mask = vic_irq_mask[cpu];
1628 vic_irq_mask[cpu] |= mask;
1629 if(old_mask == vic_irq_mask[cpu])
1632 VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
1636 outb_p(cached_A1(cpu),0xA1);
1640 outb_p(cached_21(cpu),0x21);
1645 /* The VIC is level triggered, so the ack can only be issued after the
1646 * interrupt completes. However, we do Voyager lazy interrupt
1647 * handling here: It is an extremely expensive operation to mask an
1648 * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
1649 * this interrupt actually comes in, then we mask and ack here to push
1650 * the interrupt off to another CPU */
1652 before_handle_vic_irq(unsigned int irq)
1654 irq_desc_t *desc = irq_desc + irq;
1655 __u8 cpu = smp_processor_id();
1657 _raw_spin_lock(&vic_irq_lock);
1659 vic_intr_count[cpu]++;
1661 if(!(cpu_irq_affinity[cpu] & (1<<irq))) {
1662 /* The irq is not in our affinity mask, push it off
1663 * onto another CPU */
1664 VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d on cpu %d\n",
1666 disable_local_vic_irq(irq);
1667 /* set IRQ_INPROGRESS to prevent the handler in irq.c from
1668 * actually calling the interrupt routine */
1669 desc->status |= IRQ_REPLAY | IRQ_INPROGRESS;
1670 } else if(desc->status & IRQ_DISABLED) {
1671 /* Damn, the interrupt actually arrived, do the lazy
1672 * disable thing. The interrupt routine in irq.c will
1673 * not handle a IRQ_DISABLED interrupt, so nothing more
1674 * need be done here */
1675 VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
1677 disable_local_vic_irq(irq);
1678 desc->status |= IRQ_REPLAY;
1680 desc->status &= ~IRQ_REPLAY;
1683 _raw_spin_unlock(&vic_irq_lock);
1686 /* Finish the VIC interrupt: basically mask */
1688 after_handle_vic_irq(unsigned int irq)
1690 irq_desc_t *desc = irq_desc + irq;
1692 _raw_spin_lock(&vic_irq_lock);
1694 unsigned int status = desc->status & ~IRQ_INPROGRESS;
1695 #ifdef VOYAGER_DEBUG
1699 desc->status = status;
1700 if ((status & IRQ_DISABLED))
1701 disable_local_vic_irq(irq);
1702 #ifdef VOYAGER_DEBUG
1703 /* DEBUG: before we ack, check what's in progress */
1704 isr = vic_read_isr();
1705 if((isr & (1<<irq) && !(status & IRQ_REPLAY)) == 0) {
1707 __u8 cpu = smp_processor_id();
1709 int mask; /* Um... initialize me??? --RR */
1711 printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
1713 for_each_cpu(real_cpu, mask) {
1715 outb(VIC_CPU_MASQUERADE_ENABLE | real_cpu,
1717 isr = vic_read_isr();
1718 if(isr & (1<<irq)) {
1719 printk("VOYAGER SMP: CPU%d ack irq %d\n",
1723 outb(cpu, VIC_PROCESSOR_ID);
1726 #endif /* VOYAGER_DEBUG */
1727 /* as soon as we ack, the interrupt is eligible for
1728 * receipt by another CPU so everything must be in
1731 if(status & IRQ_REPLAY) {
1732 /* replay is set if we disable the interrupt
1733 * in the before_handle_vic_irq() routine, so
1734 * clear the in progress bit here to allow the
1735 * next CPU to handle this correctly */
1736 desc->status &= ~(IRQ_REPLAY | IRQ_INPROGRESS);
1738 #ifdef VOYAGER_DEBUG
1739 isr = vic_read_isr();
1740 if((isr & (1<<irq)) != 0)
1741 printk("VOYAGER SMP: after_handle_vic_irq() after ack irq=%d, isr=0x%x\n",
1743 #endif /* VOYAGER_DEBUG */
1745 _raw_spin_unlock(&vic_irq_lock);
1747 /* All code after this point is out of the main path - the IRQ
1748 * may be intercepted by another CPU if reasserted */
1752 /* Linux processor - interrupt affinity manipulations.
1754 * For each processor, we maintain a 32 bit irq affinity mask.
1755 * Initially it is set to all 1's so every processor accepts every
1756 * interrupt. In this call, we change the processor's affinity mask:
1758 * Change from enable to disable:
1760 * If the interrupt ever comes in to the processor, we will disable it
1761 * and ack it to push it off to another CPU, so just accept the mask here.
1763 * Change from disable to enable:
1765 * change the mask and then do an interrupt enable CPI to re-enable on
1766 * the selected processors */
1769 set_vic_irq_affinity(unsigned int irq, cpumask_t mask)
1771 /* Only extended processors handle interrupts */
1772 unsigned long real_mask;
1773 unsigned long irq_mask = 1 << irq;
1776 real_mask = cpus_addr(mask)[0] & voyager_extended_vic_processors;
1778 if(cpus_addr(mask)[0] == 0)
1779 /* can't have no cpu's to accept the interrupt -- extremely
1780 * bad things will happen */
1784 /* can't change the affinity of the timer IRQ. This
1785 * is due to the constraint in the voyager
1786 * architecture that the CPI also comes in on and IRQ
1787 * line and we have chosen IRQ0 for this. If you
1788 * raise the mask on this interrupt, the processor
1789 * will no-longer be able to accept VIC CPIs */
1793 /* You can only have 32 interrupts in a voyager system
1794 * (and 32 only if you have a secondary microchannel
1798 for_each_online_cpu(cpu) {
1799 unsigned long cpu_mask = 1 << cpu;
1801 if(cpu_mask & real_mask) {
1802 /* enable the interrupt for this cpu */
1803 cpu_irq_affinity[cpu] |= irq_mask;
1805 /* disable the interrupt for this cpu */
1806 cpu_irq_affinity[cpu] &= ~irq_mask;
1809 /* this is magic, we now have the correct affinity maps, so
1810 * enable the interrupt. This will send an enable CPI to
1811 * those cpu's who need to enable it in their local masks,
1812 * causing them to correct for the new affinity . If the
1813 * interrupt is currently globally disabled, it will simply be
1814 * disabled again as it comes in (voyager lazy disable). If
1815 * the affinity map is tightened to disable the interrupt on a
1816 * cpu, it will be pushed off when it comes in */
1817 enable_vic_irq(irq);
1821 ack_vic_irq(unsigned int irq)
1824 outb(0x62,0x20); /* Specific EOI to cascade */
1825 outb(0x60|(irq & 7),0xA0);
1827 outb(0x60 | (irq & 7),0x20);
1831 /* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
1832 * but are not vectored by it. This means that the 8259 mask must be
1833 * lowered to receive them */
1835 vic_enable_cpi(void)
1837 __u8 cpu = smp_processor_id();
1839 /* just take a copy of the current mask (nop for boot cpu) */
1840 vic_irq_mask[cpu] = vic_irq_mask[boot_cpu_id];
1842 enable_local_vic_irq(VIC_CPI_LEVEL0);
1843 enable_local_vic_irq(VIC_CPI_LEVEL1);
1844 /* for sys int and cmn int */
1845 enable_local_vic_irq(7);
1848 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
1849 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
1850 VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
1851 cpu, QIC_CPI_ENABLE));
1854 VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
1855 cpu, vic_irq_mask[cpu]));
1861 int old_cpu = smp_processor_id(), cpu;
1863 /* dump the interrupt masks of each processor */
1864 for_each_online_cpu(cpu) {
1865 __u16 imr, isr, irr;
1866 unsigned long flags;
1868 local_irq_save(flags);
1869 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
1870 imr = (inb(0xa1) << 8) | inb(0x21);
1872 irr = inb(0xa0) << 8;
1876 isr = inb(0xa0) << 8;
1879 outb(old_cpu, VIC_PROCESSOR_ID);
1880 local_irq_restore(flags);
1881 printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
1882 cpu, vic_irq_mask[cpu], imr, irr, isr);
1884 /* These lines are put in to try to unstick an un ack'd irq */
1887 for(irq=0; irq<16; irq++) {
1888 if(isr & (1<<irq)) {
1889 printk("\tCPU%d: ack irq %d\n",
1891 local_irq_save(flags);
1892 outb(VIC_CPU_MASQUERADE_ENABLE | cpu,
1895 outb(old_cpu, VIC_PROCESSOR_ID);
1896 local_irq_restore(flags);
1905 smp_voyager_power_off(void *dummy)
1907 if(smp_processor_id() == boot_cpu_id)
1908 voyager_power_off();
1910 smp_stop_cpu_function(NULL);
1914 smp_prepare_cpus(unsigned int max_cpus)
1916 /* FIXME: ignore max_cpus for now */
1920 void __devinit smp_prepare_boot_cpu(void)
1922 cpu_set(smp_processor_id(), cpu_online_map);
1923 cpu_set(smp_processor_id(), cpu_callout_map);
1927 __cpu_up(unsigned int cpu)
1929 /* This only works at boot for x86. See "rewrite" above. */
1930 if (cpu_isset(cpu, smp_commenced_mask))
1933 /* In case one didn't come up */
1934 if (!cpu_isset(cpu, cpu_callin_map))
1936 /* Unleash the CPU! */
1937 cpu_set(cpu, smp_commenced_mask);
1938 while (!cpu_isset(cpu, cpu_online_map))
1944 smp_cpus_done(unsigned int max_cpus)