2 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
6 #include <linux/init.h>
10 static void __devinit pci_fixup_i450nx(struct pci_dev *d)
13 * i450NX -- Find and scan all secondary buses on all PXB's.
18 printk(KERN_WARNING "PCI: Searching for i450NX host bridges on %s\n", pci_name(d));
20 for(pxb=0; pxb<2; pxb++) {
21 pci_read_config_byte(d, reg++, &busno);
22 pci_read_config_byte(d, reg++, &suba);
23 pci_read_config_byte(d, reg++, &subb);
24 DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
26 pci_scan_bus(busno, &pci_root_ops, NULL); /* Bus A */
28 pci_scan_bus(suba+1, &pci_root_ops, NULL); /* Bus B */
30 pcibios_last_bus = -1;
33 static void __devinit pci_fixup_i450gx(struct pci_dev *d)
36 * i450GX and i450KX -- Find and scan all secondary buses.
37 * (called separately for each PCI bridge found)
40 pci_read_config_byte(d, 0x4a, &busno);
41 printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", pci_name(d), busno);
42 pci_scan_bus(busno, &pci_root_ops, NULL);
43 pcibios_last_bus = -1;
46 static void __devinit pci_fixup_umc_ide(struct pci_dev *d)
49 * UM8886BF IDE controller sets region type bits incorrectly,
50 * therefore they look like memory despite of them being I/O.
54 printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", pci_name(d));
56 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
59 static void __devinit pci_fixup_ncr53c810(struct pci_dev *d)
62 * NCR 53C810 returns class code 0 (at least on some systems).
63 * Fix class to be PCI_CLASS_STORAGE_SCSI
66 printk(KERN_WARNING "PCI: fixing NCR 53C810 class code for %s\n", pci_name(d));
67 d->class = PCI_CLASS_STORAGE_SCSI << 8;
71 static void __devinit pci_fixup_ide_bases(struct pci_dev *d)
76 * PCI IDE controllers use non-standard I/O port decoding, respect it.
78 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
80 DBG("PCI: IDE base address fixup for %s\n", pci_name(d));
82 struct resource *r = &d->resource[i];
83 if ((r->start & ~0x80) == 0x374) {
90 static void __devinit pci_fixup_ide_trash(struct pci_dev *d)
95 * Runs the fixup only for the first IDE controller
96 * (Shai Fultheim - shai@ftcon.com)
98 static int called = 0;
104 * There exist PCI IDE controllers which have utter garbage
105 * in first four base registers. Ignore that.
107 DBG("PCI: IDE base address trash cleared for %s\n", pci_name(d));
109 d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
112 static void __devinit pci_fixup_latency(struct pci_dev *d)
115 * SiS 5597 and 5598 chipsets require latency timer set to
116 * at most 32 to avoid lockups.
118 DBG("PCI: Setting max latency to 32\n");
119 pcibios_max_latency = 32;
122 static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d)
125 * PIIX4 ACPI device: hardwired IRQ9
131 * Addresses issues with problems in the memory write queue timer in
132 * certain VIA Northbridges. This bugfix is per VIA's specifications,
133 * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
134 * to trigger a bug in its integrated ProSavage video card, which
135 * causes screen corruption. We only clear bits 6 and 7 for that chipset,
136 * until VIA can provide us with definitive information on why screen
137 * corruption occurs, and what exactly those bits do.
139 * VIA 8363,8622,8361 Northbridges:
140 * - bits 5, 6, 7 at offset 0x55 need to be turned off
141 * VIA 8367 (KT266x) Northbridges:
142 * - bits 5, 6, 7 at offset 0x95 need to be turned off
143 * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
144 * - bits 6, 7 at offset 0x55 need to be turned off
147 #define VIA_8363_KL133_REVISION_ID 0x81
148 #define VIA_8363_KM133_REVISION_ID 0x84
150 static void __devinit pci_fixup_via_northbridge_bug(struct pci_dev *d)
155 int mask = 0x1f; /* clear bits 5, 6, 7 by default */
157 pci_read_config_byte(d, PCI_REVISION_ID, &revision);
159 if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
160 /* fix pci bus latency issues resulted by NB bios error
161 it appears on bug free^Wreduced kt266x's bios forces
162 NB latency to zero */
163 pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
165 where = 0x95; /* the memory write queue timer register is
166 different for the KT266x's: 0x95 not 0x55 */
167 } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
168 (revision == VIA_8363_KL133_REVISION_ID ||
169 revision == VIA_8363_KM133_REVISION_ID)) {
170 mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
171 causes screen corruption on the KL133/KM133 */
174 pci_read_config_byte(d, where, &v);
176 printk(KERN_WARNING "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
177 d->device, revision, where, v, mask, v & mask);
179 pci_write_config_byte(d, where, v);
184 * For some reasons Intel decided that certain parts of their
185 * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
186 * while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
187 * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
188 * to Intel terminology. These devices do forward all addresses from
189 * system to PCI bus no matter what are their window settings, so they are
190 * "transparent" (or subtractive decoding) from programmers point of view.
192 static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev)
194 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
195 (dev->device & 0xff00) == 0x2400)
196 dev->transparent = 1;
200 * Fixup for C1 Halt Disconnect problem on nForce2 systems.
202 * From information provided by "Allen Martin" <AMartin@nvidia.com>:
204 * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle
205 * sequence. Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns.
206 * This allows the state-machine and timer to return to a proper state within
207 * 80 ns of the CONNECT and probe appearing together. Since the CPU will not
208 * issue another HALT within 80 ns of the initial HALT, the failure condition
211 static void __init pci_fixup_nforce2(struct pci_dev *dev)
216 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
219 * Chip Old value New value
220 * C17 0x1F0FFF01 0x1F01FF01
221 * C18D 0x9F0FFF01 0x9F01FF01
223 * Northbridge chip version may be determined by
224 * reading the PCI revision ID (0xC1 or greater is C18D).
226 fixed_val = rev < 0xC1 ? 0x1F01FF01 : 0x9F01FF01;
228 pci_read_config_dword(dev, 0x6c, &val);
229 if (val != fixed_val) {
230 printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n");
231 pci_write_config_dword(dev, 0x6c, fixed_val);
235 struct pci_fixup pcibios_fixups[] = {
237 .pass = PCI_FIXUP_HEADER,
238 .vendor = PCI_VENDOR_ID_INTEL,
239 .device = PCI_DEVICE_ID_INTEL_82451NX,
240 .hook = pci_fixup_i450nx
243 .pass = PCI_FIXUP_HEADER,
244 .vendor = PCI_VENDOR_ID_INTEL,
245 .device = PCI_DEVICE_ID_INTEL_82454GX,
246 .hook = pci_fixup_i450gx
249 .pass = PCI_FIXUP_HEADER,
250 .vendor = PCI_VENDOR_ID_UMC,
251 .device = PCI_DEVICE_ID_UMC_UM8886BF,
252 .hook = pci_fixup_umc_ide
255 .pass = PCI_FIXUP_HEADER,
256 .vendor = PCI_VENDOR_ID_SI,
257 .device = PCI_DEVICE_ID_SI_5513,
258 .hook = pci_fixup_ide_trash
261 .pass = PCI_FIXUP_HEADER,
262 .vendor = PCI_ANY_ID,
263 .device = PCI_ANY_ID,
264 .hook = pci_fixup_ide_bases
267 .pass = PCI_FIXUP_HEADER,
268 .vendor = PCI_VENDOR_ID_SI,
269 .device = PCI_DEVICE_ID_SI_5597,
270 .hook = pci_fixup_latency
273 .pass = PCI_FIXUP_HEADER,
274 .vendor = PCI_VENDOR_ID_SI,
275 .device = PCI_DEVICE_ID_SI_5598,
276 .hook = pci_fixup_latency
279 .pass = PCI_FIXUP_HEADER,
280 .vendor = PCI_VENDOR_ID_INTEL,
281 .device = PCI_DEVICE_ID_INTEL_82371AB_3,
282 .hook = pci_fixup_piix4_acpi
285 .pass = PCI_FIXUP_HEADER,
286 .vendor = PCI_VENDOR_ID_INTEL,
287 .device = PCI_DEVICE_ID_INTEL_82801CA_10,
288 .hook = pci_fixup_ide_trash
291 .pass = PCI_FIXUP_HEADER,
292 .vendor = PCI_VENDOR_ID_INTEL,
293 .device = PCI_DEVICE_ID_INTEL_82801CA_11,
294 .hook = pci_fixup_ide_trash
297 .pass = PCI_FIXUP_HEADER,
298 .vendor = PCI_VENDOR_ID_INTEL,
299 .device = PCI_DEVICE_ID_INTEL_82801DB_9,
300 .hook = pci_fixup_ide_trash
303 .pass = PCI_FIXUP_HEADER,
304 .vendor = PCI_VENDOR_ID_VIA,
305 .device = PCI_DEVICE_ID_VIA_8363_0,
306 .hook = pci_fixup_via_northbridge_bug
309 .pass = PCI_FIXUP_HEADER,
310 .vendor = PCI_VENDOR_ID_VIA,
311 .device = PCI_DEVICE_ID_VIA_8622,
312 .hook = pci_fixup_via_northbridge_bug
315 .pass = PCI_FIXUP_HEADER,
316 .vendor = PCI_VENDOR_ID_VIA,
317 .device = PCI_DEVICE_ID_VIA_8361,
318 .hook = pci_fixup_via_northbridge_bug
321 .pass = PCI_FIXUP_HEADER,
322 .vendor = PCI_VENDOR_ID_VIA,
323 .device = PCI_DEVICE_ID_VIA_8367_0,
324 .hook = pci_fixup_via_northbridge_bug
327 .pass = PCI_FIXUP_HEADER,
328 .vendor = PCI_VENDOR_ID_NCR,
329 .device = PCI_DEVICE_ID_NCR_53C810,
330 .hook = pci_fixup_ncr53c810
333 .pass = PCI_FIXUP_HEADER,
334 .vendor = PCI_VENDOR_ID_INTEL,
335 .device = PCI_ANY_ID,
336 .hook = pci_fixup_transparent_bridge
339 .pass = PCI_FIXUP_HEADER,
340 .vendor = PCI_VENDOR_ID_NVIDIA,
341 .device = PCI_DEVICE_ID_NVIDIA_NFORCE2,
342 .hook = pci_fixup_nforce2