2 * Low-Level PCI Support for PC -- Routing of Interrupts
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
7 #include <linux/types.h>
8 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/interrupt.h>
13 #include <linux/dmi.h>
16 #include <asm/io_apic.h>
17 #include <linux/irq.h>
18 #include <linux/acpi.h>
22 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
23 #define PIRQ_VERSION 0x0100
25 static int broken_hp_bios_irq9;
26 static int acer_tm360_irqrouting;
28 static struct irq_routing_table *pirq_table;
30 static int pirq_enable_irq(struct pci_dev *dev);
33 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
34 * Avoid using: 13, 14 and 15 (FP error and IDE).
35 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
37 unsigned int pcibios_irq_mask = 0xfff8;
39 static int pirq_penalty[16] = {
40 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
41 0, 0, 0, 0, 1000, 100000, 100000, 100000
47 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
48 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new);
51 struct irq_router_handler {
53 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
56 int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL;
57 void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL;
60 * Check passed address for the PCI IRQ Routing Table signature
61 * and perform checksum verification.
64 static inline struct irq_routing_table * pirq_check_routing_table(u8 *addr)
66 struct irq_routing_table *rt;
70 rt = (struct irq_routing_table *) addr;
71 if (rt->signature != PIRQ_SIGNATURE ||
72 rt->version != PIRQ_VERSION ||
74 rt->size < sizeof(struct irq_routing_table))
77 for (i=0; i < rt->size; i++)
80 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n", rt);
89 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
92 static struct irq_routing_table * __init pirq_find_routing_table(void)
95 struct irq_routing_table *rt;
98 if (!is_initial_xendomain())
101 if (pirq_table_addr) {
102 rt = pirq_check_routing_table((u8 *) isa_bus_to_virt(pirq_table_addr));
105 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n");
107 for(addr = (u8 *) isa_bus_to_virt(0xf0000); addr < (u8 *) isa_bus_to_virt(0x100000); addr += 16) {
108 rt = pirq_check_routing_table(addr);
117 * If we have a IRQ routing table, use it to search for peer host
118 * bridges. It's a gross hack, but since there are no other known
119 * ways how to get a list of buses, we have to go this way.
122 static void __init pirq_peer_trick(void)
124 struct irq_routing_table *rt = pirq_table;
129 memset(busmap, 0, sizeof(busmap));
130 for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
135 DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
137 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
143 for(i = 1; i < 256; i++) {
144 if (!busmap[i] || pci_find_bus(0, i))
146 if (pci_scan_bus(i, &pci_root_ops, NULL))
147 printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
149 pcibios_last_bus = -1;
153 * Code for querying and setting of IRQ routes on various interrupt routers.
156 void eisa_set_level_irq(unsigned int irq)
158 unsigned char mask = 1 << (irq & 7);
159 unsigned int port = 0x4d0 + (irq >> 3);
161 static u16 eisa_irq_mask;
163 if (irq >= 16 || (1 << irq) & eisa_irq_mask)
166 eisa_irq_mask |= (1 << irq);
167 printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq);
170 DBG(KERN_DEBUG " -> edge");
171 outb(val | mask, port);
176 * Common IRQ routing practice: nybbles in config space,
177 * offset by some magic constant.
179 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
182 unsigned reg = offset + (nr >> 1);
184 pci_read_config_byte(router, reg, &x);
185 return (nr & 1) ? (x >> 4) : (x & 0xf);
188 static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val)
191 unsigned reg = offset + (nr >> 1);
193 pci_read_config_byte(router, reg, &x);
194 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
195 pci_write_config_byte(router, reg, x);
199 * ALI pirq entries are damn ugly, and completely undocumented.
200 * This has been figured out from pirq tables, and it's not a pretty
203 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
205 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
207 return irqmap[read_config_nybble(router, 0x48, pirq-1)];
210 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
212 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
213 unsigned int val = irqmap[irq];
216 write_config_nybble(router, 0x48, pirq-1, val);
223 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
224 * just a pointer to the config space.
226 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
230 pci_read_config_byte(router, pirq, &x);
231 return (x < 16) ? x : 0;
234 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
236 pci_write_config_byte(router, pirq, irq);
241 * The VIA pirq rules are nibble-based, like ALI,
242 * but without the ugly irq number munging.
243 * However, PIRQD is in the upper instead of lower 4 bits.
245 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
247 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
250 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
252 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
257 * The VIA pirq rules are nibble-based, like ALI,
258 * but without the ugly irq number munging.
259 * However, for 82C586, nibble map is different .
261 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
263 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
264 return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
267 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
269 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
270 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
275 * ITE 8330G pirq rules are nibble-based
276 * FIXME: pirqmap may be { 1, 0, 3, 2 },
277 * 2+3 are both mapped to irq 9 on my system
279 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
281 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
282 return read_config_nybble(router,0x43, pirqmap[pirq-1]);
285 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
287 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
288 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
293 * OPTI: high four bits are nibble pointer..
294 * I wonder what the low bits do?
296 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
298 return read_config_nybble(router, 0xb8, pirq >> 4);
301 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
303 write_config_nybble(router, 0xb8, pirq >> 4, irq);
308 * Cyrix: nibble offset 0x5C
309 * 0x5C bits 7:4 is INTB bits 3:0 is INTA
310 * 0x5D bits 7:4 is INTD bits 3:0 is INTC
312 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
314 return read_config_nybble(router, 0x5C, (pirq-1)^1);
317 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
319 write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
324 * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
325 * We have to deal with the following issues here:
326 * - vendors have different ideas about the meaning of link values
327 * - some onboard devices (integrated in the chipset) have special
328 * links and are thus routed differently (i.e. not via PCI INTA-INTD)
329 * - different revision of the router have a different layout for
330 * the routing registers, particularly for the onchip devices
332 * For all routing registers the common thing is we have one byte
333 * per routeable link which is defined as:
334 * bit 7 IRQ mapping enabled (0) or disabled (1)
335 * bits [6:4] reserved (sometimes used for onchip devices)
336 * bits [3:0] IRQ to map to
337 * allowed: 3-7, 9-12, 14-15
338 * reserved: 0, 1, 2, 8, 13
340 * The config-space registers located at 0x41/0x42/0x43/0x44 are
341 * always used to route the normal PCI INT A/B/C/D respectively.
342 * Apparently there are systems implementing PCI routing table using
343 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
344 * We try our best to handle both link mappings.
346 * Currently (2003-05-21) it appears most SiS chipsets follow the
347 * definition of routing registers from the SiS-5595 southbridge.
348 * According to the SiS 5595 datasheets the revision id's of the
349 * router (ISA-bridge) should be 0x01 or 0xb0.
351 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
352 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
353 * They seem to work with the current routing code. However there is
354 * some concern because of the two USB-OHCI HCs (original SiS 5595
355 * had only one). YMMV.
357 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
360 * bits [6:5] must be written 01
361 * bit 4 channel-select primary (0), secondary (1)
364 * bit 6 OHCI function disabled (0), enabled (1)
366 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
368 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
370 * We support USBIRQ (in addition to INTA-INTD) and keep the
371 * IDE, ACPI and DAQ routing untouched as set by the BIOS.
373 * Currently the only reported exception is the new SiS 65x chipset
374 * which includes the SiS 69x southbridge. Here we have the 85C503
375 * router revision 0x04 and there are changes in the register layout
376 * mostly related to the different USB HCs with USB 2.0 support.
378 * Onchip routing for router rev-id 0x04 (try-and-error observation)
380 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
381 * bit 6-4 are probably unused, not like 5595
384 #define PIRQ_SIS_IRQ_MASK 0x0f
385 #define PIRQ_SIS_IRQ_DISABLE 0x80
386 #define PIRQ_SIS_USB_ENABLE 0x40
388 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
394 if (reg >= 0x01 && reg <= 0x04)
396 pci_read_config_byte(router, reg, &x);
397 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
400 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
406 if (reg >= 0x01 && reg <= 0x04)
408 pci_read_config_byte(router, reg, &x);
409 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
410 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
411 pci_write_config_byte(router, reg, x);
417 * VLSI: nibble offset 0x74 - educated guess due to routing table and
418 * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
419 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
420 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
421 * for the busbridge to the docking station.
424 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
427 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
430 return read_config_nybble(router, 0x74, pirq-1);
433 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
436 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
439 write_config_nybble(router, 0x74, pirq-1, irq);
444 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
445 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
446 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
447 * register is a straight binary coding of desired PIC IRQ (low nibble).
449 * The 'link' value in the PIRQ table is already in the correct format
450 * for the Index register. There are some special index values:
451 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
452 * and 0x03 for SMBus.
454 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
457 return inb(0xc01) & 0xf;
460 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
467 /* Support for AMD756 PCI IRQ Routing
468 * Jhon H. Caicedo <jhcaiced@osso.org.co>
469 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
470 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
471 * The AMD756 pirq rules are nibble-based
472 * offset 0x56 0-3 PIRQA 4-7 PIRQB
473 * offset 0x57 0-3 PIRQC 4-7 PIRQD
475 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
481 irq = read_config_nybble(router, 0x56, pirq - 1);
483 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n",
484 dev->vendor, dev->device, pirq, irq);
488 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
490 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
491 dev->vendor, dev->device, pirq, irq);
494 write_config_nybble(router, 0x56, pirq - 1, irq);
499 #ifdef CONFIG_PCI_BIOS
501 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
503 struct pci_dev *bridge;
504 int pin = pci_get_interrupt_pin(dev, &bridge);
505 return pcibios_set_irq_routing(bridge, pin, irq);
510 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
512 static struct pci_device_id __initdata pirq_440gx[] = {
513 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
514 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
518 /* 440GX has a proprietary PIRQ router -- don't use it */
519 if (pci_dev_present(pirq_440gx))
524 case PCI_DEVICE_ID_INTEL_82371FB_0:
525 case PCI_DEVICE_ID_INTEL_82371SB_0:
526 case PCI_DEVICE_ID_INTEL_82371AB_0:
527 case PCI_DEVICE_ID_INTEL_82371MX:
528 case PCI_DEVICE_ID_INTEL_82443MX_0:
529 case PCI_DEVICE_ID_INTEL_82801AA_0:
530 case PCI_DEVICE_ID_INTEL_82801AB_0:
531 case PCI_DEVICE_ID_INTEL_82801BA_0:
532 case PCI_DEVICE_ID_INTEL_82801BA_10:
533 case PCI_DEVICE_ID_INTEL_82801CA_0:
534 case PCI_DEVICE_ID_INTEL_82801CA_12:
535 case PCI_DEVICE_ID_INTEL_82801DB_0:
536 case PCI_DEVICE_ID_INTEL_82801E_0:
537 case PCI_DEVICE_ID_INTEL_82801EB_0:
538 case PCI_DEVICE_ID_INTEL_ESB_1:
539 case PCI_DEVICE_ID_INTEL_ICH6_0:
540 case PCI_DEVICE_ID_INTEL_ICH6_1:
541 case PCI_DEVICE_ID_INTEL_ICH7_0:
542 case PCI_DEVICE_ID_INTEL_ICH7_1:
543 case PCI_DEVICE_ID_INTEL_ICH7_30:
544 case PCI_DEVICE_ID_INTEL_ICH7_31:
545 case PCI_DEVICE_ID_INTEL_ESB2_0:
546 case PCI_DEVICE_ID_INTEL_ICH8_0:
547 case PCI_DEVICE_ID_INTEL_ICH8_1:
548 case PCI_DEVICE_ID_INTEL_ICH8_2:
549 case PCI_DEVICE_ID_INTEL_ICH8_3:
550 case PCI_DEVICE_ID_INTEL_ICH8_4:
551 r->name = "PIIX/ICH";
552 r->get = pirq_piix_get;
553 r->set = pirq_piix_set;
559 static __init int via_router_probe(struct irq_router *r,
560 struct pci_dev *router, u16 device)
562 /* FIXME: We should move some of the quirk fixup stuff here */
565 * work arounds for some buggy BIOSes
567 if (device == PCI_DEVICE_ID_VIA_82C586_0) {
568 switch(router->device) {
569 case PCI_DEVICE_ID_VIA_82C686:
571 * Asus k7m bios wrongly reports 82C686A
574 device = PCI_DEVICE_ID_VIA_82C686;
576 case PCI_DEVICE_ID_VIA_8235:
578 * Asus a7v-x bios wrongly reports 8235
581 device = PCI_DEVICE_ID_VIA_8235;
587 case PCI_DEVICE_ID_VIA_82C586_0:
589 r->get = pirq_via586_get;
590 r->set = pirq_via586_set;
592 case PCI_DEVICE_ID_VIA_82C596:
593 case PCI_DEVICE_ID_VIA_82C686:
594 case PCI_DEVICE_ID_VIA_8231:
595 case PCI_DEVICE_ID_VIA_8233A:
596 case PCI_DEVICE_ID_VIA_8235:
597 case PCI_DEVICE_ID_VIA_8237:
598 /* FIXME: add new ones for 8233/5 */
600 r->get = pirq_via_get;
601 r->set = pirq_via_set;
607 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
611 case PCI_DEVICE_ID_VLSI_82C534:
612 r->name = "VLSI 82C534";
613 r->get = pirq_vlsi_get;
614 r->set = pirq_vlsi_set;
621 static __init int serverworks_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
625 case PCI_DEVICE_ID_SERVERWORKS_OSB4:
626 case PCI_DEVICE_ID_SERVERWORKS_CSB5:
627 r->name = "ServerWorks";
628 r->get = pirq_serverworks_get;
629 r->set = pirq_serverworks_set;
635 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
637 if (device != PCI_DEVICE_ID_SI_503)
641 r->get = pirq_sis_get;
642 r->set = pirq_sis_set;
646 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
650 case PCI_DEVICE_ID_CYRIX_5520:
652 r->get = pirq_cyrix_get;
653 r->set = pirq_cyrix_set;
659 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
663 case PCI_DEVICE_ID_OPTI_82C700:
665 r->get = pirq_opti_get;
666 r->set = pirq_opti_set;
672 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
676 case PCI_DEVICE_ID_ITE_IT8330G_0:
678 r->get = pirq_ite_get;
679 r->set = pirq_ite_set;
685 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
689 case PCI_DEVICE_ID_AL_M1533:
690 case PCI_DEVICE_ID_AL_M1563:
691 printk(KERN_DEBUG "PCI: Using ALI IRQ Router\n");
693 r->get = pirq_ali_get;
694 r->set = pirq_ali_set;
700 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
704 case PCI_DEVICE_ID_AMD_VIPER_740B:
707 case PCI_DEVICE_ID_AMD_VIPER_7413:
710 case PCI_DEVICE_ID_AMD_VIPER_7443:
716 r->get = pirq_amd756_get;
717 r->set = pirq_amd756_set;
721 static __initdata struct irq_router_handler pirq_routers[] = {
722 { PCI_VENDOR_ID_INTEL, intel_router_probe },
723 { PCI_VENDOR_ID_AL, ali_router_probe },
724 { PCI_VENDOR_ID_ITE, ite_router_probe },
725 { PCI_VENDOR_ID_VIA, via_router_probe },
726 { PCI_VENDOR_ID_OPTI, opti_router_probe },
727 { PCI_VENDOR_ID_SI, sis_router_probe },
728 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
729 { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
730 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
731 { PCI_VENDOR_ID_AMD, amd_router_probe },
732 /* Someone with docs needs to add the ATI Radeon IGP */
735 static struct irq_router pirq_router;
736 static struct pci_dev *pirq_router_dev;
740 * FIXME: should we have an option to say "generic for
744 static void __init pirq_find_router(struct irq_router *r)
746 struct irq_routing_table *rt = pirq_table;
747 struct irq_router_handler *h;
749 #ifdef CONFIG_PCI_BIOS
750 if (!rt->signature) {
751 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
752 r->set = pirq_bios_set;
758 /* Default unless a driver reloads it */
763 DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for %04x:%04x\n",
764 rt->rtr_vendor, rt->rtr_device);
766 pirq_router_dev = pci_find_slot(rt->rtr_bus, rt->rtr_devfn);
767 if (!pirq_router_dev) {
768 DBG(KERN_DEBUG "PCI: Interrupt router not found at "
769 "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
773 for( h = pirq_routers; h->vendor; h++) {
774 /* First look for a router match */
775 if (rt->rtr_vendor == h->vendor && h->probe(r, pirq_router_dev, rt->rtr_device))
777 /* Fall back to a device match */
778 if (pirq_router_dev->vendor == h->vendor && h->probe(r, pirq_router_dev, pirq_router_dev->device))
781 printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n",
783 pirq_router_dev->vendor,
784 pirq_router_dev->device,
785 pci_name(pirq_router_dev));
788 static struct irq_info *pirq_get_info(struct pci_dev *dev)
790 struct irq_routing_table *rt = pirq_table;
791 int entries = (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info);
792 struct irq_info *info;
794 for (info = rt->slots; entries--; info++)
795 if (info->bus == dev->bus->number && PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
800 static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
803 struct irq_info *info;
807 struct irq_router *r = &pirq_router;
808 struct pci_dev *dev2 = NULL;
812 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
814 DBG(KERN_DEBUG " -> no interrupt pin\n");
819 /* Find IRQ routing entry */
824 DBG(KERN_DEBUG "IRQ for %s[%c]", pci_name(dev), 'A' + pin);
825 info = pirq_get_info(dev);
827 DBG(" -> not found in routing table\n" KERN_DEBUG);
830 pirq = info->irq[pin].link;
831 mask = info->irq[pin].bitmap;
833 DBG(" -> not routed\n" KERN_DEBUG);
836 DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, pirq_table->exclusive_irqs);
837 mask &= pcibios_irq_mask;
839 /* Work around broken HP Pavilion Notebooks which assign USB to
840 IRQ 9 even though it is actually wired to IRQ 11 */
842 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
844 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
845 r->set(pirq_router_dev, dev, pirq, 11);
848 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
849 if (acer_tm360_irqrouting && dev->irq == 11 && dev->vendor == PCI_VENDOR_ID_O2) {
852 dev->irq = r->get(pirq_router_dev, dev, pirq);
853 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
857 * Find the best IRQ to assign: use the one
858 * reported by the device if possible.
861 if (newirq && !((1 << newirq) & mask)) {
862 if ( pci_probe & PCI_USE_PIRQ_MASK) newirq = 0;
863 else printk("\n" KERN_WARNING
864 "PCI: IRQ %i for device %s doesn't match PIRQ mask "
865 "- try pci=usepirqmask\n" KERN_DEBUG, newirq,
868 if (!newirq && assign) {
869 for (i = 0; i < 16; i++) {
870 if (!(mask & (1 << i)))
872 if (pirq_penalty[i] < pirq_penalty[newirq] && can_request_irq(i, IRQF_SHARED))
876 DBG(" -> newirq=%d", newirq);
878 /* Check if it is hardcoded */
879 if ((pirq & 0xf0) == 0xf0) {
881 DBG(" -> hardcoded IRQ %d\n", irq);
883 } else if ( r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
884 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask)) ) {
885 DBG(" -> got IRQ %d\n", irq);
887 eisa_set_level_irq(irq);
888 } else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
889 DBG(" -> assigning IRQ %d", newirq);
890 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
891 eisa_set_level_irq(newirq);
899 DBG(" ... failed\n");
900 if (newirq && mask == (1 << newirq)) {
906 printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, pci_name(dev));
908 /* Update IRQ for all devices with the same pirq value */
909 while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) {
910 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
914 info = pirq_get_info(dev2);
917 if (info->irq[pin].link == pirq) {
918 /* We refuse to override the dev->irq information. Give a warning! */
919 if ( dev2->irq && dev2->irq != irq && \
920 (!(pci_probe & PCI_USE_PIRQ_MASK) || \
921 ((1 << dev2->irq) & mask)) ) {
922 #ifndef CONFIG_PCI_MSI
923 printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
924 pci_name(dev2), dev2->irq, irq);
931 printk(KERN_INFO "PCI: Sharing IRQ %d with %s\n", irq, pci_name(dev2));
937 static void __init pcibios_fixup_irqs(void)
939 struct pci_dev *dev = NULL;
942 DBG(KERN_DEBUG "PCI: IRQ fixup\n");
943 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
945 * If the BIOS has set an out of range IRQ number, just ignore it.
946 * Also keep track of which IRQ's are already in use.
948 if (dev->irq >= 16) {
949 DBG(KERN_DEBUG "%s: ignoring bogus IRQ %d\n", pci_name(dev), dev->irq);
952 /* If the IRQ is already assigned to a PCI device, ignore its ISA use penalty */
953 if (pirq_penalty[dev->irq] >= 100 && pirq_penalty[dev->irq] < 100000)
954 pirq_penalty[dev->irq] = 0;
955 pirq_penalty[dev->irq]++;
959 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
960 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
961 #ifdef CONFIG_X86_IO_APIC
963 * Recalculate IRQ numbers if we use the I/O APIC.
965 if (io_apic_assign_pci_irqs)
970 pin--; /* interrupt pins are numbered starting from 1 */
971 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
973 * Busses behind bridges are typically not listed in the MP-table.
974 * In this case we have to look up the IRQ based on the parent bus,
975 * parent slot, and pin number. The SMP code detects such bridged
976 * busses itself so we should get into this branch reliably.
978 if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
979 struct pci_dev * bridge = dev->bus->self;
981 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
982 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
983 PCI_SLOT(bridge->devfn), pin);
985 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
986 pci_name(bridge), 'A' + pin, irq);
989 if (use_pci_vector() &&
990 !platform_legacy_irq(irq))
991 irq = IO_APIC_VECTOR(irq);
993 printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
994 pci_name(dev), 'A' + pin, irq);
1001 * Still no IRQ? Try to lookup one...
1003 if (pin && !dev->irq)
1004 pcibios_lookup_irq(dev, 0);
1009 * Work around broken HP Pavilion Notebooks which assign USB to
1010 * IRQ 9 even though it is actually wired to IRQ 11
1012 static int __init fix_broken_hp_bios_irq9(struct dmi_system_id *d)
1014 if (!broken_hp_bios_irq9) {
1015 broken_hp_bios_irq9 = 1;
1016 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
1022 * Work around broken Acer TravelMate 360 Notebooks which assign
1023 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
1025 static int __init fix_acer_tm360_irqrouting(struct dmi_system_id *d)
1027 if (!acer_tm360_irqrouting) {
1028 acer_tm360_irqrouting = 1;
1029 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
1034 static struct dmi_system_id __initdata pciirq_dmi_table[] = {
1036 .callback = fix_broken_hp_bios_irq9,
1037 .ident = "HP Pavilion N5400 Series Laptop",
1039 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1040 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
1041 DMI_MATCH(DMI_PRODUCT_VERSION, "HP Pavilion Notebook Model GE"),
1042 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
1046 .callback = fix_acer_tm360_irqrouting,
1047 .ident = "Acer TravelMate 36x Laptop",
1049 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1050 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
1056 static int __init pcibios_irq_init(void)
1058 DBG(KERN_DEBUG "PCI: IRQ init\n");
1060 if (pcibios_enable_irq || raw_pci_ops == NULL)
1063 dmi_check_system(pciirq_dmi_table);
1065 pirq_table = pirq_find_routing_table();
1067 #ifdef CONFIG_PCI_BIOS
1068 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
1069 pirq_table = pcibios_get_irq_routing_table();
1073 pirq_find_router(&pirq_router);
1074 if (pirq_table->exclusive_irqs) {
1076 for (i=0; i<16; i++)
1077 if (!(pirq_table->exclusive_irqs & (1 << i)))
1078 pirq_penalty[i] += 100;
1080 /* If we're using the I/O APIC, avoid using the PCI IRQ routing table */
1081 if (io_apic_assign_pci_irqs)
1085 pcibios_enable_irq = pirq_enable_irq;
1087 pcibios_fixup_irqs();
1091 subsys_initcall(pcibios_irq_init);
1094 static void pirq_penalize_isa_irq(int irq, int active)
1097 * If any ISAPnP device reports an IRQ in its list of possible
1098 * IRQ's, we try to avoid assigning it to PCI devices.
1102 pirq_penalty[irq] += 1000;
1104 pirq_penalty[irq] += 100;
1108 void pcibios_penalize_isa_irq(int irq, int active)
1112 acpi_penalize_isa_irq(irq, active);
1115 pirq_penalize_isa_irq(irq, active);
1118 static int pirq_enable_irq(struct pci_dev *dev)
1121 struct pci_dev *temp_dev;
1123 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1124 if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) {
1127 pin--; /* interrupt pins are numbered starting from 1 */
1129 if (io_apic_assign_pci_irqs) {
1132 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
1134 * Busses behind bridges are typically not listed in the MP-table.
1135 * In this case we have to look up the IRQ based on the parent bus,
1136 * parent slot, and pin number. The SMP code detects such bridged
1137 * busses itself so we should get into this branch reliably.
1140 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1141 struct pci_dev * bridge = dev->bus->self;
1143 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1144 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1145 PCI_SLOT(bridge->devfn), pin);
1147 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
1148 pci_name(bridge), 'A' + pin, irq);
1153 #ifdef CONFIG_PCI_MSI
1154 if (!platform_legacy_irq(irq))
1155 irq = IO_APIC_VECTOR(irq);
1157 printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
1158 pci_name(dev), 'A' + pin, irq);
1162 msg = " Probably buggy MP table.";
1163 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1166 msg = " Please try using pci=biosirq.";
1168 /* With IDE legacy devices the IRQ lookup failure is not a problem.. */
1169 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && !(dev->class & 0x5))
1172 printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n",
1173 'A' + pin, pci_name(dev), msg);
1178 int pci_vector_resources(int last, int nr_released)
1180 int count = nr_released;
1183 int offset = (last % 8);
1185 while (next < FIRST_SYSTEM_VECTOR) {
1187 #ifdef CONFIG_X86_64
1188 if (next == IA32_SYSCALL_VECTOR)
1191 if (next == SYSCALL_VECTOR)
1195 if (next >= FIRST_SYSTEM_VECTOR) {
1197 next = FIRST_DEVICE_VECTOR + offset;