2 * Low-Level PCI Support for PC -- Routing of Interrupts
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
7 #include <linux/config.h>
8 #include <linux/types.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/slab.h>
13 #include <linux/interrupt.h>
14 #include <linux/dmi.h>
17 #include <asm/io_apic.h>
18 #include <linux/irq.h>
19 #include <linux/acpi.h>
23 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
24 #define PIRQ_VERSION 0x0100
26 static int broken_hp_bios_irq9;
27 static int acer_tm360_irqrouting;
29 static struct irq_routing_table *pirq_table;
31 static int pirq_enable_irq(struct pci_dev *dev);
34 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
35 * Avoid using: 13, 14 and 15 (FP error and IDE).
36 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
38 unsigned int pcibios_irq_mask = 0xfff8;
40 static int pirq_penalty[16] = {
41 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
42 0, 0, 0, 0, 1000, 100000, 100000, 100000
48 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
49 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new);
52 struct irq_router_handler {
54 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
57 int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL;
58 void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL;
61 * Check passed address for the PCI IRQ Routing Table signature
62 * and perform checksum verification.
65 static inline struct irq_routing_table * pirq_check_routing_table(u8 *addr)
67 struct irq_routing_table *rt;
71 rt = (struct irq_routing_table *) addr;
72 if (rt->signature != PIRQ_SIGNATURE ||
73 rt->version != PIRQ_VERSION ||
75 rt->size < sizeof(struct irq_routing_table))
78 for (i=0; i < rt->size; i++)
81 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n", rt);
90 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
93 static struct irq_routing_table * __init pirq_find_routing_table(void)
96 struct irq_routing_table *rt;
98 #ifdef CONFIG_XEN_PRIVILEGED_GUEST
99 if (pirq_table_addr) {
100 rt = pirq_check_routing_table((u8 *) isa_bus_to_virt(pirq_table_addr));
103 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n");
105 for(addr = (u8 *) isa_bus_to_virt(0xf0000); addr < (u8 *) isa_bus_to_virt(0x100000); addr += 16) {
106 rt = pirq_check_routing_table(addr);
116 * If we have a IRQ routing table, use it to search for peer host
117 * bridges. It's a gross hack, but since there are no other known
118 * ways how to get a list of buses, we have to go this way.
121 static void __init pirq_peer_trick(void)
123 struct irq_routing_table *rt = pirq_table;
128 memset(busmap, 0, sizeof(busmap));
129 for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
134 DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
136 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
142 for(i = 1; i < 256; i++) {
143 if (!busmap[i] || pci_find_bus(0, i))
145 if (pci_scan_bus(i, &pci_root_ops, NULL))
146 printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
148 pcibios_last_bus = -1;
152 * Code for querying and setting of IRQ routes on various interrupt routers.
155 void eisa_set_level_irq(unsigned int irq)
157 unsigned char mask = 1 << (irq & 7);
158 unsigned int port = 0x4d0 + (irq >> 3);
160 static u16 eisa_irq_mask;
162 if (irq >= 16 || (1 << irq) & eisa_irq_mask)
165 eisa_irq_mask |= (1 << irq);
166 printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq);
169 DBG(KERN_DEBUG " -> edge");
170 outb(val | mask, port);
175 * Common IRQ routing practice: nybbles in config space,
176 * offset by some magic constant.
178 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
181 unsigned reg = offset + (nr >> 1);
183 pci_read_config_byte(router, reg, &x);
184 return (nr & 1) ? (x >> 4) : (x & 0xf);
187 static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val)
190 unsigned reg = offset + (nr >> 1);
192 pci_read_config_byte(router, reg, &x);
193 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
194 pci_write_config_byte(router, reg, x);
198 * ALI pirq entries are damn ugly, and completely undocumented.
199 * This has been figured out from pirq tables, and it's not a pretty
202 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
204 static unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
206 return irqmap[read_config_nybble(router, 0x48, pirq-1)];
209 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
211 static unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
212 unsigned int val = irqmap[irq];
215 write_config_nybble(router, 0x48, pirq-1, val);
222 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
223 * just a pointer to the config space.
225 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
229 pci_read_config_byte(router, pirq, &x);
230 return (x < 16) ? x : 0;
233 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
235 pci_write_config_byte(router, pirq, irq);
240 * The VIA pirq rules are nibble-based, like ALI,
241 * but without the ugly irq number munging.
242 * However, PIRQD is in the upper instead of lower 4 bits.
244 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
246 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
249 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
251 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
256 * The VIA pirq rules are nibble-based, like ALI,
257 * but without the ugly irq number munging.
258 * However, for 82C586, nibble map is different .
260 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
262 static unsigned int pirqmap[4] = { 3, 2, 5, 1 };
263 return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
266 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
268 static unsigned int pirqmap[4] = { 3, 2, 5, 1 };
269 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
274 * ITE 8330G pirq rules are nibble-based
275 * FIXME: pirqmap may be { 1, 0, 3, 2 },
276 * 2+3 are both mapped to irq 9 on my system
278 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
280 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
281 return read_config_nybble(router,0x43, pirqmap[pirq-1]);
284 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
286 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
287 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
292 * OPTI: high four bits are nibble pointer..
293 * I wonder what the low bits do?
295 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
297 return read_config_nybble(router, 0xb8, pirq >> 4);
300 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
302 write_config_nybble(router, 0xb8, pirq >> 4, irq);
307 * Cyrix: nibble offset 0x5C
308 * 0x5C bits 7:4 is INTB bits 3:0 is INTA
309 * 0x5D bits 7:4 is INTD bits 3:0 is INTC
311 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
313 return read_config_nybble(router, 0x5C, (pirq-1)^1);
316 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
318 write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
323 * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
324 * We have to deal with the following issues here:
325 * - vendors have different ideas about the meaning of link values
326 * - some onboard devices (integrated in the chipset) have special
327 * links and are thus routed differently (i.e. not via PCI INTA-INTD)
328 * - different revision of the router have a different layout for
329 * the routing registers, particularly for the onchip devices
331 * For all routing registers the common thing is we have one byte
332 * per routeable link which is defined as:
333 * bit 7 IRQ mapping enabled (0) or disabled (1)
334 * bits [6:4] reserved (sometimes used for onchip devices)
335 * bits [3:0] IRQ to map to
336 * allowed: 3-7, 9-12, 14-15
337 * reserved: 0, 1, 2, 8, 13
339 * The config-space registers located at 0x41/0x42/0x43/0x44 are
340 * always used to route the normal PCI INT A/B/C/D respectively.
341 * Apparently there are systems implementing PCI routing table using
342 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
343 * We try our best to handle both link mappings.
345 * Currently (2003-05-21) it appears most SiS chipsets follow the
346 * definition of routing registers from the SiS-5595 southbridge.
347 * According to the SiS 5595 datasheets the revision id's of the
348 * router (ISA-bridge) should be 0x01 or 0xb0.
350 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
351 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
352 * They seem to work with the current routing code. However there is
353 * some concern because of the two USB-OHCI HCs (original SiS 5595
354 * had only one). YMMV.
356 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
359 * bits [6:5] must be written 01
360 * bit 4 channel-select primary (0), secondary (1)
363 * bit 6 OHCI function disabled (0), enabled (1)
365 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
367 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
369 * We support USBIRQ (in addition to INTA-INTD) and keep the
370 * IDE, ACPI and DAQ routing untouched as set by the BIOS.
372 * Currently the only reported exception is the new SiS 65x chipset
373 * which includes the SiS 69x southbridge. Here we have the 85C503
374 * router revision 0x04 and there are changes in the register layout
375 * mostly related to the different USB HCs with USB 2.0 support.
377 * Onchip routing for router rev-id 0x04 (try-and-error observation)
379 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
380 * bit 6-4 are probably unused, not like 5595
383 #define PIRQ_SIS_IRQ_MASK 0x0f
384 #define PIRQ_SIS_IRQ_DISABLE 0x80
385 #define PIRQ_SIS_USB_ENABLE 0x40
387 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
393 if (reg >= 0x01 && reg <= 0x04)
395 pci_read_config_byte(router, reg, &x);
396 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
399 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
405 if (reg >= 0x01 && reg <= 0x04)
407 pci_read_config_byte(router, reg, &x);
408 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
409 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
410 pci_write_config_byte(router, reg, x);
416 * VLSI: nibble offset 0x74 - educated guess due to routing table and
417 * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
418 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
419 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
420 * for the busbridge to the docking station.
423 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
426 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
429 return read_config_nybble(router, 0x74, pirq-1);
432 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
435 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
438 write_config_nybble(router, 0x74, pirq-1, irq);
443 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
444 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
445 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
446 * register is a straight binary coding of desired PIC IRQ (low nibble).
448 * The 'link' value in the PIRQ table is already in the correct format
449 * for the Index register. There are some special index values:
450 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
451 * and 0x03 for SMBus.
453 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
456 return inb(0xc01) & 0xf;
459 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
466 /* Support for AMD756 PCI IRQ Routing
467 * Jhon H. Caicedo <jhcaiced@osso.org.co>
468 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
469 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
470 * The AMD756 pirq rules are nibble-based
471 * offset 0x56 0-3 PIRQA 4-7 PIRQB
472 * offset 0x57 0-3 PIRQC 4-7 PIRQD
474 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
480 irq = read_config_nybble(router, 0x56, pirq - 1);
482 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n",
483 dev->vendor, dev->device, pirq, irq);
487 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
489 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
490 dev->vendor, dev->device, pirq, irq);
493 write_config_nybble(router, 0x56, pirq - 1, irq);
498 #ifdef CONFIG_PCI_BIOS
500 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
502 struct pci_dev *bridge;
503 int pin = pci_get_interrupt_pin(dev, &bridge);
504 return pcibios_set_irq_routing(bridge, pin, irq);
509 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
511 static struct pci_device_id pirq_440gx[] = {
512 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
513 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
517 /* 440GX has a proprietary PIRQ router -- don't use it */
518 if (pci_dev_present(pirq_440gx))
523 case PCI_DEVICE_ID_INTEL_82371FB_0:
524 case PCI_DEVICE_ID_INTEL_82371SB_0:
525 case PCI_DEVICE_ID_INTEL_82371AB_0:
526 case PCI_DEVICE_ID_INTEL_82371MX:
527 case PCI_DEVICE_ID_INTEL_82443MX_0:
528 case PCI_DEVICE_ID_INTEL_82801AA_0:
529 case PCI_DEVICE_ID_INTEL_82801AB_0:
530 case PCI_DEVICE_ID_INTEL_82801BA_0:
531 case PCI_DEVICE_ID_INTEL_82801BA_10:
532 case PCI_DEVICE_ID_INTEL_82801CA_0:
533 case PCI_DEVICE_ID_INTEL_82801CA_12:
534 case PCI_DEVICE_ID_INTEL_82801DB_0:
535 case PCI_DEVICE_ID_INTEL_82801E_0:
536 case PCI_DEVICE_ID_INTEL_82801EB_0:
537 case PCI_DEVICE_ID_INTEL_ESB_1:
538 case PCI_DEVICE_ID_INTEL_ICH6_0:
539 case PCI_DEVICE_ID_INTEL_ICH6_1:
540 case PCI_DEVICE_ID_INTEL_ICH7_0:
541 case PCI_DEVICE_ID_INTEL_ICH7_1:
542 case PCI_DEVICE_ID_INTEL_ICH7_30:
543 case PCI_DEVICE_ID_INTEL_ICH7_31:
544 case PCI_DEVICE_ID_INTEL_ESB2_0:
545 case PCI_DEVICE_ID_INTEL_ICH8_0:
546 case PCI_DEVICE_ID_INTEL_ICH8_1:
547 case PCI_DEVICE_ID_INTEL_ICH8_2:
548 case PCI_DEVICE_ID_INTEL_ICH8_3:
549 case PCI_DEVICE_ID_INTEL_ICH8_4:
550 r->name = "PIIX/ICH";
551 r->get = pirq_piix_get;
552 r->set = pirq_piix_set;
558 static __init int via_router_probe(struct irq_router *r,
559 struct pci_dev *router, u16 device)
561 /* FIXME: We should move some of the quirk fixup stuff here */
564 * work arounds for some buggy BIOSes
566 if (device == PCI_DEVICE_ID_VIA_82C586_0) {
567 switch(router->device) {
568 case PCI_DEVICE_ID_VIA_82C686:
570 * Asus k7m bios wrongly reports 82C686A
573 device = PCI_DEVICE_ID_VIA_82C686;
575 case PCI_DEVICE_ID_VIA_8235:
577 * Asus a7v-x bios wrongly reports 8235
580 device = PCI_DEVICE_ID_VIA_8235;
586 case PCI_DEVICE_ID_VIA_82C586_0:
588 r->get = pirq_via586_get;
589 r->set = pirq_via586_set;
591 case PCI_DEVICE_ID_VIA_82C596:
592 case PCI_DEVICE_ID_VIA_82C686:
593 case PCI_DEVICE_ID_VIA_8231:
594 case PCI_DEVICE_ID_VIA_8233A:
595 case PCI_DEVICE_ID_VIA_8235:
596 case PCI_DEVICE_ID_VIA_8237:
597 /* FIXME: add new ones for 8233/5 */
599 r->get = pirq_via_get;
600 r->set = pirq_via_set;
606 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
610 case PCI_DEVICE_ID_VLSI_82C534:
611 r->name = "VLSI 82C534";
612 r->get = pirq_vlsi_get;
613 r->set = pirq_vlsi_set;
620 static __init int serverworks_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
624 case PCI_DEVICE_ID_SERVERWORKS_OSB4:
625 case PCI_DEVICE_ID_SERVERWORKS_CSB5:
626 r->name = "ServerWorks";
627 r->get = pirq_serverworks_get;
628 r->set = pirq_serverworks_set;
634 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
636 if (device != PCI_DEVICE_ID_SI_503)
640 r->get = pirq_sis_get;
641 r->set = pirq_sis_set;
645 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
649 case PCI_DEVICE_ID_CYRIX_5520:
651 r->get = pirq_cyrix_get;
652 r->set = pirq_cyrix_set;
658 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
662 case PCI_DEVICE_ID_OPTI_82C700:
664 r->get = pirq_opti_get;
665 r->set = pirq_opti_set;
671 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
675 case PCI_DEVICE_ID_ITE_IT8330G_0:
677 r->get = pirq_ite_get;
678 r->set = pirq_ite_set;
684 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
688 case PCI_DEVICE_ID_AL_M1533:
689 case PCI_DEVICE_ID_AL_M1563:
690 printk(KERN_DEBUG "PCI: Using ALI IRQ Router\n");
692 r->get = pirq_ali_get;
693 r->set = pirq_ali_set;
699 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
703 case PCI_DEVICE_ID_AMD_VIPER_740B:
706 case PCI_DEVICE_ID_AMD_VIPER_7413:
709 case PCI_DEVICE_ID_AMD_VIPER_7443:
715 r->get = pirq_amd756_get;
716 r->set = pirq_amd756_set;
720 static __initdata struct irq_router_handler pirq_routers[] = {
721 { PCI_VENDOR_ID_INTEL, intel_router_probe },
722 { PCI_VENDOR_ID_AL, ali_router_probe },
723 { PCI_VENDOR_ID_ITE, ite_router_probe },
724 { PCI_VENDOR_ID_VIA, via_router_probe },
725 { PCI_VENDOR_ID_OPTI, opti_router_probe },
726 { PCI_VENDOR_ID_SI, sis_router_probe },
727 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
728 { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
729 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
730 { PCI_VENDOR_ID_AMD, amd_router_probe },
731 /* Someone with docs needs to add the ATI Radeon IGP */
734 static struct irq_router pirq_router;
735 static struct pci_dev *pirq_router_dev;
739 * FIXME: should we have an option to say "generic for
743 static void __init pirq_find_router(struct irq_router *r)
745 struct irq_routing_table *rt = pirq_table;
746 struct irq_router_handler *h;
748 #ifdef CONFIG_PCI_BIOS
749 if (!rt->signature) {
750 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
751 r->set = pirq_bios_set;
757 /* Default unless a driver reloads it */
762 DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for %04x:%04x\n",
763 rt->rtr_vendor, rt->rtr_device);
765 pirq_router_dev = pci_find_slot(rt->rtr_bus, rt->rtr_devfn);
766 if (!pirq_router_dev) {
767 DBG(KERN_DEBUG "PCI: Interrupt router not found at "
768 "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
772 for( h = pirq_routers; h->vendor; h++) {
773 /* First look for a router match */
774 if (rt->rtr_vendor == h->vendor && h->probe(r, pirq_router_dev, rt->rtr_device))
776 /* Fall back to a device match */
777 if (pirq_router_dev->vendor == h->vendor && h->probe(r, pirq_router_dev, pirq_router_dev->device))
780 printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n",
782 pirq_router_dev->vendor,
783 pirq_router_dev->device,
784 pci_name(pirq_router_dev));
787 static struct irq_info *pirq_get_info(struct pci_dev *dev)
789 struct irq_routing_table *rt = pirq_table;
790 int entries = (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info);
791 struct irq_info *info;
793 for (info = rt->slots; entries--; info++)
794 if (info->bus == dev->bus->number && PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
799 static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
802 struct irq_info *info;
806 struct irq_router *r = &pirq_router;
807 struct pci_dev *dev2 = NULL;
811 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
813 DBG(KERN_DEBUG " -> no interrupt pin\n");
818 /* Find IRQ routing entry */
823 DBG(KERN_DEBUG "IRQ for %s[%c]", pci_name(dev), 'A' + pin);
824 info = pirq_get_info(dev);
826 DBG(" -> not found in routing table\n" KERN_DEBUG);
829 pirq = info->irq[pin].link;
830 mask = info->irq[pin].bitmap;
832 DBG(" -> not routed\n" KERN_DEBUG);
835 DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, pirq_table->exclusive_irqs);
836 mask &= pcibios_irq_mask;
838 /* Work around broken HP Pavilion Notebooks which assign USB to
839 IRQ 9 even though it is actually wired to IRQ 11 */
841 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
843 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
844 r->set(pirq_router_dev, dev, pirq, 11);
847 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
848 if (acer_tm360_irqrouting && dev->irq == 11 && dev->vendor == PCI_VENDOR_ID_O2) {
851 dev->irq = r->get(pirq_router_dev, dev, pirq);
852 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
856 * Find the best IRQ to assign: use the one
857 * reported by the device if possible.
860 if (newirq && !((1 << newirq) & mask)) {
861 if ( pci_probe & PCI_USE_PIRQ_MASK) newirq = 0;
862 else printk("\n" KERN_WARNING
863 "PCI: IRQ %i for device %s doesn't match PIRQ mask "
864 "- try pci=usepirqmask\n" KERN_DEBUG, newirq,
867 if (!newirq && assign) {
868 for (i = 0; i < 16; i++) {
869 if (!(mask & (1 << i)))
871 if (pirq_penalty[i] < pirq_penalty[newirq] && can_request_irq(i, SA_SHIRQ))
875 DBG(" -> newirq=%d", newirq);
877 /* Check if it is hardcoded */
878 if ((pirq & 0xf0) == 0xf0) {
880 DBG(" -> hardcoded IRQ %d\n", irq);
882 } else if ( r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
883 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask)) ) {
884 DBG(" -> got IRQ %d\n", irq);
886 } else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
887 DBG(" -> assigning IRQ %d", newirq);
888 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
889 eisa_set_level_irq(newirq);
897 DBG(" ... failed\n");
898 if (newirq && mask == (1 << newirq)) {
904 printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, pci_name(dev));
906 /* Update IRQ for all devices with the same pirq value */
907 while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) {
908 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
912 info = pirq_get_info(dev2);
915 if (info->irq[pin].link == pirq) {
916 /* We refuse to override the dev->irq information. Give a warning! */
917 if ( dev2->irq && dev2->irq != irq && \
918 (!(pci_probe & PCI_USE_PIRQ_MASK) || \
919 ((1 << dev2->irq) & mask)) ) {
920 #ifndef CONFIG_PCI_MSI
921 printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
922 pci_name(dev2), dev2->irq, irq);
929 printk(KERN_INFO "PCI: Sharing IRQ %d with %s\n", irq, pci_name(dev2));
935 static void __init pcibios_fixup_irqs(void)
937 struct pci_dev *dev = NULL;
940 DBG(KERN_DEBUG "PCI: IRQ fixup\n");
941 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
943 * If the BIOS has set an out of range IRQ number, just ignore it.
944 * Also keep track of which IRQ's are already in use.
946 if (dev->irq >= 16) {
947 DBG(KERN_DEBUG "%s: ignoring bogus IRQ %d\n", pci_name(dev), dev->irq);
950 /* If the IRQ is already assigned to a PCI device, ignore its ISA use penalty */
951 if (pirq_penalty[dev->irq] >= 100 && pirq_penalty[dev->irq] < 100000)
952 pirq_penalty[dev->irq] = 0;
953 pirq_penalty[dev->irq]++;
957 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
958 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
959 #ifdef CONFIG_X86_IO_APIC
961 * Recalculate IRQ numbers if we use the I/O APIC.
963 if (io_apic_assign_pci_irqs)
968 pin--; /* interrupt pins are numbered starting from 1 */
969 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
971 * Busses behind bridges are typically not listed in the MP-table.
972 * In this case we have to look up the IRQ based on the parent bus,
973 * parent slot, and pin number. The SMP code detects such bridged
974 * busses itself so we should get into this branch reliably.
976 if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
977 struct pci_dev * bridge = dev->bus->self;
979 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
980 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
981 PCI_SLOT(bridge->devfn), pin);
983 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
984 pci_name(bridge), 'A' + pin, irq);
987 if (use_pci_vector() &&
988 !platform_legacy_irq(irq))
989 irq = IO_APIC_VECTOR(irq);
991 printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
992 pci_name(dev), 'A' + pin, irq);
999 * Still no IRQ? Try to lookup one...
1001 if (pin && !dev->irq)
1002 pcibios_lookup_irq(dev, 0);
1007 * Work around broken HP Pavilion Notebooks which assign USB to
1008 * IRQ 9 even though it is actually wired to IRQ 11
1010 static int __init fix_broken_hp_bios_irq9(struct dmi_system_id *d)
1012 if (!broken_hp_bios_irq9) {
1013 broken_hp_bios_irq9 = 1;
1014 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
1020 * Work around broken Acer TravelMate 360 Notebooks which assign
1021 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
1023 static int __init fix_acer_tm360_irqrouting(struct dmi_system_id *d)
1025 if (!acer_tm360_irqrouting) {
1026 acer_tm360_irqrouting = 1;
1027 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
1032 static struct dmi_system_id __initdata pciirq_dmi_table[] = {
1034 .callback = fix_broken_hp_bios_irq9,
1035 .ident = "HP Pavilion N5400 Series Laptop",
1037 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1038 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
1039 DMI_MATCH(DMI_PRODUCT_VERSION, "HP Pavilion Notebook Model GE"),
1040 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
1044 .callback = fix_acer_tm360_irqrouting,
1045 .ident = "Acer TravelMate 36x Laptop",
1047 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1048 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
1054 static int __init pcibios_irq_init(void)
1056 DBG(KERN_DEBUG "PCI: IRQ init\n");
1058 if (pcibios_enable_irq || raw_pci_ops == NULL)
1061 dmi_check_system(pciirq_dmi_table);
1063 pirq_table = pirq_find_routing_table();
1065 #ifdef CONFIG_PCI_BIOS
1066 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
1067 pirq_table = pcibios_get_irq_routing_table();
1071 pirq_find_router(&pirq_router);
1072 if (pirq_table->exclusive_irqs) {
1074 for (i=0; i<16; i++)
1075 if (!(pirq_table->exclusive_irqs & (1 << i)))
1076 pirq_penalty[i] += 100;
1078 /* If we're using the I/O APIC, avoid using the PCI IRQ routing table */
1079 if (io_apic_assign_pci_irqs)
1083 pcibios_enable_irq = pirq_enable_irq;
1085 pcibios_fixup_irqs();
1089 subsys_initcall(pcibios_irq_init);
1092 static void pirq_penalize_isa_irq(int irq, int active)
1095 * If any ISAPnP device reports an IRQ in its list of possible
1096 * IRQ's, we try to avoid assigning it to PCI devices.
1100 pirq_penalty[irq] += 1000;
1102 pirq_penalty[irq] += 100;
1106 void pcibios_penalize_isa_irq(int irq, int active)
1110 acpi_penalize_isa_irq(irq, active);
1113 pirq_penalize_isa_irq(irq, active);
1116 static int pirq_enable_irq(struct pci_dev *dev)
1119 struct pci_dev *temp_dev;
1121 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1122 if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) {
1125 pin--; /* interrupt pins are numbered starting from 1 */
1127 if (io_apic_assign_pci_irqs) {
1130 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
1132 * Busses behind bridges are typically not listed in the MP-table.
1133 * In this case we have to look up the IRQ based on the parent bus,
1134 * parent slot, and pin number. The SMP code detects such bridged
1135 * busses itself so we should get into this branch reliably.
1138 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1139 struct pci_dev * bridge = dev->bus->self;
1141 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1142 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1143 PCI_SLOT(bridge->devfn), pin);
1145 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
1146 pci_name(bridge), 'A' + pin, irq);
1151 #ifdef CONFIG_PCI_MSI
1152 if (!platform_legacy_irq(irq))
1153 irq = IO_APIC_VECTOR(irq);
1155 printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
1156 pci_name(dev), 'A' + pin, irq);
1160 msg = " Probably buggy MP table.";
1161 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1164 msg = " Please try using pci=biosirq.";
1166 /* With IDE legacy devices the IRQ lookup failure is not a problem.. */
1167 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && !(dev->class & 0x5))
1170 printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n",
1171 'A' + pin, pci_name(dev), msg);
1176 int pci_vector_resources(int last, int nr_released)
1178 int count = nr_released;
1181 int offset = (last % 8);
1183 while (next < FIRST_SYSTEM_VECTOR) {
1185 #ifdef CONFIG_X86_64
1186 if (next == IA32_SYSCALL_VECTOR)
1189 if (next == SYSCALL_VECTOR)
1193 if (next >= FIRST_SYSTEM_VECTOR) {
1195 next = FIRST_DEVICE_VECTOR + offset;