2 * Low-Level PCI Support for PC -- Routing of Interrupts
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
7 #include <linux/config.h>
8 #include <linux/types.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/slab.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/dmi.h>
18 #include <asm/io_apic.h>
19 #include <asm/hw_irq.h>
20 #include <linux/acpi.h>
24 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
25 #define PIRQ_VERSION 0x0100
27 static int broken_hp_bios_irq9;
28 static int acer_tm360_irqrouting;
30 static struct irq_routing_table *pirq_table;
33 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
34 * Avoid using: 13, 14 and 15 (FP error and IDE).
35 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
37 unsigned int pcibios_irq_mask = 0xfff8;
39 static int pirq_penalty[16] = {
40 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
41 0, 0, 0, 0, 1000, 100000, 100000, 100000
47 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
48 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new);
51 struct irq_router_handler {
53 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
56 int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL;
59 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
62 static struct irq_routing_table * __init pirq_find_routing_table(void)
65 struct irq_routing_table *rt;
69 for(addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
70 rt = (struct irq_routing_table *) addr;
71 if (rt->signature != PIRQ_SIGNATURE ||
72 rt->version != PIRQ_VERSION ||
74 rt->size < sizeof(struct irq_routing_table))
77 for(i=0; i<rt->size; i++)
80 DBG("PCI: Interrupt Routing Table found at 0x%p\n", rt);
88 * If we have a IRQ routing table, use it to search for peer host
89 * bridges. It's a gross hack, but since there are no other known
90 * ways how to get a list of buses, we have to go this way.
93 static void __init pirq_peer_trick(void)
95 struct irq_routing_table *rt = pirq_table;
100 memset(busmap, 0, sizeof(busmap));
101 for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
106 DBG("%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
108 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
114 for(i = 1; i < 256; i++) {
115 if (!busmap[i] || pci_find_bus(0, i))
117 if (pci_scan_bus(i, &pci_root_ops, NULL))
118 printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
120 pcibios_last_bus = -1;
124 * Code for querying and setting of IRQ routes on various interrupt routers.
127 void eisa_set_level_irq(unsigned int irq)
129 unsigned char mask = 1 << (irq & 7);
130 unsigned int port = 0x4d0 + (irq >> 3);
132 static u16 eisa_irq_mask;
134 if (irq >= 16 || (1 << irq) & eisa_irq_mask)
137 eisa_irq_mask |= (1 << irq);
138 printk("PCI: setting IRQ %u as level-triggered\n", irq);
142 outb(val | mask, port);
147 * Common IRQ routing practice: nybbles in config space,
148 * offset by some magic constant.
150 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
153 unsigned reg = offset + (nr >> 1);
155 pci_read_config_byte(router, reg, &x);
156 return (nr & 1) ? (x >> 4) : (x & 0xf);
159 static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val)
162 unsigned reg = offset + (nr >> 1);
164 pci_read_config_byte(router, reg, &x);
165 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
166 pci_write_config_byte(router, reg, x);
170 * ALI pirq entries are damn ugly, and completely undocumented.
171 * This has been figured out from pirq tables, and it's not a pretty
174 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
176 static unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
178 return irqmap[read_config_nybble(router, 0x48, pirq-1)];
181 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
183 static unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
184 unsigned int val = irqmap[irq];
187 write_config_nybble(router, 0x48, pirq-1, val);
194 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
195 * just a pointer to the config space.
197 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
201 pci_read_config_byte(router, pirq, &x);
202 return (x < 16) ? x : 0;
205 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
207 pci_write_config_byte(router, pirq, irq);
212 * The VIA pirq rules are nibble-based, like ALI,
213 * but without the ugly irq number munging.
214 * However, PIRQD is in the upper instead of lower 4 bits.
216 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
218 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
221 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
223 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
228 * ITE 8330G pirq rules are nibble-based
229 * FIXME: pirqmap may be { 1, 0, 3, 2 },
230 * 2+3 are both mapped to irq 9 on my system
232 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
234 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
235 return read_config_nybble(router,0x43, pirqmap[pirq-1]);
238 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
240 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
241 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
246 * OPTI: high four bits are nibble pointer..
247 * I wonder what the low bits do?
249 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
251 return read_config_nybble(router, 0xb8, pirq >> 4);
254 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
256 write_config_nybble(router, 0xb8, pirq >> 4, irq);
261 * Cyrix: nibble offset 0x5C
262 * 0x5C bits 7:4 is INTB bits 3:0 is INTA
263 * 0x5D bits 7:4 is INTD bits 3:0 is INTC
265 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
267 return read_config_nybble(router, 0x5C, (pirq-1)^1);
270 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
272 write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
277 * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
278 * We have to deal with the following issues here:
279 * - vendors have different ideas about the meaning of link values
280 * - some onboard devices (integrated in the chipset) have special
281 * links and are thus routed differently (i.e. not via PCI INTA-INTD)
282 * - different revision of the router have a different layout for
283 * the routing registers, particularly for the onchip devices
285 * For all routing registers the common thing is we have one byte
286 * per routeable link which is defined as:
287 * bit 7 IRQ mapping enabled (0) or disabled (1)
288 * bits [6:4] reserved (sometimes used for onchip devices)
289 * bits [3:0] IRQ to map to
290 * allowed: 3-7, 9-12, 14-15
291 * reserved: 0, 1, 2, 8, 13
293 * The config-space registers located at 0x41/0x42/0x43/0x44 are
294 * always used to route the normal PCI INT A/B/C/D respectively.
295 * Apparently there are systems implementing PCI routing table using
296 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
297 * We try our best to handle both link mappings.
299 * Currently (2003-05-21) it appears most SiS chipsets follow the
300 * definition of routing registers from the SiS-5595 southbridge.
301 * According to the SiS 5595 datasheets the revision id's of the
302 * router (ISA-bridge) should be 0x01 or 0xb0.
304 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
305 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
306 * They seem to work with the current routing code. However there is
307 * some concern because of the two USB-OHCI HCs (original SiS 5595
308 * had only one). YMMV.
310 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
313 * bits [6:5] must be written 01
314 * bit 4 channel-select primary (0), secondary (1)
317 * bit 6 OHCI function disabled (0), enabled (1)
319 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
321 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
323 * We support USBIRQ (in addition to INTA-INTD) and keep the
324 * IDE, ACPI and DAQ routing untouched as set by the BIOS.
326 * Currently the only reported exception is the new SiS 65x chipset
327 * which includes the SiS 69x southbridge. Here we have the 85C503
328 * router revision 0x04 and there are changes in the register layout
329 * mostly related to the different USB HCs with USB 2.0 support.
331 * Onchip routing for router rev-id 0x04 (try-and-error observation)
333 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
334 * bit 6-4 are probably unused, not like 5595
337 #define PIRQ_SIS_IRQ_MASK 0x0f
338 #define PIRQ_SIS_IRQ_DISABLE 0x80
339 #define PIRQ_SIS_USB_ENABLE 0x40
341 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
347 if (reg >= 0x01 && reg <= 0x04)
349 pci_read_config_byte(router, reg, &x);
350 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
353 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
359 if (reg >= 0x01 && reg <= 0x04)
361 pci_read_config_byte(router, reg, &x);
362 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
363 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
364 pci_write_config_byte(router, reg, x);
370 * VLSI: nibble offset 0x74 - educated guess due to routing table and
371 * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
372 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
373 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
374 * for the busbridge to the docking station.
377 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
380 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
383 return read_config_nybble(router, 0x74, pirq-1);
386 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
389 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
392 write_config_nybble(router, 0x74, pirq-1, irq);
397 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
398 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
399 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
400 * register is a straight binary coding of desired PIC IRQ (low nibble).
402 * The 'link' value in the PIRQ table is already in the correct format
403 * for the Index register. There are some special index values:
404 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
405 * and 0x03 for SMBus.
407 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
410 return inb(0xc01) & 0xf;
413 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
420 /* Support for AMD756 PCI IRQ Routing
421 * Jhon H. Caicedo <jhcaiced@osso.org.co>
422 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
423 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
424 * The AMD756 pirq rules are nibble-based
425 * offset 0x56 0-3 PIRQA 4-7 PIRQB
426 * offset 0x57 0-3 PIRQC 4-7 PIRQD
428 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
434 irq = read_config_nybble(router, 0x56, pirq - 1);
436 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n",
437 dev->vendor, dev->device, pirq, irq);
441 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
443 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
444 dev->vendor, dev->device, pirq, irq);
447 write_config_nybble(router, 0x56, pirq - 1, irq);
452 #ifdef CONFIG_PCI_BIOS
454 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
456 struct pci_dev *bridge;
457 int pin = pci_get_interrupt_pin(dev, &bridge);
458 return pcibios_set_irq_routing(bridge, pin, irq);
463 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
465 static struct pci_device_id pirq_440gx[] = {
466 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
467 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
471 /* 440GX has a proprietary PIRQ router -- don't use it */
472 if (pci_dev_present(pirq_440gx))
477 case PCI_DEVICE_ID_INTEL_82371FB_0:
478 case PCI_DEVICE_ID_INTEL_82371SB_0:
479 case PCI_DEVICE_ID_INTEL_82371AB_0:
480 case PCI_DEVICE_ID_INTEL_82371MX:
481 case PCI_DEVICE_ID_INTEL_82443MX_0:
482 case PCI_DEVICE_ID_INTEL_82801AA_0:
483 case PCI_DEVICE_ID_INTEL_82801AB_0:
484 case PCI_DEVICE_ID_INTEL_82801BA_0:
485 case PCI_DEVICE_ID_INTEL_82801BA_10:
486 case PCI_DEVICE_ID_INTEL_82801CA_0:
487 case PCI_DEVICE_ID_INTEL_82801CA_12:
488 case PCI_DEVICE_ID_INTEL_82801DB_0:
489 case PCI_DEVICE_ID_INTEL_82801E_0:
490 case PCI_DEVICE_ID_INTEL_82801EB_0:
491 case PCI_DEVICE_ID_INTEL_ESB_1:
492 case PCI_DEVICE_ID_INTEL_ICH6_0:
493 case PCI_DEVICE_ID_INTEL_ICH6_1:
494 case PCI_DEVICE_ID_INTEL_ICH7_0:
495 case PCI_DEVICE_ID_INTEL_ICH7_1:
496 r->name = "PIIX/ICH";
497 r->get = pirq_piix_get;
498 r->set = pirq_piix_set;
504 static __init int via_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
506 /* FIXME: We should move some of the quirk fixup stuff here */
509 case PCI_DEVICE_ID_VIA_82C586_0:
510 case PCI_DEVICE_ID_VIA_82C596:
511 case PCI_DEVICE_ID_VIA_82C686:
512 case PCI_DEVICE_ID_VIA_8231:
513 /* FIXME: add new ones for 8233/5 */
515 r->get = pirq_via_get;
516 r->set = pirq_via_set;
522 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
526 case PCI_DEVICE_ID_VLSI_82C534:
527 r->name = "VLSI 82C534";
528 r->get = pirq_vlsi_get;
529 r->set = pirq_vlsi_set;
536 static __init int serverworks_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
540 case PCI_DEVICE_ID_SERVERWORKS_OSB4:
541 case PCI_DEVICE_ID_SERVERWORKS_CSB5:
542 r->name = "ServerWorks";
543 r->get = pirq_serverworks_get;
544 r->set = pirq_serverworks_set;
550 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
552 if (device != PCI_DEVICE_ID_SI_503)
556 r->get = pirq_sis_get;
557 r->set = pirq_sis_set;
561 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
565 case PCI_DEVICE_ID_CYRIX_5520:
567 r->get = pirq_cyrix_get;
568 r->set = pirq_cyrix_set;
574 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
578 case PCI_DEVICE_ID_OPTI_82C700:
580 r->get = pirq_opti_get;
581 r->set = pirq_opti_set;
587 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
591 case PCI_DEVICE_ID_ITE_IT8330G_0:
593 r->get = pirq_ite_get;
594 r->set = pirq_ite_set;
600 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
604 case PCI_DEVICE_ID_AL_M1533:
605 case PCI_DEVICE_ID_AL_M1563:
606 printk("PCI: Using ALI IRQ Router\n");
608 r->get = pirq_ali_get;
609 r->set = pirq_ali_set;
615 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
619 case PCI_DEVICE_ID_AMD_VIPER_740B:
622 case PCI_DEVICE_ID_AMD_VIPER_7413:
625 case PCI_DEVICE_ID_AMD_VIPER_7443:
631 r->get = pirq_amd756_get;
632 r->set = pirq_amd756_set;
636 static __initdata struct irq_router_handler pirq_routers[] = {
637 { PCI_VENDOR_ID_INTEL, intel_router_probe },
638 { PCI_VENDOR_ID_AL, ali_router_probe },
639 { PCI_VENDOR_ID_ITE, ite_router_probe },
640 { PCI_VENDOR_ID_VIA, via_router_probe },
641 { PCI_VENDOR_ID_OPTI, opti_router_probe },
642 { PCI_VENDOR_ID_SI, sis_router_probe },
643 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
644 { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
645 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
646 { PCI_VENDOR_ID_AMD, amd_router_probe },
647 /* Someone with docs needs to add the ATI Radeon IGP */
650 static struct irq_router pirq_router;
651 static struct pci_dev *pirq_router_dev;
655 * FIXME: should we have an option to say "generic for
659 static void __init pirq_find_router(struct irq_router *r)
661 struct irq_routing_table *rt = pirq_table;
662 struct irq_router_handler *h;
664 #ifdef CONFIG_PCI_BIOS
665 if (!rt->signature) {
666 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
667 r->set = pirq_bios_set;
673 /* Default unless a driver reloads it */
678 DBG("PCI: Attempting to find IRQ router for %04x:%04x\n",
679 rt->rtr_vendor, rt->rtr_device);
681 pirq_router_dev = pci_find_slot(rt->rtr_bus, rt->rtr_devfn);
682 if (!pirq_router_dev) {
683 DBG("PCI: Interrupt router not found at %02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
687 for( h = pirq_routers; h->vendor; h++) {
688 /* First look for a router match */
689 if (rt->rtr_vendor == h->vendor && h->probe(r, pirq_router_dev, rt->rtr_device))
691 /* Fall back to a device match */
692 if (pirq_router_dev->vendor == h->vendor && h->probe(r, pirq_router_dev, pirq_router_dev->device))
695 printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n",
697 pirq_router_dev->vendor,
698 pirq_router_dev->device,
699 pci_name(pirq_router_dev));
702 static struct irq_info *pirq_get_info(struct pci_dev *dev)
704 struct irq_routing_table *rt = pirq_table;
705 int entries = (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info);
706 struct irq_info *info;
708 for (info = rt->slots; entries--; info++)
709 if (info->bus == dev->bus->number && PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
714 static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
717 struct irq_info *info;
721 struct irq_router *r = &pirq_router;
722 struct pci_dev *dev2 = NULL;
726 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
728 DBG(" -> no interrupt pin\n");
733 /* Find IRQ routing entry */
738 DBG("IRQ for %s:%d", pci_name(dev), pin);
739 info = pirq_get_info(dev);
741 DBG(" -> not found in routing table\n");
744 pirq = info->irq[pin].link;
745 mask = info->irq[pin].bitmap;
747 DBG(" -> not routed\n");
750 DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, pirq_table->exclusive_irqs);
751 mask &= pcibios_irq_mask;
753 /* Work around broken HP Pavilion Notebooks which assign USB to
754 IRQ 9 even though it is actually wired to IRQ 11 */
756 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
758 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
759 r->set(pirq_router_dev, dev, pirq, 11);
762 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
763 if (acer_tm360_irqrouting && dev->irq == 11 && dev->vendor == PCI_VENDOR_ID_O2) {
766 dev->irq = r->get(pirq_router_dev, dev, pirq);
767 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
771 * Find the best IRQ to assign: use the one
772 * reported by the device if possible.
775 if (!((1 << newirq) & mask)) {
776 if ( pci_probe & PCI_USE_PIRQ_MASK) newirq = 0;
777 else printk(KERN_WARNING "PCI: IRQ %i for device %s doesn't match PIRQ mask - try pci=usepirqmask\n", newirq, pci_name(dev));
779 if (!newirq && assign) {
780 for (i = 0; i < 16; i++) {
781 if (!(mask & (1 << i)))
783 if (pirq_penalty[i] < pirq_penalty[newirq] && can_request_irq(i, SA_SHIRQ))
787 DBG(" -> newirq=%d", newirq);
789 /* Check if it is hardcoded */
790 if ((pirq & 0xf0) == 0xf0) {
792 DBG(" -> hardcoded IRQ %d\n", irq);
794 } else if ( r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
795 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask)) ) {
796 DBG(" -> got IRQ %d\n", irq);
798 } else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
799 DBG(" -> assigning IRQ %d", newirq);
800 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
801 eisa_set_level_irq(newirq);
809 DBG(" ... failed\n");
810 if (newirq && mask == (1 << newirq)) {
816 printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, pci_name(dev));
818 /* Update IRQ for all devices with the same pirq value */
819 while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) {
820 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
824 info = pirq_get_info(dev2);
827 if (info->irq[pin].link == pirq) {
828 /* We refuse to override the dev->irq information. Give a warning! */
829 if ( dev2->irq && dev2->irq != irq && \
830 (!(pci_probe & PCI_USE_PIRQ_MASK) || \
831 ((1 << dev2->irq) & mask)) ) {
832 #ifndef CONFIG_PCI_MSI
833 printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
834 pci_name(dev2), dev2->irq, irq);
841 printk(KERN_INFO "PCI: Sharing IRQ %d with %s\n", irq, pci_name(dev2));
847 static void __init pcibios_fixup_irqs(void)
849 struct pci_dev *dev = NULL;
852 DBG("PCI: IRQ fixup\n");
853 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
855 * If the BIOS has set an out of range IRQ number, just ignore it.
856 * Also keep track of which IRQ's are already in use.
858 if (dev->irq >= 16) {
859 DBG("%s: ignoring bogus IRQ %d\n", pci_name(dev), dev->irq);
862 /* If the IRQ is already assigned to a PCI device, ignore its ISA use penalty */
863 if (pirq_penalty[dev->irq] >= 100 && pirq_penalty[dev->irq] < 100000)
864 pirq_penalty[dev->irq] = 0;
865 pirq_penalty[dev->irq]++;
869 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
870 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
871 #ifdef CONFIG_X86_IO_APIC
873 * Recalculate IRQ numbers if we use the I/O APIC.
875 if (io_apic_assign_pci_irqs)
880 pin--; /* interrupt pins are numbered starting from 1 */
881 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
883 * Busses behind bridges are typically not listed in the MP-table.
884 * In this case we have to look up the IRQ based on the parent bus,
885 * parent slot, and pin number. The SMP code detects such bridged
886 * busses itself so we should get into this branch reliably.
888 if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
889 struct pci_dev * bridge = dev->bus->self;
891 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
892 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
893 PCI_SLOT(bridge->devfn), pin);
895 printk(KERN_WARNING "PCI: using PPB(B%d,I%d,P%d) to get irq %d\n",
896 bridge->bus->number, PCI_SLOT(bridge->devfn), pin, irq);
899 if (use_pci_vector() &&
900 !platform_legacy_irq(irq))
901 irq = IO_APIC_VECTOR(irq);
903 printk(KERN_INFO "PCI->APIC IRQ transform: (B%d,I%d,P%d) -> %d\n",
904 dev->bus->number, PCI_SLOT(dev->devfn), pin, irq);
911 * Still no IRQ? Try to lookup one...
913 if (pin && !dev->irq)
914 pcibios_lookup_irq(dev, 0);
919 * Work around broken HP Pavilion Notebooks which assign USB to
920 * IRQ 9 even though it is actually wired to IRQ 11
922 static int __init fix_broken_hp_bios_irq9(struct dmi_system_id *d)
924 if (!broken_hp_bios_irq9) {
925 broken_hp_bios_irq9 = 1;
926 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
932 * Work around broken Acer TravelMate 360 Notebooks which assign
933 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
935 static int __init fix_acer_tm360_irqrouting(struct dmi_system_id *d)
937 if (!acer_tm360_irqrouting) {
938 acer_tm360_irqrouting = 1;
939 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
944 static struct dmi_system_id __initdata pciirq_dmi_table[] = {
946 .callback = fix_broken_hp_bios_irq9,
947 .ident = "HP Pavilion N5400 Series Laptop",
949 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
950 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
951 DMI_MATCH(DMI_PRODUCT_VERSION, "HP Pavilion Notebook Model GE"),
952 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
956 .callback = fix_acer_tm360_irqrouting,
957 .ident = "Acer TravelMate 36x Laptop",
959 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
960 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
966 static int __init pcibios_irq_init(void)
968 DBG("PCI: IRQ init\n");
970 if (pcibios_enable_irq || raw_pci_ops == NULL)
973 dmi_check_system(pciirq_dmi_table);
975 pirq_table = pirq_find_routing_table();
977 #ifdef CONFIG_PCI_BIOS
978 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
979 pirq_table = pcibios_get_irq_routing_table();
983 pirq_find_router(&pirq_router);
984 if (pirq_table->exclusive_irqs) {
987 if (!(pirq_table->exclusive_irqs & (1 << i)))
988 pirq_penalty[i] += 100;
990 /* If we're using the I/O APIC, avoid using the PCI IRQ routing table */
991 if (io_apic_assign_pci_irqs)
995 pcibios_enable_irq = pirq_enable_irq;
997 pcibios_fixup_irqs();
1001 subsys_initcall(pcibios_irq_init);
1004 static void pirq_penalize_isa_irq(int irq)
1007 * If any ISAPnP device reports an IRQ in its list of possible
1008 * IRQ's, we try to avoid assigning it to PCI devices.
1011 pirq_penalty[irq] += 100;
1014 void pcibios_penalize_isa_irq(int irq)
1016 #ifdef CONFIG_ACPI_PCI
1018 acpi_penalize_isa_irq(irq);
1021 pirq_penalize_isa_irq(irq);
1024 int pirq_enable_irq(struct pci_dev *dev)
1027 extern int via_interrupt_line_quirk;
1028 struct pci_dev *temp_dev;
1030 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1031 if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) {
1034 if (io_apic_assign_pci_irqs) {
1038 pin--; /* interrupt pins are numbered starting from 1 */
1039 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
1041 * Busses behind bridges are typically not listed in the MP-table.
1042 * In this case we have to look up the IRQ based on the parent bus,
1043 * parent slot, and pin number. The SMP code detects such bridged
1044 * busses itself so we should get into this branch reliably.
1047 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1048 struct pci_dev * bridge = dev->bus->self;
1050 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1051 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1052 PCI_SLOT(bridge->devfn), pin);
1054 printk(KERN_WARNING "PCI: using PPB(B%d,I%d,P%d) to get irq %d\n",
1055 bridge->bus->number, PCI_SLOT(bridge->devfn), pin, irq);
1060 #ifdef CONFIG_PCI_MSI
1061 if (!platform_legacy_irq(irq))
1062 irq = IO_APIC_VECTOR(irq);
1064 printk(KERN_INFO "PCI->APIC IRQ transform: (B%d,I%d,P%d) -> %d\n",
1065 dev->bus->number, PCI_SLOT(dev->devfn), pin, irq);
1069 msg = " Probably buggy MP table.";
1071 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1074 msg = " Please try using pci=biosirq.";
1076 /* With IDE legacy devices the IRQ lookup failure is not a problem.. */
1077 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && !(dev->class & 0x5))
1080 printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n",
1081 'A' + pin - 1, pci_name(dev), msg);
1083 /* VIA bridges use interrupt line for apic/pci steering across
1085 else if (via_interrupt_line_quirk)
1086 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq & 15);
1090 int pci_vector_resources(int last, int nr_released)
1092 int count = nr_released;
1095 int offset = (last % 8);
1097 while (next < FIRST_SYSTEM_VECTOR) {
1099 #ifdef CONFIG_X86_64
1100 if (next == IA32_SYSCALL_VECTOR)
1103 if (next == SYSCALL_VECTOR)
1107 if (next >= FIRST_SYSTEM_VECTOR) {
1109 next = FIRST_DEVICE_VECTOR + offset;