2 * This file contains the code that gets mapped at the upper end of each task's text
3 * region. For now, it contains the signal trampoline code only.
5 * Copyright (C) 1999-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
9 #include <linux/config.h>
11 #include <asm/asmmacro.h>
12 #include <asm/errno.h>
13 #include <asm/offsets.h>
14 #include <asm/sigcontext.h>
15 #include <asm/system.h>
16 #include <asm/unistd.h>
19 * We can't easily refer to symbols inside the kernel. To avoid full runtime relocation,
20 * complications with the linker (which likes to create PLT stubs for branches
21 * to targets outside the shared object) and to avoid multi-phase kernel builds, we
22 * simply create minimalistic "patch lists" in special ELF sections.
24 .section ".data.patch.fsyscall_table", "a"
26 #define LOAD_FSYSCALL_TABLE(reg) \
28 .xdata4 ".data.patch.fsyscall_table", 1b-.
30 .section ".data.patch.brl_fsys_bubble_down", "a"
32 #define BRL_COND_FSYS_BUBBLE_DOWN(pr) \
33 [1:](pr)brl.cond.sptk 0; \
34 .xdata4 ".data.patch.brl_fsys_bubble_down", 1b-.
36 GLOBAL_ENTRY(__kernel_syscall_via_break)
41 * Note: for (fast) syscall restart to work, the break instruction must be
42 * the first one in the bundle addressed by syscall_via_break.
49 END(__kernel_syscall_via_break)
55 * b0 = saved return address
60 * b0 = saved return address
61 * all other "scratch" registers: undefined
62 * all "preserved" registers: same as on entry
65 GLOBAL_ENTRY(__kernel_syscall_via_epc)
71 * Note: the kernel cannot assume that the first two instructions in this
72 * bundle get executed. The remaining code must be safe even if
73 * they do not get executed.
76 mov r10=0 // default to successful syscall execution
80 rsm psr.be // note: on McKinley "rsm psr.be/srlz.d" is slightly faster than "rum psr.be"
81 LOAD_FSYSCALL_TABLE(r14)
83 mov r16=IA64_KR(CURRENT) // 12 cycle read latency
89 cmp.ne p8,p0=r0,r0 // p8 <- FALSE
90 /* Note: if r17 is a NaT, p6 will be set to zero. */
91 cmp.geu p6,p7=r19,r17 // (syscall > 0 && syscall < 1024+NR_syscalls)?
94 mov r29=psr // read psr (12 cyc load latency)
95 add r14=-8,r14 // r14 <- addr of fsys_bubble_down entry
98 (p6) tbit.z p8,p0=r18,0
105 * brl.cond doesn't work as intended because the linker would convert this branch
106 * into a branch to a PLT. Perhaps there will be a way to avoid this with some
107 * future version of the linker. In the meantime, we just use an indirect branch
110 #ifdef CONFIG_ITANIUM
111 (p6) ld8 r14=[r14] // r14 <- fsys_bubble_down
116 BRL_COND_FSYS_BUBBLE_DOWN(p6)
122 END(__kernel_syscall_via_epc)
124 # define ARG0_OFF (16 + IA64_SIGFRAME_ARG0_OFFSET)
125 # define ARG1_OFF (16 + IA64_SIGFRAME_ARG1_OFFSET)
126 # define ARG2_OFF (16 + IA64_SIGFRAME_ARG2_OFFSET)
127 # define SIGHANDLER_OFF (16 + IA64_SIGFRAME_HANDLER_OFFSET)
128 # define SIGCONTEXT_OFF (16 + IA64_SIGFRAME_SIGCONTEXT_OFFSET)
130 # define FLAGS_OFF IA64_SIGCONTEXT_FLAGS_OFFSET
131 # define CFM_OFF IA64_SIGCONTEXT_CFM_OFFSET
132 # define FR6_OFF IA64_SIGCONTEXT_FR6_OFFSET
133 # define BSP_OFF IA64_SIGCONTEXT_AR_BSP_OFFSET
134 # define RNAT_OFF IA64_SIGCONTEXT_AR_RNAT_OFFSET
135 # define UNAT_OFF IA64_SIGCONTEXT_AR_UNAT_OFFSET
136 # define FPSR_OFF IA64_SIGCONTEXT_AR_FPSR_OFFSET
137 # define PR_OFF IA64_SIGCONTEXT_PR_OFFSET
138 # define RP_OFF IA64_SIGCONTEXT_IP_OFFSET
139 # define SP_OFF IA64_SIGCONTEXT_R12_OFFSET
140 # define RBS_BASE_OFF IA64_SIGCONTEXT_RBS_BASE_OFFSET
141 # define LOADRS_OFF IA64_SIGCONTEXT_LOADRS_OFFSET
145 * When we get here, the memory stack looks like this:
147 * +===============================+
149 * // struct sigframe //
151 * +-------------------------------+ <-- sp+16
152 * | 16 byte of scratch |
154 * +-------------------------------+ <-- sp
156 * The register stack looks _exactly_ the way it looked at the time the signal
157 * occurred. In other words, we're treading on a potential mine-field: each
158 * incoming general register may be a NaT value (including sp, in which case the
159 * process ends up dying with a SIGSEGV).
161 * The first thing need to do is a cover to get the registers onto the backing
162 * store. Once that is done, we invoke the signal handler which may modify some
163 * of the machine state. After returning from the signal handler, we return
164 * control to the previous context by executing a sigreturn system call. A signal
165 * handler may call the rt_sigreturn() function to directly return to a given
166 * sigcontext. However, the user-level sigreturn() needs to do much more than
167 * calling the rt_sigreturn() system call as it needs to unwind the stack to
168 * restore preserved registers that may have been saved on the signal handler's
172 #define SIGTRAMP_SAVES \
173 .unwabi 3, 's'; /* mark this as a sigtramp handler (saves scratch regs) */ \
174 .unwabi @svr4, 's'; /* backwards compatibility with old unwinders (remove in v2.7) */ \
175 .savesp ar.unat, UNAT_OFF+SIGCONTEXT_OFF; \
176 .savesp ar.fpsr, FPSR_OFF+SIGCONTEXT_OFF; \
177 .savesp pr, PR_OFF+SIGCONTEXT_OFF; \
178 .savesp rp, RP_OFF+SIGCONTEXT_OFF; \
179 .savesp ar.pfs, CFM_OFF+SIGCONTEXT_OFF; \
180 .vframesp SP_OFF+SIGCONTEXT_OFF
182 GLOBAL_ENTRY(__kernel_sigtramp)
183 // describe the state that is active when we get here:
190 adds base0=SIGHANDLER_OFF,sp
191 adds base1=RBS_BASE_OFF+SIGCONTEXT_OFF,sp
192 br.call.sptk.many rp=1f
194 ld8 r17=[base0],(ARG0_OFF-SIGHANDLER_OFF) // get pointer to signal handler's plabel
195 ld8 r15=[base1] // get address of new RBS base (or NULL)
196 cover // push args in interrupted frame onto backing store
198 cmp.ne p1,p0=r15,r0 // do we need to switch rbs? (note: pr is saved by kernel)
199 mov.m r9=ar.bsp // fetch ar.bsp
200 .spillsp.p p1, ar.rnat, RNAT_OFF+SIGCONTEXT_OFF
201 (p1) br.cond.spnt setup_rbs // yup -> (clobbers p8, r14-r16, and r18-r20)
203 alloc r8=ar.pfs,0,0,3,0
204 ld8 out0=[base0],16 // load arg0 (signum)
205 adds base1=(ARG1_OFF-(RBS_BASE_OFF+SIGCONTEXT_OFF)),base1
207 ld8 out1=[base1] // load arg1 (siginfop)
208 ld8 r10=[r17],8 // get signal handler entry point
210 ld8 out2=[base0] // load arg2 (sigcontextp)
211 ld8 gp=[r17] // get signal handler's global pointer
212 adds base0=(BSP_OFF+SIGCONTEXT_OFF),sp
214 .spillsp ar.bsp, BSP_OFF+SIGCONTEXT_OFF
215 st8 [base0]=r9 // save sc_ar_bsp
216 adds base0=(FR6_OFF+SIGCONTEXT_OFF),sp
217 adds base1=(FR6_OFF+16+SIGCONTEXT_OFF),sp
219 stf.spill [base0]=f6,32
220 stf.spill [base1]=f7,32
222 stf.spill [base0]=f8,32
223 stf.spill [base1]=f9,32
226 stf.spill [base0]=f10,32
227 stf.spill [base1]=f11,32
229 stf.spill [base0]=f12,32
230 stf.spill [base1]=f13,32
232 stf.spill [base0]=f14,32
233 stf.spill [base1]=f15,32
234 br.call.sptk.many rp=b6 // call the signal handler
235 .ret0: adds base0=(BSP_OFF+SIGCONTEXT_OFF),sp
237 ld8 r15=[base0] // fetch sc_ar_bsp
240 cmp.ne p1,p0=r14,r15 // do we need to restore the rbs?
241 (p1) br.cond.spnt restore_rbs // yup -> (clobbers r14-r18, f6 & f7)
243 back_from_restore_rbs:
244 adds base0=(FR6_OFF+SIGCONTEXT_OFF),sp
245 adds base1=(FR6_OFF+16+SIGCONTEXT_OFF),sp
247 ldf.fill f6=[base0],32
248 ldf.fill f7=[base1],32
250 ldf.fill f8=[base0],32
251 ldf.fill f9=[base1],32
253 ldf.fill f10=[base0],32
254 ldf.fill f11=[base1],32
256 ldf.fill f12=[base0],32
257 ldf.fill f13=[base1],32
259 ldf.fill f14=[base0],32
260 ldf.fill f15=[base1],32
261 mov r15=__NR_rt_sigreturn
262 .restore sp // pop .prologue
263 break __BREAK_SYSCALL
268 mov ar.rsc=0 // put RSE into enforced lazy mode
271 mov r19=ar.rnat // save RNaT before switching backing store area
272 adds r14=(RNAT_OFF+SIGCONTEXT_OFF),sp
275 mov ar.bspstore=r15 // switch over to new register backing store area
278 .spillsp ar.rnat, RNAT_OFF+SIGCONTEXT_OFF
279 st8 [r14]=r19 // save sc_ar_rnat
281 mov.m r16=ar.bsp // sc_loadrs <- (new bsp - new bspstore) << 16
282 adds r14=(LOADRS_OFF+SIGCONTEXT_OFF),sp
288 mov ar.rsc=0xf // set RSE into eager mode, pl 3
292 st8 [r14]=r15 // save sc_loadrs
293 (p8) st8 [r18]=r19 // if bspstore points at RNaT slot, store RNaT there now
294 .restore sp // pop .prologue
295 br.cond.sptk back_from_setup_rbs
299 .spillsp ar.rnat, RNAT_OFF+SIGCONTEXT_OFF
303 // r14 = bsp1 (bsp at the time of return from signal handler)
304 // r15 = bsp0 (bsp at the time the signal occurred)
306 // Here, we need to calculate bspstore0, the value that ar.bspstore needs
307 // to be set to, based on bsp0 and the size of the dirty partition on
308 // the alternate stack (sc_loadrs >> 16). This can be done with the
309 // following algorithm:
311 // bspstore0 = rse_skip_regs(bsp0, -rse_num_regs(bsp1 - (loadrs >> 19), bsp1));
313 // This is what the code below does.
315 alloc r2=ar.pfs,0,0,0,0 // alloc null frame
316 adds r16=(LOADRS_OFF+SIGCONTEXT_OFF),sp
317 adds r18=(RNAT_OFF+SIGCONTEXT_OFF),sp
320 ld8 r16=[r18] // get new rnat
321 extr.u r18=r15,3,6 // r18 <- rse_slot_num(bsp0)
323 mov ar.rsc=r17 // put RSE into enforced lazy mode
326 sub r14=r14,r17 // r14 (bspstore1) <- bsp1 - (sc_loadrs >> 16)
327 shr.u r17=r17,3 // r17 <- (sc_loadrs >> 19)
329 loadrs // restore dirty partition
330 extr.u r14=r14,3,6 // r14 <- rse_slot_num(bspstore1)
332 add r14=r14,r17 // r14 <- rse_slot_num(bspstore1) + (sc_loadrs >> 19)
334 shr.u r14=r14,6 // r14 <- (rse_slot_num(bspstore1) + (sc_loadrs >> 19))/0x40
336 sub r14=r14,r17 // r14 <- -rse_num_regs(bspstore1, bsp1)
337 movl r17=0x8208208208208209
339 add r18=r18,r14 // r18 (delta) <- rse_slot_num(bsp0) - rse_num_regs(bspstore1,bsp1)
341 cmp.lt p7,p0=r14,r0 // p7 <- (r14 < 0)?
343 (p7) adds r18=-62,r18 // delta -= 62
356 sub r17=r17,r18 // r17 = delta/63
358 add r17=r14,r17 // r17 <- delta/63 - rse_num_regs(bspstore1, bsp1)
360 shladd r15=r17,3,r15 // r15 <- bsp0 + 8*(delta/63 - rse_num_regs(bspstore1, bsp1))
362 mov ar.bspstore=r15 // switch back to old register backing store area
364 mov ar.rnat=r16 // restore RNaT
365 mov ar.rsc=0xf // (will be restored later on from sc_ar_rsc)
366 // invala not necessary as that will happen when returning to user-mode
367 br.cond.sptk back_from_restore_rbs
368 END(__kernel_sigtramp)