4 * Copyright (C) 1999 Intel Corp.
5 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
6 * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
7 * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 1999 VA Linux Systems
10 * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
12 * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O APIC code.
13 * In particular, we now have separate handlers for edge
14 * and level triggered interrupts.
15 * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector allocation
16 * PCI to vector mapping, shared PCI interrupts.
17 * 00/10/27 D. Mosberger Document things a bit more to make them more understandable.
18 * Clean up much of the old IOSAPIC cruft.
19 * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts and fixes for
20 * ACPI S5(SoftOff) support.
21 * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT
22 * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt vectors in
23 * iosapic_set_affinity(), initializations for
24 * /proc/irq/#/smp_affinity
25 * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing.
26 * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq
27 * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to IOSAPIC mapping
29 * 02/07/29 T. Kochi Allocate interrupt vectors dynamically
30 * 02/08/04 T. Kochi Cleaned up terminology (irq, global system interrupt, vector, etc.)
31 * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's pci_irq code.
32 * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC.
33 * Remove iosapic_address & gsi_base from external interfaces.
34 * Rationalize __init/__devinit attributes.
37 * Here is what the interrupt logic between a PCI device and the kernel looks like:
39 * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, INTD). The
40 * device is uniquely identified by its bus--, and slot-number (the function
41 * number does not matter here because all functions share the same interrupt
44 * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC controller.
45 * Multiple interrupt lines may have to share the same IOSAPIC pin (if they're level
46 * triggered and use the same polarity). Each interrupt line has a unique Global
47 * System Interrupt (GSI) number which can be calculated as the sum of the controller's
48 * base GSI number and the IOSAPIC pin number to which the line connects.
50 * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the IOSAPIC pin
51 * into the IA-64 interrupt vector. This interrupt vector is then sent to the CPU.
53 * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is used as
54 * architecture-independent interrupt handling mechanism in Linux. As an
55 * IRQ is a number, we have to have IA-64 interrupt vector number <-> IRQ number
56 * mapping. On smaller systems, we use one-to-one mapping between IA-64 vector and
57 * IRQ. A platform can implement platform_irq_to_vector(irq) and
58 * platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
59 * Please see also include/asm-ia64/hw_irq.h for those APIs.
61 * To sum up, there are three levels of mappings involved:
63 * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
65 * Note: The term "IRQ" is loosely used everywhere in Linux kernel to describe interrupts.
66 * Now we use "IRQ" only for Linux IRQ's. ISA IRQ (isa_irq) is the only exception in this
69 #include <linux/config.h>
71 #include <linux/acpi.h>
72 #include <linux/init.h>
73 #include <linux/irq.h>
74 #include <linux/kernel.h>
75 #include <linux/list.h>
76 #include <linux/pci.h>
77 #include <linux/smp.h>
78 #include <linux/smp_lock.h>
79 #include <linux/string.h>
81 #include <asm/delay.h>
82 #include <asm/hw_irq.h>
84 #include <asm/iosapic.h>
85 #include <asm/machvec.h>
86 #include <asm/processor.h>
87 #include <asm/ptrace.h>
88 #include <asm/system.h>
91 #undef DEBUG_INTERRUPT_ROUTING
94 #ifdef DEBUG_INTERRUPT_ROUTING
95 #define DBG(fmt...) printk(fmt)
100 static spinlock_t iosapic_lock = SPIN_LOCK_UNLOCKED;
102 /* These tables map IA-64 vectors to the IOSAPIC pin that generates this vector. */
104 static struct iosapic_intr_info {
105 char *addr; /* base address of IOSAPIC */
106 u32 low32; /* current value of low word of Redirection table entry */
107 unsigned int gsi_base; /* first GSI assigned to this IOSAPIC */
108 char rte_index; /* IOSAPIC RTE index (-1 => not an IOSAPIC interrupt) */
109 unsigned char dmode : 3; /* delivery mode (see iosapic.h) */
110 unsigned char polarity: 1; /* interrupt polarity (see iosapic.h) */
111 unsigned char trigger : 1; /* trigger mode (see iosapic.h) */
112 } iosapic_intr_info[IA64_NUM_VECTORS];
114 static struct iosapic {
115 char *addr; /* base address of IOSAPIC */
116 unsigned int gsi_base; /* first GSI assigned to this IOSAPIC */
117 unsigned short num_rte; /* number of RTE in this IOSAPIC */
118 } iosapic_lists[NR_IOSAPICS];
120 static int num_iosapic;
122 static unsigned char pcat_compat __initdata; /* 8259 compatibility flag */
126 * Find an IOSAPIC associated with a GSI
129 find_iosapic (unsigned int gsi)
133 for (i = 0; i < num_iosapic; i++) {
134 if ((unsigned) (gsi - iosapic_lists[i].gsi_base) < iosapic_lists[i].num_rte)
142 _gsi_to_vector (unsigned int gsi)
144 struct iosapic_intr_info *info;
146 for (info = iosapic_intr_info; info < iosapic_intr_info + IA64_NUM_VECTORS; ++info)
147 if (info->gsi_base + info->rte_index == gsi)
148 return info - iosapic_intr_info;
153 * Translate GSI number to the corresponding IA-64 interrupt vector. If no
154 * entry exists, return -1.
157 gsi_to_vector (unsigned int gsi)
159 return _gsi_to_vector(gsi);
163 gsi_to_irq (unsigned int gsi)
166 * XXX fix me: this assumes an identity mapping vetween IA-64 vector and Linux irq
169 return _gsi_to_vector(gsi);
173 set_rte (unsigned int vector, unsigned int dest, int mask)
175 unsigned long pol, trigger, dmode, flags;
181 DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);
183 rte_index = iosapic_intr_info[vector].rte_index;
185 return; /* not an IOSAPIC interrupt */
187 addr = iosapic_intr_info[vector].addr;
188 pol = iosapic_intr_info[vector].polarity;
189 trigger = iosapic_intr_info[vector].trigger;
190 dmode = iosapic_intr_info[vector].dmode;
192 redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
197 for (irq = 0; irq < NR_IRQS; ++irq)
198 if (irq_to_vector(irq) == vector) {
199 set_irq_affinity_info(irq, (int)(dest & 0xffff), redir);
205 low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
206 (trigger << IOSAPIC_TRIGGER_SHIFT) |
207 (dmode << IOSAPIC_DELIVERY_SHIFT) |
208 ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) |
211 /* dest contains both id and eid */
212 high32 = (dest << IOSAPIC_DEST_SHIFT);
214 spin_lock_irqsave(&iosapic_lock, flags);
216 writel(IOSAPIC_RTE_HIGH(rte_index), addr + IOSAPIC_REG_SELECT);
217 writel(high32, addr + IOSAPIC_WINDOW);
218 writel(IOSAPIC_RTE_LOW(rte_index), addr + IOSAPIC_REG_SELECT);
219 writel(low32, addr + IOSAPIC_WINDOW);
220 iosapic_intr_info[vector].low32 = low32;
222 spin_unlock_irqrestore(&iosapic_lock, flags);
226 nop (unsigned int vector)
232 mask_irq (unsigned int irq)
238 ia64_vector vec = irq_to_vector(irq);
240 addr = iosapic_intr_info[vec].addr;
241 rte_index = iosapic_intr_info[vec].rte_index;
244 return; /* not an IOSAPIC interrupt! */
246 spin_lock_irqsave(&iosapic_lock, flags);
248 writel(IOSAPIC_RTE_LOW(rte_index), addr + IOSAPIC_REG_SELECT);
250 /* set only the mask bit */
251 low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK;
253 writel(low32, addr + IOSAPIC_WINDOW);
255 spin_unlock_irqrestore(&iosapic_lock, flags);
259 unmask_irq (unsigned int irq)
265 ia64_vector vec = irq_to_vector(irq);
267 addr = iosapic_intr_info[vec].addr;
268 rte_index = iosapic_intr_info[vec].rte_index;
270 return; /* not an IOSAPIC interrupt! */
272 spin_lock_irqsave(&iosapic_lock, flags);
274 writel(IOSAPIC_RTE_LOW(rte_index), addr + IOSAPIC_REG_SELECT);
275 low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK;
276 writel(low32, addr + IOSAPIC_WINDOW);
278 spin_unlock_irqrestore(&iosapic_lock, flags);
283 iosapic_set_affinity (unsigned int irq, cpumask_t mask)
290 int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
293 irq &= (~IA64_IRQ_REDIRECTED);
294 vec = irq_to_vector(irq);
296 if (cpus_empty(mask))
299 dest = cpu_physical_id(first_cpu(mask));
301 rte_index = iosapic_intr_info[vec].rte_index;
302 addr = iosapic_intr_info[vec].addr;
305 return; /* not an IOSAPIC interrupt */
307 set_irq_affinity_info(irq, dest, redir);
309 /* dest contains both id and eid */
310 high32 = dest << IOSAPIC_DEST_SHIFT;
312 spin_lock_irqsave(&iosapic_lock, flags);
314 /* get current delivery mode by reading the low32 */
315 writel(IOSAPIC_RTE_LOW(rte_index), addr + IOSAPIC_REG_SELECT);
316 low32 = iosapic_intr_info[vec].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT);
318 /* change delivery mode to lowest priority */
319 low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
321 /* change delivery mode to fixed */
322 low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
324 iosapic_intr_info[vec].low32 = low32;
325 writel(IOSAPIC_RTE_HIGH(rte_index), addr + IOSAPIC_REG_SELECT);
326 writel(high32, addr + IOSAPIC_WINDOW);
327 writel(IOSAPIC_RTE_LOW(rte_index), addr + IOSAPIC_REG_SELECT);
328 writel(low32, addr + IOSAPIC_WINDOW);
330 spin_unlock_irqrestore(&iosapic_lock, flags);
335 * Handlers for level-triggered interrupts.
339 iosapic_startup_level_irq (unsigned int irq)
346 iosapic_end_level_irq (unsigned int irq)
348 ia64_vector vec = irq_to_vector(irq);
350 writel(vec, iosapic_intr_info[vec].addr + IOSAPIC_EOI);
353 #define iosapic_shutdown_level_irq mask_irq
354 #define iosapic_enable_level_irq unmask_irq
355 #define iosapic_disable_level_irq mask_irq
356 #define iosapic_ack_level_irq nop
358 struct hw_interrupt_type irq_type_iosapic_level = {
359 .typename = "IO-SAPIC-level",
360 .startup = iosapic_startup_level_irq,
361 .shutdown = iosapic_shutdown_level_irq,
362 .enable = iosapic_enable_level_irq,
363 .disable = iosapic_disable_level_irq,
364 .ack = iosapic_ack_level_irq,
365 .end = iosapic_end_level_irq,
366 .set_affinity = iosapic_set_affinity
370 * Handlers for edge-triggered interrupts.
374 iosapic_startup_edge_irq (unsigned int irq)
378 * IOSAPIC simply drops interrupts pended while the
379 * corresponding pin was masked, so we can't know if an
380 * interrupt is pending already. Let's hope not...
386 iosapic_ack_edge_irq (unsigned int irq)
388 irq_desc_t *idesc = irq_descp(irq);
390 * Once we have recorded IRQ_PENDING already, we can mask the
391 * interrupt for real. This prevents IRQ storms from unhandled
394 if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) == (IRQ_PENDING|IRQ_DISABLED))
398 #define iosapic_enable_edge_irq unmask_irq
399 #define iosapic_disable_edge_irq nop
400 #define iosapic_end_edge_irq nop
402 struct hw_interrupt_type irq_type_iosapic_edge = {
403 .typename = "IO-SAPIC-edge",
404 .startup = iosapic_startup_edge_irq,
405 .shutdown = iosapic_disable_edge_irq,
406 .enable = iosapic_enable_edge_irq,
407 .disable = iosapic_disable_edge_irq,
408 .ack = iosapic_ack_edge_irq,
409 .end = iosapic_end_edge_irq,
410 .set_affinity = iosapic_set_affinity
414 iosapic_version (char *addr)
417 * IOSAPIC Version Register return 32 bit structure like:
419 * unsigned int version : 8;
420 * unsigned int reserved1 : 8;
421 * unsigned int max_redir : 8;
422 * unsigned int reserved2 : 8;
425 writel(IOSAPIC_VERSION, addr + IOSAPIC_REG_SELECT);
426 return readl(IOSAPIC_WINDOW + addr);
430 * if the given vector is already owned by other,
431 * assign a new vector for the other and make the vector available
434 iosapic_reassign_vector (int vector)
438 if (iosapic_intr_info[vector].rte_index >= 0 || iosapic_intr_info[vector].addr
439 || iosapic_intr_info[vector].gsi_base || iosapic_intr_info[vector].dmode
440 || iosapic_intr_info[vector].polarity || iosapic_intr_info[vector].trigger)
442 new_vector = assign_irq_vector(AUTO_ASSIGN);
443 printk(KERN_INFO "Reassigning vector %d to %d\n", vector, new_vector);
444 memcpy(&iosapic_intr_info[new_vector], &iosapic_intr_info[vector],
445 sizeof(struct iosapic_intr_info));
446 memset(&iosapic_intr_info[vector], 0, sizeof(struct iosapic_intr_info));
447 iosapic_intr_info[vector].rte_index = -1;
452 register_intr (unsigned int gsi, int vector, unsigned char delivery,
453 unsigned long polarity, unsigned long trigger)
456 struct hw_interrupt_type *irq_type;
459 unsigned long gsi_base;
460 char *iosapic_address;
462 index = find_iosapic(gsi);
464 printk(KERN_WARNING "%s: No IOSAPIC for GSI 0x%x\n", __FUNCTION__, gsi);
468 iosapic_address = iosapic_lists[index].addr;
469 gsi_base = iosapic_lists[index].gsi_base;
471 rte_index = gsi - gsi_base;
472 iosapic_intr_info[vector].rte_index = rte_index;
473 iosapic_intr_info[vector].polarity = polarity;
474 iosapic_intr_info[vector].dmode = delivery;
475 iosapic_intr_info[vector].addr = iosapic_address;
476 iosapic_intr_info[vector].gsi_base = gsi_base;
477 iosapic_intr_info[vector].trigger = trigger;
479 if (trigger == IOSAPIC_EDGE)
480 irq_type = &irq_type_iosapic_edge;
482 irq_type = &irq_type_iosapic_level;
484 idesc = irq_descp(vector);
485 if (idesc->handler != irq_type) {
486 if (idesc->handler != &no_irq_type)
487 printk(KERN_WARNING "%s: changing vector %d from %s to %s\n",
488 __FUNCTION__, vector, idesc->handler->typename, irq_type->typename);
489 idesc->handler = irq_type;
494 * ACPI can describe IOSAPIC interrupts via static tables and namespace
495 * methods. This provides an interface to register those interrupts and
496 * program the IOSAPIC RTE.
499 iosapic_register_intr (unsigned int gsi,
500 unsigned long polarity, unsigned long trigger)
503 unsigned int dest = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
505 vector = gsi_to_vector(gsi);
507 vector = assign_irq_vector(AUTO_ASSIGN);
509 register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY,
512 printk(KERN_INFO "GSI 0x%x(%s,%s) -> CPU 0x%04x vector %d\n",
513 gsi, (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
514 (trigger == IOSAPIC_EDGE ? "edge" : "level"), dest, vector);
516 /* program the IOSAPIC routing table */
517 set_rte(vector, dest, 0);
522 * ACPI calls this when it finds an entry for a platform interrupt.
523 * Note that the irq_base and IOSAPIC address must be set in iosapic_init().
526 iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
527 int iosapic_vector, u16 eid, u16 id,
528 unsigned long polarity, unsigned long trigger)
530 unsigned char delivery;
532 unsigned int dest = ((id << 8) | eid) & 0xffff;
535 case ACPI_INTERRUPT_PMI:
536 vector = iosapic_vector;
538 * since PMI vector is alloc'd by FW(ACPI) not by kernel,
539 * we need to make sure the vector is available
541 iosapic_reassign_vector(vector);
542 delivery = IOSAPIC_PMI;
544 case ACPI_INTERRUPT_INIT:
545 vector = assign_irq_vector(AUTO_ASSIGN);
546 delivery = IOSAPIC_INIT;
548 case ACPI_INTERRUPT_CPEI:
549 vector = IA64_CPE_VECTOR;
550 delivery = IOSAPIC_LOWEST_PRIORITY;
553 printk(KERN_ERR "iosapic_register_platform_irq(): invalid int type\n");
557 register_intr(gsi, vector, delivery, polarity,
560 printk(KERN_INFO "PLATFORM int 0x%x: GSI 0x%x(%s,%s) -> CPU 0x%04x vector %d\n",
561 int_type, gsi, (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
562 (trigger == IOSAPIC_EDGE ? "edge" : "level"), dest, vector);
564 /* program the IOSAPIC routing table */
565 set_rte(vector, dest, 0);
571 * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
572 * Note that the gsi_base and IOSAPIC address must be set in iosapic_init().
575 iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
576 unsigned long polarity,
577 unsigned long trigger)
580 unsigned int dest = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
582 vector = isa_irq_to_vector(isa_irq);
584 register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, polarity, trigger);
586 DBG("ISA: IRQ %u -> GSI 0x%x (%s,%s) -> CPU 0x%04x vector %d\n",
587 isa_irq, gsi, polarity == IOSAPIC_POL_HIGH ? "high" : "low",
588 trigger == IOSAPIC_EDGE ? "edge" : "level", dest, vector);
590 /* program the IOSAPIC routing table */
591 set_rte(vector, dest, 0);
595 iosapic_system_init (int system_pcat_compat)
599 for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
600 iosapic_intr_info[vector].rte_index = -1; /* mark as unused */
602 pcat_compat = system_pcat_compat;
605 * Disable the compatibility mode interrupts (8259 style), needs IN/OUT support
608 printk(KERN_INFO "%s: Disabling PC-AT compatible 8259 interrupts\n", __FUNCTION__);
615 iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
618 unsigned int isa_irq, ver;
621 addr = ioremap(phys_addr, 0);
622 ver = iosapic_version(addr);
625 * The MAX_REDIR register holds the highest input pin
626 * number (starting from 0).
627 * We add 1 so that we can use it for number of pins (= RTEs)
629 num_rte = ((ver >> 16) & 0xff) + 1;
631 iosapic_lists[num_iosapic].addr = addr;
632 iosapic_lists[num_iosapic].gsi_base = gsi_base;
633 iosapic_lists[num_iosapic].num_rte = num_rte;
636 if ((gsi_base == 0) && pcat_compat) {
638 * Map the legacy ISA devices into the IOSAPIC data. Some of these may
639 * get reprogrammed later on with data from the ACPI Interrupt Source
642 for (isa_irq = 0; isa_irq < 16; ++isa_irq)
643 iosapic_override_isa_irq(isa_irq, isa_irq, IOSAPIC_POL_HIGH, IOSAPIC_EDGE);
648 iosapic_enable_intr (unsigned int vector)
654 * In the case of a shared interrupt, do not re-route the vector, and
655 * especially do not mask a running interrupt (startup will not get
656 * called for a shared interrupt).
658 desc = irq_descp(vector);
664 * For platforms that do not support interrupt redirect via the XTP interface, we
665 * can round-robin the PCI device interrupts to the processors
667 if (!(smp_int_redirect & SMP_IRQ_REDIRECTION)) {
668 static int cpu_index = -1;
671 if (++cpu_index >= NR_CPUS)
673 while (!cpu_online(cpu_index));
675 dest = cpu_physical_id(cpu_index) & 0xffff;
678 * Direct the interrupt vector to the current cpu, platform redirection
679 * will distribute them.
681 dest = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
684 /* direct the interrupt vector to the running cpu id */
685 dest = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
687 set_rte(vector, dest, 1);
689 printk(KERN_INFO "IOSAPIC: vector %d -> CPU 0x%04x, enabled\n",
693 #ifdef CONFIG_ACPI_PCI
696 iosapic_parse_prt (void)
698 struct acpi_prt_entry *entry;
699 struct list_head *node;
703 struct hw_interrupt_type *irq_type = &irq_type_iosapic_level;
706 list_for_each(node, &acpi_prt.entries) {
707 entry = list_entry(node, struct acpi_prt_entry, node);
709 /* We're only interested in static (non-link) entries. */
710 if (entry->link.handle)
713 gsi = entry->link.index;
715 vector = gsi_to_vector(gsi);
717 if (find_iosapic(gsi) < 0)
720 /* allocate a vector for this interrupt line */
721 if (pcat_compat && (gsi < 16))
722 vector = isa_irq_to_vector(gsi);
724 /* new GSI; allocate a vector for it */
725 vector = assign_irq_vector(AUTO_ASSIGN);
727 register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, IOSAPIC_POL_LOW,
731 snprintf(pci_id, sizeof(pci_id), "%02x:%02x:%02x[%c]",
732 entry->id.segment, entry->id.bus, entry->id.device, 'A' + entry->pin);
735 * If vector was previously initialized to a different
736 * handler, re-initialize.
738 idesc = irq_descp(vector);
739 if (idesc->handler != irq_type)
740 register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, IOSAPIC_POL_LOW,
746 #endif /* CONFIG_ACPI */